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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 677433002: Add floor, ceil, round (truncate) instructions for ia32, x64 (if SSE4.1) and (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Address changes and fix compilation on mac. Created 6 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 26 matching lines...) Expand all
37 V(ArmVcmpF64) \ 37 V(ArmVcmpF64) \
38 V(ArmVaddF64) \ 38 V(ArmVaddF64) \
39 V(ArmVsubF64) \ 39 V(ArmVsubF64) \
40 V(ArmVmulF64) \ 40 V(ArmVmulF64) \
41 V(ArmVmlaF64) \ 41 V(ArmVmlaF64) \
42 V(ArmVmlsF64) \ 42 V(ArmVmlsF64) \
43 V(ArmVdivF64) \ 43 V(ArmVdivF64) \
44 V(ArmVmodF64) \ 44 V(ArmVmodF64) \
45 V(ArmVnegF64) \ 45 V(ArmVnegF64) \
46 V(ArmVsqrtF64) \ 46 V(ArmVsqrtF64) \
47 V(ArmVfloorF64) \
48 V(ArmVceilF64) \
49 V(ArmVroundTruncateF64) \
50 V(ArmVroundTiesAwayF64) \
47 V(ArmVcvtF32F64) \ 51 V(ArmVcvtF32F64) \
48 V(ArmVcvtF64F32) \ 52 V(ArmVcvtF64F32) \
49 V(ArmVcvtF64S32) \ 53 V(ArmVcvtF64S32) \
50 V(ArmVcvtF64U32) \ 54 V(ArmVcvtF64U32) \
51 V(ArmVcvtS32F64) \ 55 V(ArmVcvtS32F64) \
52 V(ArmVcvtU32F64) \ 56 V(ArmVcvtU32F64) \
53 V(ArmVldrF32) \ 57 V(ArmVldrF32) \
54 V(ArmVstrF32) \ 58 V(ArmVstrF32) \
55 V(ArmVldrF64) \ 59 V(ArmVldrF64) \
56 V(ArmVstrF64) \ 60 V(ArmVstrF64) \
(...skipping 25 matching lines...) Expand all
82 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 86 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
83 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 87 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
84 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 88 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
85 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 89 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
86 90
87 } // namespace compiler 91 } // namespace compiler
88 } // namespace internal 92 } // namespace internal
89 } // namespace v8 93 } // namespace v8
90 94
91 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 95 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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