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Issue 6678002: Fix incorrect assumption about BIT_AND on smis on ARM. (Closed) Base URL: http://v8.googlecode.com/svn/branches/2.4/
Patch Set: Created 9 years, 9 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 1131 matching lines...) Expand 10 before | Expand all | Expand 10 after
1142 case Token::SHL: 1142 case Token::SHL:
1143 ASSERT(!reversed_); 1143 ASSERT(!reversed_);
1144 if (shift_value != 0) { 1144 if (shift_value != 0) {
1145 __ mov(int32, Operand(int32, LSL, shift_value)); 1145 __ mov(int32, Operand(int32, LSL, shift_value));
1146 } 1146 }
1147 break; 1147 break;
1148 default: UNREACHABLE(); 1148 default: UNREACHABLE();
1149 } 1149 }
1150 // Check that the *signed* result fits in a smi. Not necessary for AND, SAR 1150 // Check that the *signed* result fits in a smi. Not necessary for AND, SAR
1151 // if the shift if more than 0 or SHR if the shit is more than 1. 1151 // if the shift if more than 0 or SHR if the shit is more than 1.
1152 if (!( (op_ == Token::AND) || 1152 if (!( (op_ == Token::AND && value_ >= 0) ||
1153 ((op_ == Token::SAR) && (shift_value > 0)) || 1153 ((op_ == Token::SAR) && (shift_value > 0)) ||
1154 ((op_ == Token::SHR) && (shift_value > 1)))) { 1154 ((op_ == Token::SHR) && (shift_value > 1)))) {
1155 __ add(r3, int32, Operand(0x40000000), SetCC); 1155 __ add(r3, int32, Operand(0x40000000), SetCC);
1156 __ b(mi, &result_not_a_smi); 1156 __ b(mi, &result_not_a_smi);
1157 } 1157 }
1158 __ mov(tos_register_, Operand(int32, LSL, kSmiTagSize)); 1158 __ mov(tos_register_, Operand(int32, LSL, kSmiTagSize));
1159 Exit(); 1159 Exit();
1160 1160
1161 if (result_not_a_smi.is_linked()) { 1161 if (result_not_a_smi.is_linked()) {
1162 __ bind(&result_not_a_smi); 1162 __ bind(&result_not_a_smi);
(...skipping 240 matching lines...) Expand 10 before | Expand all | Expand 10 after
1403 new DeferredInlineSmiOperation(op, int_value, reversed, mode, tos); 1403 new DeferredInlineSmiOperation(op, int_value, reversed, mode, tos);
1404 __ tst(tos, Operand(kSmiTagMask)); 1404 __ tst(tos, Operand(kSmiTagMask));
1405 deferred->JumpToNonSmiInput(ne); 1405 deferred->JumpToNonSmiInput(ne);
1406 switch (op) { 1406 switch (op) {
1407 case Token::BIT_OR: __ orr(tos, tos, Operand(value)); break; 1407 case Token::BIT_OR: __ orr(tos, tos, Operand(value)); break;
1408 case Token::BIT_XOR: __ eor(tos, tos, Operand(value)); break; 1408 case Token::BIT_XOR: __ eor(tos, tos, Operand(value)); break;
1409 case Token::BIT_AND: __ And(tos, tos, Operand(value)); break; 1409 case Token::BIT_AND: __ And(tos, tos, Operand(value)); break;
1410 default: UNREACHABLE(); 1410 default: UNREACHABLE();
1411 } 1411 }
1412 deferred->BindExit(); 1412 deferred->BindExit();
1413 TypeInfo result_type = 1413 TypeInfo result_type = TypeInfo::Integer32();
1414 (op == Token::BIT_AND) ? TypeInfo::Smi() : TypeInfo::Integer32(); 1414 if (op == Token::BIT_AND && int_value >= 0) {
1415 result_type = TypeInfo::Smi();
1416 }
1415 frame_->EmitPush(tos, result_type); 1417 frame_->EmitPush(tos, result_type);
1416 } 1418 }
1417 break; 1419 break;
1418 } 1420 }
1419 1421
1420 case Token::SHL: 1422 case Token::SHL:
1421 if (reversed) { 1423 if (reversed) {
1422 ASSERT(both_sides_are_smi); 1424 ASSERT(both_sides_are_smi);
1423 int max_shift = 0; 1425 int max_shift = 0;
1424 int max_result = int_value == 0 ? 1 : int_value; 1426 int max_result = int_value == 0 ? 1 : int_value;
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7315 BinaryOpIC::GetName(runtime_operands_type_)); 7317 BinaryOpIC::GetName(runtime_operands_type_));
7316 return name_; 7318 return name_;
7317 } 7319 }
7318 7320
7319 7321
7320 #undef __ 7322 #undef __
7321 7323
7322 } } // namespace v8::internal 7324 } } // namespace v8::internal
7323 7325
7324 #endif // V8_TARGET_ARCH_ARM 7326 #endif // V8_TARGET_ARCH_ARM
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