[turbofan] cleanup InstructionSequence

src/compiler/register-allocator.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/register-allocator.h"
 
 #include "src/compiler/linkage.h"
 #include "src/hydrogen.h"
 #include "src/string-stream.h"
 
@@ skipping 481 matching lines @@
       if (a == NULL || a->start().Value() > other->End().Value()) break;
       AdvanceLastProcessedMarker(a, advance_last_processed_up_to);
     } else {
       b = b->next();
     }
   }
   return LifetimePosition::Invalid();
 }
 
 
-RegisterAllocator::RegisterAllocator(InstructionSequence* code)
+RegisterAllocator::RegisterAllocator(Frame* frame, CompilationInfo* info,
+                                     InstructionSequence* code)
     : zone_(code->isolate()),
+      frame_(frame),
+      info_(info),
       code_(code),
-      live_in_sets_(code->BasicBlockCount(), zone()),
+      live_in_sets_(code->InstructionBlockCount(), zone()),
       live_ranges_(code->VirtualRegisterCount() * 2, zone()),
       fixed_live_ranges_(NULL),
       fixed_double_live_ranges_(NULL),
       unhandled_live_ranges_(code->VirtualRegisterCount() * 2, zone()),
       active_live_ranges_(8, zone()),
       inactive_live_ranges_(8, zone()),
       reusable_slots_(8, zone()),
       mode_(UNALLOCATED_REGISTERS),
       num_registers_(-1),
       allocation_ok_(true) {}
 
 
 void RegisterAllocator::InitializeLivenessAnalysis() {
   // Initialize the live_in sets for each block to NULL.
-  int block_count = code()->BasicBlockCount();
+  int block_count = code()->InstructionBlockCount();
   live_in_sets_.Initialize(block_count, zone());
   live_in_sets_.AddBlock(NULL, block_count, zone());
 }
 
 
 BitVector* RegisterAllocator::ComputeLiveOut(const InstructionBlock* block) {
   // Compute live out for the given block, except not including backward
   // successor edges.
   BitVector* live_out =
       new (zone()) BitVector(code()->VirtualRegisterCount(), zone());
@@ skipping 569 matching lines @@
   if (!AllocationOk()) return false;
   ResolvePhis();
   BuildLiveRanges();
   AllocateGeneralRegisters();
   if (!AllocationOk()) return false;
   AllocateDoubleRegisters();
   if (!AllocationOk()) return false;
   PopulatePointerMaps();
   ConnectRanges();
   ResolveControlFlow();
-  code()->frame()->SetAllocatedRegisters(assigned_registers_);
-  code()->frame()->SetAllocatedDoubleRegisters(assigned_double_registers_);
+  frame()->SetAllocatedRegisters(assigned_registers_);
+  frame()->SetAllocatedDoubleRegisters(assigned_double_registers_);
   return true;
 }
 
 
 void RegisterAllocator::MeetRegisterConstraints() {
   RegisterAllocatorPhase phase("L_Register constraints", this);
-  for (int i = 0; i < code()->BasicBlockCount(); ++i) {
+  for (int i = 0; i < code()->InstructionBlockCount(); ++i) {
     MeetRegisterConstraints(
         code()->InstructionBlockAt(BasicBlock::RpoNumber::FromInt(i)));
     if (!AllocationOk()) return;
   }
 }
 
 
 void RegisterAllocator::ResolvePhis() {
   RegisterAllocatorPhase phase("L_Resolve phis", this);
 
   // Process the blocks in reverse order.
-  for (int i = code()->BasicBlockCount() - 1; i >= 0; --i) {
+  for (int i = code()->InstructionBlockCount() - 1; i >= 0; --i) {
     ResolvePhis(code()->InstructionBlockAt(BasicBlock::RpoNumber::FromInt(i)));
   }
 }
 
 
 void RegisterAllocator::ResolveControlFlow(LiveRange* range,
                                            const InstructionBlock* block,
                                            const InstructionBlock* pred) {
   LifetimePosition pred_end =
       LifetimePosition::FromInstructionIndex(pred->last_instruction_index());
@@ skipping 100 matching lines @@
 
 bool RegisterAllocator::CanEagerlyResolveControlFlow(
     const InstructionBlock* block) const {
   if (block->PredecessorCount() != 1) return false;
   return block->predecessors()[0].IsNext(block->rpo_number());
 }
 
 
 void RegisterAllocator::ResolveControlFlow() {
   RegisterAllocatorPhase phase("L_Resolve control flow", this);
-  for (int block_id = 1; block_id < code()->BasicBlockCount(); ++block_id) {
+  for (int block_id = 1; block_id < code()->InstructionBlockCount();
+       ++block_id) {
     const InstructionBlock* block =
         code()->InstructionBlockAt(BasicBlock::RpoNumber::FromInt(block_id));
     if (CanEagerlyResolveControlFlow(block)) continue;
     BitVector* live = live_in_sets_[block->rpo_number().ToInt()];
     BitVector::Iterator iterator(live);
     while (!iterator.Done()) {
       int operand_index = iterator.Current();
       for (auto pred : block->predecessors()) {
         const InstructionBlock* cur = code()->InstructionBlockAt(pred);
         LiveRange* cur_range = LiveRangeFor(operand_index);
         ResolveControlFlow(cur_range, block, cur);
       }
       iterator.Advance();
     }
   }
 }
 
 
 void RegisterAllocator::BuildLiveRanges() {
   RegisterAllocatorPhase phase("L_Build live ranges", this);
   InitializeLivenessAnalysis();
   // Process the blocks in reverse order.
-  for (int block_id = code()->BasicBlockCount() - 1; block_id >= 0;
+  for (int block_id = code()->InstructionBlockCount() - 1; block_id >= 0;
        --block_id) {
     const InstructionBlock* block =
         code()->InstructionBlockAt(BasicBlock::RpoNumber::FromInt(block_id));
     BitVector* live = ComputeLiveOut(block);
     // Initially consider all live_out values live for the entire block. We
     // will shorten these intervals if necessary.
     AddInitialIntervals(block, live);
 
     // Process the instructions in reverse order, generating and killing
     // live values.
@@ skipping 62 matching lines @@
     if (block_id == 0) {
       BitVector::Iterator iterator(live);
       bool found = false;
       while (!iterator.Done()) {
         found = true;
         int operand_index = iterator.Current();
         PrintF("Register allocator error: live v%d reached first block.\n",
                operand_index);
         LiveRange* range = LiveRangeFor(operand_index);
         PrintF("  (first use is at %d)\n", range->first_pos()->pos().Value());
-        CompilationInfo* info = code()->linkage()->info();
+        CompilationInfo* info = this->info();
         if (info->IsStub()) {
           if (info->code_stub() == NULL) {
             PrintF("\n");
           } else {
             CodeStub::Major major_key = info->code_stub()->MajorKey();
             PrintF("  (function: %s)\n", CodeStub::MajorName(major_key, false));
           }
         } else {
           DCHECK(info->IsOptimizing());
           AllowHandleDereference allow_deref;
@@ skipping 569 matching lines @@
              current->id());
   SetLiveRangeAssignedRegister(current, reg);
 
   // This register was not free. Thus we need to find and spill
   // parts of active and inactive live regions that use the same register
   // at the same lifetime positions as current.
   SplitAndSpillIntersecting(current);
 }
 
 
+static const InstructionBlock* GetContainingLoop(
+    const InstructionSequence* sequence, const InstructionBlock* block) {
+  BasicBlock::RpoNumber index = block->loop_header();
+  if (!index.IsValid()) return NULL;
+  return sequence->InstructionBlockAt(index);
+}
+
+
 LifetimePosition RegisterAllocator::FindOptimalSpillingPos(
     LiveRange* range, LifetimePosition pos) {
   const InstructionBlock* block = GetInstructionBlock(pos.InstructionStart());
   const InstructionBlock* loop_header =
-      block->IsLoopHeader() ? block : code()->GetContainingLoop(block);
+      block->IsLoopHeader() ? block : GetContainingLoop(code(), block);
 
   if (loop_header == NULL) return pos;
 
   UsePosition* prev_use = range->PreviousUsePositionRegisterIsBeneficial(pos);
 
   while (loop_header != NULL) {
     // We are going to spill live range inside the loop.
     // If possible try to move spilling position backwards to loop header.
     // This will reduce number of memory moves on the back edge.
     LifetimePosition loop_start = LifetimePosition::FromInstructionIndex(
         loop_header->first_instruction_index());
 
     if (range->Covers(loop_start)) {
       if (prev_use == NULL || prev_use->pos().Value() < loop_start.Value()) {
         // No register beneficial use inside the loop before the pos.
         pos = loop_start;
       }
     }
 
     // Try hoisting out to an outer loop.
-    loop_header = code()->GetContainingLoop(loop_header);
+    loop_header = GetContainingLoop(code(), loop_header);
   }
 
   return pos;
 }
 
 
 void RegisterAllocator::SplitAndSpillIntersecting(LiveRange* current) {
   DCHECK(current->HasRegisterAssigned());
   int reg = current->assigned_register();
   LifetimePosition split_pos = current->Start();
@@ skipping 96 matching lines @@
 
   if (end_block == start_block) {
     // The interval is split in the same basic block. Split at the latest
     // possible position.
     return end;
   }
 
   const InstructionBlock* block = end_block;
   // Find header of outermost loop.
   // TODO(titzer): fix redundancy below.
-  while (code()->GetContainingLoop(block) != NULL &&
-         code()->GetContainingLoop(block)->rpo_number().ToInt() >
+  while (GetContainingLoop(code(), block) != NULL &&
+         GetContainingLoop(code(), block)->rpo_number().ToInt() >
              start_block->rpo_number().ToInt()) {
-    block = code()->GetContainingLoop(block);
+    block = GetContainingLoop(code(), block);
   }
 
   // We did not find any suitable outer loop. Split at the latest possible
   // position unless end_block is a loop header itself.
   if (block == end_block && !end_block->IsLoopHeader()) return end;
 
   return LifetimePosition::FromInstructionIndex(
       block->first_instruction_index());
 }
 
@@ skipping 43 matching lines @@
 void RegisterAllocator::Spill(LiveRange* range) {
   DCHECK(!range->IsSpilled());
   TraceAlloc("Spilling live range %d\n", range->id());
   LiveRange* first = range->TopLevel();
 
   if (!first->HasAllocatedSpillOperand()) {
     InstructionOperand* op = TryReuseSpillSlot(range);
     if (op == NULL) {
       // Allocate a new operand referring to the spill slot.
       RegisterKind kind = range->Kind();
-      int index = code()->frame()->AllocateSpillSlot(kind == DOUBLE_REGISTERS);
+      int index = frame()->AllocateSpillSlot(kind == DOUBLE_REGISTERS);
       if (kind == DOUBLE_REGISTERS) {
         op = DoubleStackSlotOperand::Create(index, zone());
       } else {
         DCHECK(kind == GENERAL_REGISTERS);
         op = StackSlotOperand::Create(index, zone());
       }
     }
     first->SetSpillOperand(op);
   }
   range->MakeSpilled(code_zone());
@@ skipping 24 matching lines @@
   } else {
     DCHECK(range->Kind() == GENERAL_REGISTERS);
     assigned_registers_->Add(reg);
   }
   range->set_assigned_register(reg, code_zone());
 }
 
 
 RegisterAllocatorPhase::RegisterAllocatorPhase(const char* name,
                                                RegisterAllocator* allocator)
-    : CompilationPhase(name, allocator->code()->linkage()->info()),
-      allocator_(allocator) {
+    : CompilationPhase(name, allocator->info()), allocator_(allocator) {
   if (FLAG_turbo_stats) {
     allocator_zone_start_allocation_size_ =
         allocator->zone()->allocation_size();
   }
 }
 
 
 RegisterAllocatorPhase::~RegisterAllocatorPhase() {
   if (FLAG_turbo_stats) {
     unsigned size = allocator_->zone()->allocation_size() -
                     allocator_zone_start_allocation_size_;
     isolate()->GetTStatistics()->SaveTiming(name(), base::TimeDelta(), size);
   }
 #ifdef DEBUG
   if (allocator_ != NULL) allocator_->Verify();
 #endif
 }
 }
 }
 }  // namespace v8::internal::compiler