[turbofan] cleanup InstructionSequence

src/compiler/pipeline.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/pipeline.h"
 
 #include <sstream>
 
 #include "src/base/platform/elapsed-timer.h"
 #include "src/compiler/ast-graph-builder.h"
@@ skipping 436 matching lines @@
   DCHECK_NOT_NULL(linkage);
   DCHECK_NOT_NULL(schedule);
   CHECK(SupportedBackend());
 
   BasicBlockProfiler::Data* profiler_data = NULL;
   if (FLAG_turbo_profiling) {
     profiler_data = BasicBlockInstrumentor::Instrument(info_, graph, schedule);
   }
 
   Zone* instruction_zone = schedule->zone();
-  InstructionSequence sequence(instruction_zone, linkage, graph, schedule);
+  InstructionSequence sequence(instruction_zone, graph, schedule);
 
   // Select and schedule instructions covering the scheduled graph.
   {
-    InstructionSelector selector(&sequence, schedule, source_positions);
+    InstructionSelector selector(linkage, &sequence, schedule,
+                                 source_positions);
     selector.SelectInstructions();
   }
 
   if (FLAG_trace_turbo) {
     OFStream os(stdout);
     os << "----- Instruction sequence before register allocation -----\n"
        << sequence;
     PrintScheduleAndInstructions("CodeGen", schedule, source_positions,
                                  &sequence);
   }
 
   // Allocate registers.
+  Frame frame;
   {
     int node_count = graph->NodeCount();
     if (node_count > UnallocatedOperand::kMaxVirtualRegisters) {
       linkage->info()->AbortOptimization(kNotEnoughVirtualRegistersForValues);
       return Handle<Code>::null();
     }
-    RegisterAllocator allocator(&sequence);
+    RegisterAllocator allocator(&frame, linkage->info(), &sequence);
     if (!allocator.Allocate()) {
       linkage->info()->AbortOptimization(kNotEnoughVirtualRegistersRegalloc);
       return Handle<Code>::null();
     }
     if (FLAG_trace_turbo) {
       PrintAllocator("CodeGen", &allocator);
     }
   }
 
   if (FLAG_trace_turbo) {
     OFStream os(stdout);
     os << "----- Instruction sequence after register allocation -----\n"
        << sequence;
   }
 
   // Generate native sequence.
-  CodeGenerator generator(&sequence);
+  CodeGenerator generator(&frame, linkage, &sequence);
   Handle<Code> code = generator.GenerateCode();
   if (profiler_data != NULL) {
 #if ENABLE_DISASSEMBLER
     std::ostringstream os;
     code->Disassemble(NULL, os);
     profiler_data->SetCode(&os);
 #endif
   }
   return code;
 }
 
 
 void Pipeline::SetUp() {
   InstructionOperand::SetUpCaches();
 }
 
 
 void Pipeline::TearDown() {
   InstructionOperand::TearDownCaches();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8