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Issue 6623073: Chromium: arm: tegra: Add NAND support (Closed) Base URL: http://git.chromium.org/git/u-boot-next.git@chromeos-v2010.09
Patch Set: Remove some unexpected lines of code and files Created 9 years, 9 months ago
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1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
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75 #define CLK_RST_CONTROLLER_PLLU_MISC_0 _MK_ADDR_CONST(0xcc) 75 #define CLK_RST_CONTROLLER_PLLU_MISC_0 _MK_ADDR_CONST(0xcc)
76 #define CLK_RST_CONTROLLER_PLLP_BASE_0 _MK_ADDR_CONST(0xa0) 76 #define CLK_RST_CONTROLLER_PLLP_BASE_0 _MK_ADDR_CONST(0xa0)
77 #define CLK_RST_CONTROLLER_PLLP_MISC_0 _MK_ADDR_CONST(0xac) 77 #define CLK_RST_CONTROLLER_PLLP_MISC_0 _MK_ADDR_CONST(0xac)
78 #define CLK_RST_CONTROLLER_PLLX_BASE_0 _MK_ADDR_CONST(0xe0) 78 #define CLK_RST_CONTROLLER_PLLX_BASE_0 _MK_ADDR_CONST(0xe0)
79 #define CLK_RST_CONTROLLER_PLLX_MISC_0 _MK_ADDR_CONST(0xe4) 79 #define CLK_RST_CONTROLLER_PLLX_MISC_0 _MK_ADDR_CONST(0xe4)
80 #define CLK_RST_CONTROLLER_OSC_CTRL_0 _MK_ADDR_CONST(0x50) 80 #define CLK_RST_CONTROLLER_OSC_CTRL_0 _MK_ADDR_CONST(0x50)
81 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0) 81 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0)
82 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0) 82 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0)
83 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0) 83 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0)
84 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0) 84 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0 _MK_ENUM _CONST(0)
85 #define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_MASK _MK_ENUM_CONST(3)
86 #define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT _MK_SHIFT_CONST(30)
87 #define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLP_OUT0 _MK_ENUM_CONST(0)
88 #define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_MASK _MK_ENUM_CONST(0xFF)
85 89
86 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT _MK_SHIFT_CONST(0) 90 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT _MK_SHIFT_CONST(0)
87 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT _MK_SHIFT_CONST(22 ) 91 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT _MK_SHIFT_CONST(22 )
88 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT _MK_SHIFT_CONST (15) 92 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT _MK_SHIFT_CONST (15)
89 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT _MK_SHIFT_CONST(12 ) 93 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT _MK_SHIFT_CONST(12 )
90 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT _MK_SHIFT_CONST(22 ) 94 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT _MK_SHIFT_CONST(22 )
91 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT _MK_SHIFT_CONST(3) 95 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT _MK_SHIFT_CONST(3)
92 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT _MK_SHIFT_CONST (13) 96 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT _MK_SHIFT_CONST (13)
93 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT _MK_SHIFT_CONST( 14) 97 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT _MK_SHIFT_CONST( 14)
94 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT _MK_SHIFT_CONST( 9) 98 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT _MK_SHIFT_CONST( 9)
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1159 #define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_SHIFT _MK_SHIFT_CONST(22) 1163 #define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_SHIFT _MK_SHIFT_CONST(22)
1160 #define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF) 1164 #define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
1161 #define APBDEV_PMC_SCRATCH_FOR_AVP_RESUME_PTR_0 APBDEV_PMC_SCRATCH39_0 1165 #define APBDEV_PMC_SCRATCH_FOR_AVP_RESUME_PTR_0 APBDEV_PMC_SCRATCH39_0
1162 1166
1163 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK _MK_MASK_CONST(0xff) 1167 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK _MK_MASK_CONST(0xff)
1164 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT _MK_SHIFT_CONST(0) 1168 #define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT _MK_SHIFT_CONST(0)
1165 1169
1166 #define PG_UP_TAG_0_PID_COP _MK_ENUM_CONST(-1431655766) / / // COP aka "arm2" aka "arm7" 1170 #define PG_UP_TAG_0_PID_COP _MK_ENUM_CONST(-1431655766) / / // COP aka "arm2" aka "arm7"
1167 1171
1168 #endif 1172 #endif
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