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Issue 66193004: Reland 17588: Add signed/unsigned 8-bit and 16-bit Representations to Crankshaft (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Latest version Created 7 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 366 matching lines...) Expand 10 before | Expand all | Expand 10 after
377 b(eq, &done); 377 b(eq, &done);
378 mov(dst, Operand::Zero(), LeaveCC, mi); // 0 if negative. 378 mov(dst, Operand::Zero(), LeaveCC, mi); // 0 if negative.
379 mov(dst, Operand(satval), LeaveCC, pl); // satval if positive. 379 mov(dst, Operand(satval), LeaveCC, pl); // satval if positive.
380 bind(&done); 380 bind(&done);
381 } else { 381 } else {
382 usat(dst, satpos, src, cond); 382 usat(dst, satpos, src, cond);
383 } 383 }
384 } 384 }
385 385
386 386
387 void MacroAssembler::Load(Register dst,
388 const MemOperand& src,
389 Representation r) {
390 ASSERT(!r.IsDouble());
391 if (r.IsInteger8()) {
392 ldrsb(dst, src);
393 } else if (r.IsUInteger8()) {
394 ldrb(dst, src);
395 } else if (r.IsInteger16()) {
396 ldrsh(dst, src);
397 } else if (r.IsUInteger16()) {
398 ldrh(dst, src);
399 } else {
400 ldr(dst, src);
401 }
402 }
403
404
405 void MacroAssembler::Store(Register src,
406 const MemOperand& dst,
407 Representation r) {
408 ASSERT(!r.IsDouble());
409 if (r.IsInteger8() || r.IsUInteger8()) {
410 strb(src, dst);
411 } else if (r.IsInteger16() || r.IsUInteger16()) {
412 strh(src, dst);
413 } else {
414 str(src, dst);
415 }
416 }
417
418
387 void MacroAssembler::LoadRoot(Register destination, 419 void MacroAssembler::LoadRoot(Register destination,
388 Heap::RootListIndex index, 420 Heap::RootListIndex index,
389 Condition cond) { 421 Condition cond) {
390 if (CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) && 422 if (CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
391 isolate()->heap()->RootCanBeTreatedAsConstant(index) && 423 isolate()->heap()->RootCanBeTreatedAsConstant(index) &&
392 !predictable_code_size()) { 424 !predictable_code_size()) {
393 // The CPU supports fast immediate values, and this root will never 425 // The CPU supports fast immediate values, and this root will never
394 // change. We will load it as a relocatable immediate value. 426 // change. We will load it as a relocatable immediate value.
395 Handle<Object> root(&isolate()->heap()->roots_array_start()[index]); 427 Handle<Object> root(&isolate()->heap()->roots_array_start()[index]);
396 mov(destination, Operand(root), LeaveCC, cond); 428 mov(destination, Operand(root), LeaveCC, cond);
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4018 void CodePatcher::EmitCondition(Condition cond) { 4050 void CodePatcher::EmitCondition(Condition cond) {
4019 Instr instr = Assembler::instr_at(masm_.pc_); 4051 Instr instr = Assembler::instr_at(masm_.pc_);
4020 instr = (instr & ~kCondMask) | cond; 4052 instr = (instr & ~kCondMask) | cond;
4021 masm_.emit(instr); 4053 masm_.emit(instr);
4022 } 4054 }
4023 4055
4024 4056
4025 } } // namespace v8::internal 4057 } } // namespace v8::internal
4026 4058
4027 #endif // V8_TARGET_ARCH_ARM 4059 #endif // V8_TARGET_ARCH_ARM
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