| Index: src/arm/assembler-arm.h
|
| ===================================================================
|
| --- src/arm/assembler-arm.h (revision 7031)
|
| +++ src/arm/assembler-arm.h (working copy)
|
| @@ -284,6 +284,7 @@
|
| const SwVfpRegister s30 = { 30 };
|
| const SwVfpRegister s31 = { 31 };
|
|
|
| +const DwVfpRegister no_dreg = { -1 };
|
| const DwVfpRegister d0 = { 0 };
|
| const DwVfpRegister d1 = { 1 };
|
| const DwVfpRegister d2 = { 2 };
|
| @@ -387,7 +388,7 @@
|
| // Return true if this is a register operand.
|
| INLINE(bool is_reg() const);
|
|
|
| - // Return true of this operand fits in one instruction so that no
|
| + // Return true if this operand fits in one instruction so that no
|
| // 2-instruction solution with a load into the ip register is necessary.
|
| bool is_single_instruction() const;
|
| bool must_use_constant_pool() const;
|
| @@ -439,7 +440,7 @@
|
| offset_ = offset;
|
| }
|
|
|
| - uint32_t offset() {
|
| + uint32_t offset() const {
|
| ASSERT(rm_.is(no_reg));
|
| return offset_;
|
| }
|
| @@ -447,6 +448,10 @@
|
| Register rn() const { return rn_; }
|
| Register rm() const { return rm_; }
|
|
|
| + bool OffsetIsUint12Encodable() const {
|
| + return offset_ >= 0 ? is_uint12(offset_) : is_uint12(-offset_);
|
| + }
|
| +
|
| private:
|
| Register rn_; // base
|
| Register rm_; // register offset
|
| @@ -742,6 +747,7 @@
|
| void cmp(Register src1, Register src2, Condition cond = al) {
|
| cmp(src1, Operand(src2), cond);
|
| }
|
| + void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);
|
|
|
| void cmn(Register src1, const Operand& src2, Condition cond = al);
|
|
|
| @@ -914,23 +920,35 @@
|
|
|
| void vldr(const DwVfpRegister dst,
|
| const Register base,
|
| - int offset, // Offset must be a multiple of 4.
|
| + int offset,
|
| const Condition cond = al);
|
| + void vldr(const DwVfpRegister dst,
|
| + const MemOperand& src,
|
| + const Condition cond = al);
|
|
|
| void vldr(const SwVfpRegister dst,
|
| const Register base,
|
| - int offset, // Offset must be a multiple of 4.
|
| + int offset,
|
| const Condition cond = al);
|
| + void vldr(const SwVfpRegister dst,
|
| + const MemOperand& src,
|
| + const Condition cond = al);
|
|
|
| void vstr(const DwVfpRegister src,
|
| const Register base,
|
| - int offset, // Offset must be a multiple of 4.
|
| + int offset,
|
| const Condition cond = al);
|
| + void vstr(const DwVfpRegister src,
|
| + const MemOperand& dst,
|
| + const Condition cond = al);
|
|
|
| void vstr(const SwVfpRegister src,
|
| const Register base,
|
| - int offset, // Offset must be a multiple of 4.
|
| + int offset,
|
| const Condition cond = al);
|
| + void vstr(const SwVfpRegister src,
|
| + const MemOperand& dst,
|
| + const Condition cond = al);
|
|
|
| void vmov(const DwVfpRegister dst,
|
| double imm,
|
| @@ -1112,6 +1130,7 @@
|
| static void instr_at_put(byte* pc, Instr instr) {
|
| *reinterpret_cast<Instr*>(pc) = instr;
|
| }
|
| + static Condition GetCondition(Instr instr);
|
| static bool IsBranch(Instr instr);
|
| static int GetBranchOffset(Instr instr);
|
| static bool IsLdrRegisterImmediate(Instr instr);
|
| @@ -1122,6 +1141,8 @@
|
| static bool IsAddRegisterImmediate(Instr instr);
|
| static Instr SetAddRegisterImmediateOffset(Instr instr, int offset);
|
| static Register GetRd(Instr instr);
|
| + static Register GetRn(Instr instr);
|
| + static Register GetRm(Instr instr);
|
| static bool IsPush(Instr instr);
|
| static bool IsPop(Instr instr);
|
| static bool IsStrRegFpOffset(Instr instr);
|
| @@ -1129,6 +1150,11 @@
|
| static bool IsStrRegFpNegOffset(Instr instr);
|
| static bool IsLdrRegFpNegOffset(Instr instr);
|
| static bool IsLdrPcImmediateOffset(Instr instr);
|
| + static bool IsTstImmediate(Instr instr);
|
| + static bool IsCmpRegister(Instr instr);
|
| + static bool IsCmpImmediate(Instr instr);
|
| + static Register GetCmpImmediateRegister(Instr instr);
|
| + static int GetCmpImmediateRawImmediate(Instr instr);
|
| static bool IsNop(Instr instr, int type = NON_MARKING_NOP);
|
|
|
| // Check if is time to emit a constant pool for pending reloc info entries
|
|
|