| OLD | NEW |
| 1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
| (...skipping 367 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 378 kDoublePrecision = 1 | 378 kDoublePrecision = 1 |
| 379 }; | 379 }; |
| 380 | 380 |
| 381 | 381 |
| 382 // VFP FPSCR constants. | 382 // VFP FPSCR constants. |
| 383 enum VFPConversionMode { | 383 enum VFPConversionMode { |
| 384 kFPSCRRounding = 0, | 384 kFPSCRRounding = 0, |
| 385 kDefaultRoundToZero = 1 | 385 kDefaultRoundToZero = 1 |
| 386 }; | 386 }; |
| 387 | 387 |
| 388 // This mask does not include the "inexact" or "input denormal" cumulative |
| 389 // exceptions flags, because we usually don't want to check for it. |
| 388 static const uint32_t kVFPExceptionMask = 0xf; | 390 static const uint32_t kVFPExceptionMask = 0xf; |
| 391 static const uint32_t kVFPInexactExceptionBit = 1 << 4; |
| 389 static const uint32_t kVFPFlushToZeroMask = 1 << 24; | 392 static const uint32_t kVFPFlushToZeroMask = 1 << 24; |
| 390 static const uint32_t kVFPInvalidExceptionBit = 1; | 393 static const uint32_t kVFPInvalidExceptionBit = 1; |
| 391 | 394 |
| 392 static const uint32_t kVFPNConditionFlagBit = 1 << 31; | 395 static const uint32_t kVFPNConditionFlagBit = 1 << 31; |
| 393 static const uint32_t kVFPZConditionFlagBit = 1 << 30; | 396 static const uint32_t kVFPZConditionFlagBit = 1 << 30; |
| 394 static const uint32_t kVFPCConditionFlagBit = 1 << 29; | 397 static const uint32_t kVFPCConditionFlagBit = 1 << 29; |
| 395 static const uint32_t kVFPVConditionFlagBit = 1 << 28; | 398 static const uint32_t kVFPVConditionFlagBit = 1 << 28; |
| 396 | 399 |
| 397 | 400 |
| 398 // VFP rounding modes. See ARM DDI 0406B Page A2-29. | 401 // VFP rounding modes. See ARM DDI 0406B Page A2-29. |
| 399 enum VFPRoundingMode { | 402 enum VFPRoundingMode { |
| 400 RN = 0 << 22, // Round to Nearest. | 403 RN = 0 << 22, // Round to Nearest. |
| 401 RP = 1 << 22, // Round towards Plus Infinity. | 404 RP = 1 << 22, // Round towards Plus Infinity. |
| 402 RM = 2 << 22, // Round towards Minus Infinity. | 405 RM = 2 << 22, // Round towards Minus Infinity. |
| 403 RZ = 3 << 22, // Round towards zero. | 406 RZ = 3 << 22, // Round towards zero. |
| 404 | 407 |
| 405 // Aliases. | 408 // Aliases. |
| 406 kRoundToNearest = RN, | 409 kRoundToNearest = RN, |
| 407 kRoundToPlusInf = RP, | 410 kRoundToPlusInf = RP, |
| 408 kRoundToMinusInf = RM, | 411 kRoundToMinusInf = RM, |
| 409 kRoundToZero = RZ | 412 kRoundToZero = RZ |
| 410 }; | 413 }; |
| 411 | 414 |
| 412 static const uint32_t kVFPRoundingModeMask = 3 << 22; | 415 static const uint32_t kVFPRoundingModeMask = 3 << 22; |
| 413 | 416 |
| 417 enum CheckForInexactConversion { |
| 418 kCheckForInexactConversion, |
| 419 kDontCheckForInexactConversion |
| 420 }; |
| 421 |
| 414 // ----------------------------------------------------------------------------- | 422 // ----------------------------------------------------------------------------- |
| 415 // Hints. | 423 // Hints. |
| 416 | 424 |
| 417 // Branch hints are not used on the ARM. They are defined so that they can | 425 // Branch hints are not used on the ARM. They are defined so that they can |
| 418 // appear in shared function signatures, but will be ignored in ARM | 426 // appear in shared function signatures, but will be ignored in ARM |
| 419 // implementations. | 427 // implementations. |
| 420 enum Hint { no_hint }; | 428 enum Hint { no_hint }; |
| 421 | 429 |
| 422 // Hints are not used on the arm. Negating is trivial. | 430 // Hints are not used on the arm. Negating is trivial. |
| 423 inline Hint NegateHint(Hint ignored) { return no_hint; } | 431 inline Hint NegateHint(Hint ignored) { return no_hint; } |
| (...skipping 151 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 575 } | 583 } |
| 576 inline Condition ConditionField() const { | 584 inline Condition ConditionField() const { |
| 577 return static_cast<Condition>(BitField(31, 28)); | 585 return static_cast<Condition>(BitField(31, 28)); |
| 578 } | 586 } |
| 579 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); | 587 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); |
| 580 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); | 588 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); |
| 581 | 589 |
| 582 inline int TypeValue() const { return Bits(27, 25); } | 590 inline int TypeValue() const { return Bits(27, 25); } |
| 583 | 591 |
| 584 inline int RnValue() const { return Bits(19, 16); } | 592 inline int RnValue() const { return Bits(19, 16); } |
| 593 DECLARE_STATIC_ACCESSOR(RnValue); |
| 585 inline int RdValue() const { return Bits(15, 12); } | 594 inline int RdValue() const { return Bits(15, 12); } |
| 586 DECLARE_STATIC_ACCESSOR(RdValue); | 595 DECLARE_STATIC_ACCESSOR(RdValue); |
| 587 | 596 |
| 588 inline int CoprocessorValue() const { return Bits(11, 8); } | 597 inline int CoprocessorValue() const { return Bits(11, 8); } |
| 589 // Support for VFP. | 598 // Support for VFP. |
| 590 // Vn(19-16) | Vd(15-12) | Vm(3-0) | 599 // Vn(19-16) | Vd(15-12) | Vm(3-0) |
| 591 inline int VnValue() const { return Bits(19, 16); } | 600 inline int VnValue() const { return Bits(19, 16); } |
| 592 inline int VmValue() const { return Bits(3, 0); } | 601 inline int VmValue() const { return Bits(3, 0); } |
| 593 inline int VdValue() const { return Bits(15, 12); } | 602 inline int VdValue() const { return Bits(15, 12); } |
| 594 inline int NValue() const { return Bit(7); } | 603 inline int NValue() const { return Bit(7); } |
| (...skipping 23 matching lines...) Expand all Loading... |
| 618 // Fields used in Data processing instructions | 627 // Fields used in Data processing instructions |
| 619 inline int OpcodeValue() const { | 628 inline int OpcodeValue() const { |
| 620 return static_cast<Opcode>(Bits(24, 21)); | 629 return static_cast<Opcode>(Bits(24, 21)); |
| 621 } | 630 } |
| 622 inline Opcode OpcodeField() const { | 631 inline Opcode OpcodeField() const { |
| 623 return static_cast<Opcode>(BitField(24, 21)); | 632 return static_cast<Opcode>(BitField(24, 21)); |
| 624 } | 633 } |
| 625 inline int SValue() const { return Bit(20); } | 634 inline int SValue() const { return Bit(20); } |
| 626 // with register | 635 // with register |
| 627 inline int RmValue() const { return Bits(3, 0); } | 636 inline int RmValue() const { return Bits(3, 0); } |
| 637 DECLARE_STATIC_ACCESSOR(RmValue); |
| 628 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } | 638 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } |
| 629 inline ShiftOp ShiftField() const { | 639 inline ShiftOp ShiftField() const { |
| 630 return static_cast<ShiftOp>(BitField(6, 5)); | 640 return static_cast<ShiftOp>(BitField(6, 5)); |
| 631 } | 641 } |
| 632 inline int RegShiftValue() const { return Bit(4); } | 642 inline int RegShiftValue() const { return Bit(4); } |
| 633 inline int RsValue() const { return Bits(11, 8); } | 643 inline int RsValue() const { return Bits(11, 8); } |
| 634 inline int ShiftAmountValue() const { return Bits(11, 7); } | 644 inline int ShiftAmountValue() const { return Bits(11, 7); } |
| 635 // with immediate | 645 // with immediate |
| 636 inline int RotateValue() const { return Bits(11, 8); } | 646 inline int RotateValue() const { return Bits(11, 8); } |
| 637 inline int Immed8Value() const { return Bits(7, 0); } | 647 inline int Immed8Value() const { return Bits(7, 0); } |
| (...skipping 112 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 750 static int Number(const char* name, bool* is_double); | 760 static int Number(const char* name, bool* is_double); |
| 751 | 761 |
| 752 private: | 762 private: |
| 753 static const char* names_[kNumVFPRegisters]; | 763 static const char* names_[kNumVFPRegisters]; |
| 754 }; | 764 }; |
| 755 | 765 |
| 756 | 766 |
| 757 } } // namespace v8::internal | 767 } } // namespace v8::internal |
| 758 | 768 |
| 759 #endif // V8_ARM_CONSTANTS_ARM_H_ | 769 #endif // V8_ARM_CONSTANTS_ARM_H_ |
| OLD | NEW |