| OLD | NEW |
| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
| (...skipping 937 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 948 void vmov(const Register dst1, | 948 void vmov(const Register dst1, |
| 949 const Register dst2, | 949 const Register dst2, |
| 950 const DwVfpRegister src, | 950 const DwVfpRegister src, |
| 951 const Condition cond = al); | 951 const Condition cond = al); |
| 952 void vmov(const SwVfpRegister dst, | 952 void vmov(const SwVfpRegister dst, |
| 953 const Register src, | 953 const Register src, |
| 954 const Condition cond = al); | 954 const Condition cond = al); |
| 955 void vmov(const Register dst, | 955 void vmov(const Register dst, |
| 956 const SwVfpRegister src, | 956 const SwVfpRegister src, |
| 957 const Condition cond = al); | 957 const Condition cond = al); |
| 958 enum ConversionMode { | |
| 959 FPSCRRounding = 0, | |
| 960 RoundToZero = 1 | |
| 961 }; | |
| 962 void vcvt_f64_s32(const DwVfpRegister dst, | 958 void vcvt_f64_s32(const DwVfpRegister dst, |
| 963 const SwVfpRegister src, | 959 const SwVfpRegister src, |
| 964 ConversionMode mode = RoundToZero, | 960 VFPConversionMode mode = kDefaultRoundToZero, |
| 965 const Condition cond = al); | 961 const Condition cond = al); |
| 966 void vcvt_f32_s32(const SwVfpRegister dst, | 962 void vcvt_f32_s32(const SwVfpRegister dst, |
| 967 const SwVfpRegister src, | 963 const SwVfpRegister src, |
| 968 ConversionMode mode = RoundToZero, | 964 VFPConversionMode mode = kDefaultRoundToZero, |
| 969 const Condition cond = al); | 965 const Condition cond = al); |
| 970 void vcvt_f64_u32(const DwVfpRegister dst, | 966 void vcvt_f64_u32(const DwVfpRegister dst, |
| 971 const SwVfpRegister src, | 967 const SwVfpRegister src, |
| 972 ConversionMode mode = RoundToZero, | 968 VFPConversionMode mode = kDefaultRoundToZero, |
| 973 const Condition cond = al); | 969 const Condition cond = al); |
| 974 void vcvt_s32_f64(const SwVfpRegister dst, | 970 void vcvt_s32_f64(const SwVfpRegister dst, |
| 975 const DwVfpRegister src, | 971 const DwVfpRegister src, |
| 976 ConversionMode mode = RoundToZero, | 972 VFPConversionMode mode = kDefaultRoundToZero, |
| 977 const Condition cond = al); | 973 const Condition cond = al); |
| 978 void vcvt_u32_f64(const SwVfpRegister dst, | 974 void vcvt_u32_f64(const SwVfpRegister dst, |
| 979 const DwVfpRegister src, | 975 const DwVfpRegister src, |
| 980 ConversionMode mode = RoundToZero, | 976 VFPConversionMode mode = kDefaultRoundToZero, |
| 981 const Condition cond = al); | 977 const Condition cond = al); |
| 982 void vcvt_f64_f32(const DwVfpRegister dst, | 978 void vcvt_f64_f32(const DwVfpRegister dst, |
| 983 const SwVfpRegister src, | 979 const SwVfpRegister src, |
| 984 ConversionMode mode = RoundToZero, | 980 VFPConversionMode mode = kDefaultRoundToZero, |
| 985 const Condition cond = al); | 981 const Condition cond = al); |
| 986 void vcvt_f32_f64(const SwVfpRegister dst, | 982 void vcvt_f32_f64(const SwVfpRegister dst, |
| 987 const DwVfpRegister src, | 983 const DwVfpRegister src, |
| 988 ConversionMode mode = RoundToZero, | 984 VFPConversionMode mode = kDefaultRoundToZero, |
| 989 const Condition cond = al); | 985 const Condition cond = al); |
| 990 | 986 |
| 987 void vabs(const DwVfpRegister dst, |
| 988 const DwVfpRegister src, |
| 989 const Condition cond = al); |
| 991 void vadd(const DwVfpRegister dst, | 990 void vadd(const DwVfpRegister dst, |
| 992 const DwVfpRegister src1, | 991 const DwVfpRegister src1, |
| 993 const DwVfpRegister src2, | 992 const DwVfpRegister src2, |
| 994 const Condition cond = al); | 993 const Condition cond = al); |
| 995 void vsub(const DwVfpRegister dst, | 994 void vsub(const DwVfpRegister dst, |
| 996 const DwVfpRegister src1, | 995 const DwVfpRegister src1, |
| 997 const DwVfpRegister src2, | 996 const DwVfpRegister src2, |
| 998 const Condition cond = al); | 997 const Condition cond = al); |
| 999 void vmul(const DwVfpRegister dst, | 998 void vmul(const DwVfpRegister dst, |
| 1000 const DwVfpRegister src1, | 999 const DwVfpRegister src1, |
| (...skipping 272 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1273 public: | 1272 public: |
| 1274 explicit EnsureSpace(Assembler* assembler) { | 1273 explicit EnsureSpace(Assembler* assembler) { |
| 1275 assembler->CheckBuffer(); | 1274 assembler->CheckBuffer(); |
| 1276 } | 1275 } |
| 1277 }; | 1276 }; |
| 1278 | 1277 |
| 1279 | 1278 |
| 1280 } } // namespace v8::internal | 1279 } } // namespace v8::internal |
| 1281 | 1280 |
| 1282 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1281 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
| OLD | NEW |