[arm] Prefer BIC over BFC.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
 // Adds Arm-specific methods for generating InstructionOperands.
 class ArmOperandGenerator : public OperandGenerator {
  public:
   explicit ArmOperandGenerator(InstructionSelector* selector)
       : OperandGenerator(selector) {}
 
   InstructionOperand* UseOperand(Node* node, InstructionCode opcode) {
     if (CanBeImmediate(node, opcode)) {
       return UseImmediate(node);
     }
     return UseRegister(node);
   }
 
+  bool CanBeImmediate(int32_t value) const {
+    return Assembler::ImmediateFitsAddrMode1Instruction(value);
+  }
+
+  bool CanBeImmediate(uint32_t value) const {
+    return CanBeImmediate(bit_cast<int32_t>(value));
+  }
+
   bool CanBeImmediate(Node* node, InstructionCode opcode) {
     Int32Matcher m(node);
     if (!m.HasValue()) return false;
     int32_t value = m.Value();
     switch (ArchOpcodeField::decode(opcode)) {
       case kArmAnd:
       case kArmMov:
       case kArmMvn:
       case kArmBic:
-        return ImmediateFitsAddrMode1Instruction(value) ||
-               ImmediateFitsAddrMode1Instruction(~value);
+        return CanBeImmediate(value) || CanBeImmediate(~value);
 
       case kArmAdd:
       case kArmSub:
       case kArmCmp:
       case kArmCmn:
-        return ImmediateFitsAddrMode1Instruction(value) ||
-               ImmediateFitsAddrMode1Instruction(-value);
+        return CanBeImmediate(value) || CanBeImmediate(-value);
 
       case kArmTst:
       case kArmTeq:
       case kArmOrr:
       case kArmEor:
       case kArmRsb:
-        return ImmediateFitsAddrMode1Instruction(value);
+        return CanBeImmediate(value);
 
       case kArmVldrF32:
       case kArmVstrF32:
       case kArmVldrF64:
       case kArmVstrF64:
         return value >= -1020 && value <= 1020 && (value % 4) == 0;
 
       case kArmLdrb:
       case kArmLdrsb:
       case kArmStrb:
@@ skipping 38 matching lines @@
       case kArmVcvtF64S32:
       case kArmVcvtF64U32:
       case kArmVcvtS32F64:
       case kArmVcvtU32F64:
       case kArmPush:
         return false;
     }
     UNREACHABLE();
     return false;
   }
-
- private:
-  bool ImmediateFitsAddrMode1Instruction(int32_t imm) const {
-    return Assembler::ImmediateFitsAddrMode1Instruction(imm);
-  }
 };
 
 
 static void VisitRRRFloat64(InstructionSelector* selector, ArchOpcode opcode,
                             Node* node) {
   ArmOperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)),
                  g.UseRegister(node->InputAt(1)));
 }
@@ skipping 286 matching lines @@
     }
   }
   if (m.right().IsWord32Xor() && CanCover(node, m.right().node())) {
     Int32BinopMatcher mright(m.right().node());
     if (mright.right().Is(-1)) {
       EmitBic(this, node, m.left().node(), mright.left().node());
       return;
     }
   }
   if (IsSupported(ARMv7) && m.right().HasValue()) {
-    uint32_t value = m.right().Value();
+    // Try to interpret this AND as UBFX.
+    uint32_t const value = m.right().Value();
     uint32_t width = base::bits::CountPopulation32(value);
     uint32_t msb = base::bits::CountLeadingZeros32(value);
     if (width != 0 && msb + width == 32) {
       DCHECK_EQ(0, base::bits::CountTrailingZeros32(value));
       if (m.left().IsWord32Shr()) {
         Int32BinopMatcher mleft(m.left().node());
         if (mleft.right().IsInRange(0, 31)) {
           Emit(kArmUbfx, g.DefineAsRegister(node),
                g.UseRegister(mleft.left().node()),
                g.UseImmediate(mleft.right().node()), g.TempImmediate(width));
           return;
         }
       }
       Emit(kArmUbfx, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
            g.TempImmediate(0), g.TempImmediate(width));
       return;
     }
+
+    // Try to interpret this AND as BIC.
+    if (g.CanBeImmediate(~value)) {
+      Emit(kArmBic | AddressingModeField::encode(kMode_Operand2_I),
+           g.DefineAsRegister(node), g.UseRegister(m.left().node()),
+           g.TempImmediate(~value));
+      return;
+    }
+
     // Try to interpret this AND as BFC.
     width = 32 - width;
     msb = base::bits::CountLeadingZeros32(~value);
     uint32_t lsb = base::bits::CountTrailingZeros32(~value);
     if (msb + width + lsb == 32) {
       Emit(kArmBfc, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
            g.TempImmediate(lsb), g.TempImmediate(width));
       return;
     }
   }
@@ skipping 704 matching lines @@
 
 
 void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
   FlagsContinuation cont(kUnorderedLessThanOrEqual, node);
   VisitFloat64Compare(this, node, &cont);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8