| Index: src/arm/assembler-arm.cc
|
| ===================================================================
|
| --- src/arm/assembler-arm.cc (revision 6941)
|
| +++ src/arm/assembler-arm.cc (working copy)
|
| @@ -2339,12 +2339,11 @@
|
|
|
| void Assembler::vcmp(const DwVfpRegister src1,
|
| const DwVfpRegister src2,
|
| - const SBit s,
|
| const Condition cond) {
|
| // vcmp(Dd, Dm) double precision floating point comparison.
|
| // Instruction details available in ARM DDI 0406A, A8-570.
|
| // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
|
| - // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | Vm(3-0)
|
| + // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | Vm(3-0)
|
| ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
|
| emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
|
| src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());
|
| @@ -2353,12 +2352,11 @@
|
|
|
| void Assembler::vcmp(const DwVfpRegister src1,
|
| const double src2,
|
| - const SBit s,
|
| const Condition cond) {
|
| // vcmp(Dd, Dm) double precision floating point comparison.
|
| // Instruction details available in ARM DDI 0406A, A8-570.
|
| // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) |
|
| - // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | 0000(3-0)
|
| + // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | 0000(3-0)
|
| ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3));
|
| ASSERT(src2 == 0.0);
|
| emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 |
|
|
|