[Isolates] Merge from bleeding_edge to isolates, revisions 6100-6300.

src/x64/assembler-x64.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 80 matching lines @@
   // The non-allocatable registers are:
   //  rsp - stack pointer
   //  rbp - frame pointer
   //  rsi - context register
   //  r10 - fixed scratch register
   //  r13 - root register
   //  r15 - smi constant register
   static const int kNumRegisters = 16;
   static const int kNumAllocatableRegisters = 10;
 
+  static int ToAllocationIndex(Register reg) {
+    return allocationIndexByRegisterCode[reg.code()];
+  }
+
+  static Register FromAllocationIndex(int index) {
+    ASSERT(index >= 0 && index < kNumAllocatableRegisters);
+    Register result = { registerCodeByAllocationIndex[index] };
+    return result;
+  }
+
   static const char* AllocationIndexToString(int index) {
     ASSERT(index >= 0 && index < kNumAllocatableRegisters);
     const char* const names[] = {
       "rax",
       "rcx",
       "rdx",
       "rbx",
       "rdi",
       "r8",
       "r9",
@@ skipping 25 matching lines @@
   }
   // Return the 3 low bits of the register code.  Used when encoding registers
   // in modR/M, SIB, and opcode bytes.
   int low_bits() const {
     return code_ & 0x7;
   }
 
   // Unfortunately we can't make this private in a struct when initializing
   // by assignment.
   int code_;
+ private:
+  static const int registerCodeByAllocationIndex[kNumAllocatableRegisters];
+  static const int allocationIndexByRegisterCode[kNumRegisters];
 };
 
 const Register rax = { 0 };
 const Register rcx = { 1 };
 const Register rdx = { 2 };
 const Register rbx = { 3 };
 const Register rsp = { 4 };
 const Register rbp = { 5 };
 const Register rsi = { 6 };
 const Register rdi = { 7 };
@@ skipping 10 matching lines @@
 
 struct XMMRegister {
   static const int kNumRegisters = 16;
   static const int kNumAllocatableRegisters = 15;
 
   static int ToAllocationIndex(XMMRegister reg) {
     ASSERT(reg.code() != 0);
     return reg.code() - 1;
   }
 
+  static XMMRegister FromAllocationIndex(int index) {
+    ASSERT(0 <= index && index < kNumAllocatableRegisters);
+    XMMRegister result = { index + 1 };
+    return result;
+  }
+
   static const char* AllocationIndexToString(int index) {
     ASSERT(index >= 0 && index < kNumAllocatableRegisters);
     const char* const names[] = {
       "xmm1",
       "xmm2",
       "xmm3",
       "xmm4",
       "xmm5",
       "xmm6",
       "xmm7",
@@ skipping 361 matching lines @@
   static const int kRealPatchReturnSequenceAddressOffset = 2;
 
   // The x64 JS return sequence is padded with int3 to make it large
   // enough to hold a call instruction when the debugger patches it.
   static const int kCallInstructionLength = 13;
   static const int kJSReturnSequenceLength = 13;
 
   // The debug break slot must be able to contain a call instruction.
   static const int kDebugBreakSlotLength = kCallInstructionLength;
 
+  // One byte opcode for test eax,0xXXXXXXXX.
+  static const byte kTestEaxByte = 0xA9;
 
   // ---------------------------------------------------------------------------
   // Code generation
   //
   // Function names correspond one-to-one to x64 instruction mnemonics.
   // Unless specified otherwise, instructions operate on 64-bit operands.
   //
   // If we need versions of an assembly instruction that operate on different
   // width arguments, we add a single-letter suffix specifying the width.
   // This is done for the following instructions: mov, cmp, inc, dec,
@@ skipping 945 matching lines @@
  private:
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_X64_ASSEMBLER_X64_H_