Index: src/opts/opts_check_x86.cpp |
diff --git a/src/opts/opts_check_x86.cpp b/src/opts/opts_check_x86.cpp |
index 55eb843312746b7e475eb776a6d35549e7553884..8fec2ba69c528040cbb02c2bd603bd1e00120a6f 100644 |
--- a/src/opts/opts_check_x86.cpp |
+++ b/src/opts/opts_check_x86.cpp |
@@ -16,6 +16,7 @@ |
#include "SkBlitRow_opts_SSE4.h" |
#include "SkBlurImage_opts_SSE2.h" |
#include "SkBlurImage_opts_SSE4.h" |
+#include "SkLazyPtr.h" |
#include "SkMorphology_opts.h" |
#include "SkMorphology_opts_SSE2.h" |
#include "SkRTConf.h" |
@@ -79,22 +80,29 @@ static inline void getcpuid(int info_type, int info[4]) { |
/* Fetch the SIMD level directly from the CPU, at run-time. |
* Only checks the levels needed by the optimizations in this file. |
*/ |
-static int get_SIMD_level() { |
- int cpu_info[4] = { 0 }; |
- |
+namespace { // get_SIMD_level() technically must have external linkage, so no static. |
+int* get_SIMD_level() { |
+ int cpu_info[4] = { 0, 0, 0, 0 }; |
getcpuid(1, cpu_info); |
+ |
+ int* level = SkNEW(int); |
+ |
if ((cpu_info[2] & (1<<20)) != 0) { |
- return SK_CPU_SSE_LEVEL_SSE42; |
+ *level = SK_CPU_SSE_LEVEL_SSE42; |
} else if ((cpu_info[2] & (1<<19)) != 0) { |
- return SK_CPU_SSE_LEVEL_SSE41; |
+ *level = SK_CPU_SSE_LEVEL_SSE41; |
} else if ((cpu_info[2] & (1<<9)) != 0) { |
- return SK_CPU_SSE_LEVEL_SSSE3; |
+ *level = SK_CPU_SSE_LEVEL_SSSE3; |
} else if ((cpu_info[3] & (1<<26)) != 0) { |
- return SK_CPU_SSE_LEVEL_SSE2; |
+ *level = SK_CPU_SSE_LEVEL_SSE2; |
} else { |
- return 0; |
+ *level = 0; |
} |
+ return level; |
} |
+} // namespace |
+ |
+SK_DECLARE_STATIC_LAZY_PTR(int, gSIMDLevel, get_SIMD_level); |
/* Verify that the requested SIMD level is supported in the build. |
* If not, check if the platform supports it. |
@@ -115,8 +123,7 @@ static inline bool supports_simd(int minLevel) { |
*/ |
return false; |
#else |
- static int gSIMDLevel = get_SIMD_level(); |
- return (minLevel <= gSIMDLevel); |
+ return minLevel <= *gSIMDLevel.get(); |
#endif |
} |
} |