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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1090 UNREACHABLE(); | 1090 UNREACHABLE(); |
1091 } | 1091 } |
1092 break; | 1092 break; |
1093 } | 1093 } |
1094 } | 1094 } |
1095 } | 1095 } |
1096 break; | 1096 break; |
1097 } | 1097 } |
1098 case db_x: { | 1098 case db_x: { |
1099 if (instr->Bits(22, 20) == 0x5) { | 1099 if (instr->Bits(22, 20) == 0x5) { |
1100 if (instr->Bits(7, 4) == 0xd) { | |
1101 // SMMLS (in V8 notation matching ARM ISA format) | |
1102 Format(instr, "smmls'cond 'rn, 'rm, 'rs, 'rd"); | |
1103 break; | |
1104 } | |
1105 if (instr->Bits(7, 4) == 0x1) { | 1100 if (instr->Bits(7, 4) == 0x1) { |
1106 if (instr->Bits(15, 12) == 0xF) { | 1101 if (instr->Bits(15, 12) == 0xF) { |
1107 Format(instr, "smmul'cond 'rn, 'rm, 'rs"); | 1102 Format(instr, "smmul'cond 'rn, 'rm, 'rs"); |
1108 } else { | 1103 } else { |
1109 // SMMLA (in V8 notation matching ARM ISA format) | 1104 // SMMLA (in V8 notation matching ARM ISA format) |
1110 Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd"); | 1105 Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd"); |
1111 } | 1106 } |
1112 break; | 1107 break; |
1113 } | 1108 } |
1114 } | 1109 } |
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1797 v8::internal::PrintF( | 1792 v8::internal::PrintF( |
1798 f, "%p %08x %s\n", | 1793 f, "%p %08x %s\n", |
1799 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1794 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1800 } | 1795 } |
1801 } | 1796 } |
1802 | 1797 |
1803 | 1798 |
1804 } // namespace disasm | 1799 } // namespace disasm |
1805 | 1800 |
1806 #endif // V8_TARGET_ARCH_ARM | 1801 #endif // V8_TARGET_ARCH_ARM |
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