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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1580 | 1580 |
1581 | 1581 |
1582 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA, | 1582 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA, |
1583 Condition cond) { | 1583 Condition cond) { |
1584 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | 1584 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
1585 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | | 1585 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | |
1586 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code()); | 1586 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code()); |
1587 } | 1587 } |
1588 | 1588 |
1589 | 1589 |
1590 void Assembler::smmls(Register dst, Register src1, Register src2, Register srcA, | |
1591 Condition cond) { | |
1592 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | |
1593 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | | |
1594 srcA.code() * B12 | src2.code() * B8 | B7 | B6 | B4 | src1.code()); | |
1595 } | |
1596 | |
1597 | |
1598 void Assembler::smmul(Register dst, Register src1, Register src2, | 1590 void Assembler::smmul(Register dst, Register src1, Register src2, |
1599 Condition cond) { | 1591 Condition cond) { |
1600 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 1592 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
1601 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xf * B12 | | 1593 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xf * B12 | |
1602 src2.code() * B8 | B4 | src1.code()); | 1594 src2.code() * B8 | B4 | src1.code()); |
1603 } | 1595 } |
1604 | 1596 |
1605 | 1597 |
1606 void Assembler::smlal(Register dstL, | 1598 void Assembler::smlal(Register dstL, |
1607 Register dstH, | 1599 Register dstH, |
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3859 assm->instr_at_put( | 3851 assm->instr_at_put( |
3860 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); | 3852 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); |
3861 } | 3853 } |
3862 } | 3854 } |
3863 } | 3855 } |
3864 | 3856 |
3865 | 3857 |
3866 } } // namespace v8::internal | 3858 } } // namespace v8::internal |
3867 | 3859 |
3868 #endif // V8_TARGET_ARCH_ARM | 3860 #endif // V8_TARGET_ARCH_ARM |
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