src/arm/assembler-arm.h - Issue 6529032: Merge 6168:6800 from bleeding_edge to experimental/gc branch.

Unified Diff: src/arm/assembler-arm.h

Issue 6529032: Merge 6168:6800 from bleeding_edge to experimental/gc branch. (Closed) Base URL: http://v8.googlecode.com/svn/branches/experimental/gc/

Patch Set: Created 9 years, 10 months ago

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Index: src/arm/assembler-arm.h

===================================================================

--- src/arm/assembler-arm.h (revision 6800)

+++ src/arm/assembler-arm.h (working copy)

@@ -41,6 +41,7 @@

#define V8_ARM_ASSEMBLER_ARM_H_

#include <stdio.h>

#include "assembler.h"

+#include "constants-arm.h"

#include "serialize.h"

namespace v8 {

@@ -167,6 +168,9 @@

struct DwVfpRegister {

// d0 has been excluded from allocation. This is following ia32

// where xmm0 is excluded. This should be revisited.

+ // Currently d0 is used as a scratch register.

+ // d1 has also been excluded from allocation to be used as a scratch

+ // register as well.

static const int kNumRegisters = 16;

static const int kNumAllocatableRegisters = 15;

@@ -297,11 +301,6 @@

const DwVfpRegister d14 = { 14 };

const DwVfpRegister d15 = { 15 };

-// VFP FPSCR constants.

-static const uint32_t kVFPExceptionMask = 0xf;

-static const uint32_t kVFPRoundingModeMask = 3 << 22;

-static const uint32_t kVFPFlushToZeroMask = 1 << 24;

-static const uint32_t kVFPRoundToMinusInfinityBits = 2 << 22;

// Coprocessor register

struct CRegister {

@@ -362,150 +361,7 @@

};

-// Condition field in instructions.

-enum Condition {

- // any value < 0 is considered no_condition

- no_condition = -1,

- eq = 0 << 28, // Z set equal.

- ne = 1 << 28, // Z clear not equal.

- nz = 1 << 28, // Z clear not zero.

- cs = 2 << 28, // C set carry set.

- hs = 2 << 28, // C set unsigned higher or same.

- cc = 3 << 28, // C clear carry clear.

- lo = 3 << 28, // C clear unsigned lower.

- mi = 4 << 28, // N set negative.

- pl = 5 << 28, // N clear positive or zero.

- vs = 6 << 28, // V set overflow.

- vc = 7 << 28, // V clear no overflow.

- hi = 8 << 28, // C set, Z clear unsigned higher.

- ls = 9 << 28, // C clear or Z set unsigned lower or same.

- ge = 10 << 28, // N == V greater or equal.

- lt = 11 << 28, // N != V less than.

- gt = 12 << 28, // Z clear, N == V greater than.

- le = 13 << 28, // Z set or N != V less then or equal

- al = 14 << 28 // always.

-};

-// Returns the equivalent of !cc.

-inline Condition NegateCondition(Condition cc) {

- ASSERT(cc != al);

- return static_cast<Condition>(cc ^ ne);

-// Corresponds to transposing the operands of a comparison.

-inline Condition ReverseCondition(Condition cc) {

- switch (cc) {

- case lo:

- return hi;

- case hi:

- return lo;

- case hs:

- return ls;

- case ls:

- return hs;

- case lt:

- return gt;

- case gt:

- return lt;

- case ge:

- return le;

- case le:

- return ge;

- default:

- return cc;

- };

-// Branch hints are not used on the ARM. They are defined so that they can

-// appear in shared function signatures, but will be ignored in ARM

-// implementations.

-enum Hint { no_hint };

-// Hints are not used on the arm. Negating is trivial.

-inline Hint NegateHint(Hint ignored) { return no_hint; }

// -----------------------------------------------------------------------------

-// Addressing modes and instruction variants

-// Shifter operand shift operation

-enum ShiftOp {

- LSL = 0 << 5,

- LSR = 1 << 5,

- ASR = 2 << 5,

- ROR = 3 << 5,

- RRX = -1

-};

-// Condition code updating mode

-enum SBit {

- SetCC = 1 << 20, // set condition code

- LeaveCC = 0 << 20 // leave condition code unchanged

-};

-// Status register selection

-enum SRegister {

- CPSR = 0 << 22,

- SPSR = 1 << 22

-};

-// Status register fields

-enum SRegisterField {

- CPSR_c = CPSR | 1 << 16,

- CPSR_x = CPSR | 1 << 17,

- CPSR_s = CPSR | 1 << 18,

- CPSR_f = CPSR | 1 << 19,

- SPSR_c = SPSR | 1 << 16,

- SPSR_x = SPSR | 1 << 17,

- SPSR_s = SPSR | 1 << 18,

- SPSR_f = SPSR | 1 << 19

-};

-// Status register field mask (or'ed SRegisterField enum values)

-typedef uint32_t SRegisterFieldMask;

-// Memory operand addressing mode

-enum AddrMode {

- // bit encoding P U W

- Offset = (8|4|0) << 21, // offset (without writeback to base)

- PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback

- PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback

- NegOffset = (8|0|0) << 21, // negative offset (without writeback to base)

- NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback

- NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback

-};

-// Load/store multiple addressing mode

-enum BlockAddrMode {

- // bit encoding P U W

- da = (0|0|0) << 21, // decrement after

- ia = (0|4|0) << 21, // increment after

- db = (8|0|0) << 21, // decrement before

- ib = (8|4|0) << 21, // increment before

- da_w = (0|0|1) << 21, // decrement after with writeback to base

- ia_w = (0|4|1) << 21, // increment after with writeback to base

- db_w = (8|0|1) << 21, // decrement before with writeback to base

- ib_w = (8|4|1) << 21 // increment before with writeback to base

-};

-// Coprocessor load/store operand size

-enum LFlag {

- Long = 1 << 22, // long load/store coprocessor

- Short = 0 << 22 // short load/store coprocessor

-};

-// -----------------------------------------------------------------------------

// Machine instruction Operands

// Class Operand represents a shifter operand in data processing instructions

@@ -648,9 +504,6 @@

};

-typedef int32_t Instr;

extern const Instr kMovLrPc;

extern const Instr kLdrPCMask;

extern const Instr kLdrPCPattern;

@@ -670,15 +523,11 @@

extern const Instr kCmpCmnMask;

extern const Instr kCmpCmnPattern;

extern const Instr kCmpCmnFlip;

-extern const Instr kALUMask;

-extern const Instr kAddPattern;

-extern const Instr kSubPattern;

-extern const Instr kAndPattern;

-extern const Instr kBicPattern;

extern const Instr kAddSubFlip;

extern const Instr kAndBicFlip;

class Assembler : public Malloced {

public:

// Create an assembler. Instructions and relocation information are emitted

@@ -880,6 +729,7 @@

void cmp(Register src1, Register src2, Condition cond = al) {

cmp(src1, Operand(src2), cond);

}

+ void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);

void cmn(Register src1, const Operand& src2, Condition cond = al);

@@ -991,7 +841,6 @@

void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);

// Exception-generating instructions and debugging support

- static const int kDefaultStopCode = -1;

void stop(const char* msg,

Condition cond = al,

int32_t code = kDefaultStopCode);

@@ -1094,39 +943,38 @@

void vmov(const Register dst,

const SwVfpRegister src,

const Condition cond = al);

- enum ConversionMode {

- FPSCRRounding = 0,

- RoundToZero = 1

- };

void vcvt_f64_s32(const DwVfpRegister dst,

const SwVfpRegister src,