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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 651223003: MIPS: [turbofan] Optimize division/modulus by constant. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 2 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
11 11
12 // MIPS-specific opcodes that specify which assembly sequence to emit. 12 // MIPS-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction. 13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \ 14 #define TARGET_ARCH_OPCODE_LIST(V) \
15 V(MipsAdd) \ 15 V(MipsAdd) \
16 V(MipsAddOvf) \ 16 V(MipsAddOvf) \
17 V(MipsSub) \ 17 V(MipsSub) \
18 V(MipsSubOvf) \ 18 V(MipsSubOvf) \
19 V(MipsMul) \ 19 V(MipsMul) \
20 V(MipsMulHigh) \
20 V(MipsDiv) \ 21 V(MipsDiv) \
21 V(MipsDivU) \ 22 V(MipsDivU) \
22 V(MipsMod) \ 23 V(MipsMod) \
23 V(MipsModU) \ 24 V(MipsModU) \
24 V(MipsAnd) \ 25 V(MipsAnd) \
25 V(MipsOr) \ 26 V(MipsOr) \
26 V(MipsXor) \ 27 V(MipsXor) \
27 V(MipsShl) \ 28 V(MipsShl) \
28 V(MipsShr) \ 29 V(MipsShr) \
29 V(MipsSar) \ 30 V(MipsSar) \
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after
77 #define TARGET_ADDRESSING_MODE_LIST(V) \ 78 #define TARGET_ADDRESSING_MODE_LIST(V) \
78 V(MRI) /* [%r0 + K] */ \ 79 V(MRI) /* [%r0 + K] */ \
79 V(MRR) /* [%r0 + %r1] */ 80 V(MRR) /* [%r0 + %r1] */
80 81
81 82
82 } // namespace compiler 83 } // namespace compiler
83 } // namespace internal 84 } // namespace internal
84 } // namespace v8 85 } // namespace v8
85 86
86 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 87 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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