Forking disassembler and simulator for Thumb2 support;

src/arm/constants-arm.h

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 57 matching lines @@
 
 // Simulator should support ARM5 instructions.
 #if !defined(__arm__)
 # define CAN_USE_ARMV5_INSTRUCTIONS 1
 # define CAN_USE_THUMB_INSTRUCTIONS 1
 #endif
 
 namespace assembler {
 namespace arm {
 
+// The following enum declarations are identical to declarations in
+// assembler-thumb2.h, but in a different namespace. Please keep the order and
+// values consistent, so we can merge the files later easily.
+
+// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
+// as defined in section A3.4
+enum Opcode {
+  no_operand = -1,
+  AND =  0,  // Logical AND
+  EOR =  1,  // Logical Exclusive OR
+  SUB =  2,  // Subtract
+  RSB =  3,  // Reverse Subtract
+  ADD =  4,  // Add
+  ADC =  5,  // Add with Carry
+  SBC =  6,  // Subtract with Carry
+  RSC =  7,  // Reverse Subtract with Carry
+  TST =  8,  // Test
+  TEQ =  9,  // Test Equivalence
+  CMP = 10,  // Compare
+  CMN = 11,  // Compare Negated
+  ORR = 12,  // Logical (inclusive) OR
+  MOV = 13,  // Move
+  BIC = 14,  // Bit Clear
+  MVN = 15,  // Move Not
+  max_operand = 16
+};
+
+enum BitPositions {
+  B0  = 1 << 0,
+  B1  = 1 << 1,
+  B2  = 1 << 2,
+  B3  = 1 << 3,
+  B4  = 1 << 4,
+  B5  = 1 << 5,
+  B6  = 1 << 6,
+  B7  = 1 << 7,
+  B8  = 1 << 8,
+  B9  = 1 << 9,
+  B10 = 1 << 10,
+  B11 = 1 << 11,
+  B12 = 1 << 12,
+  B13 = 1 << 13,
+  B14 = 1 << 14,
+  B15 = 1 << 15,
+  B16 = 1 << 16,
+  B18 = 1 << 18,
+  B19 = 1 << 19,
+  B20 = 1 << 20,
+  B21 = 1 << 21,
+  B22 = 1 << 22,
+  B23 = 1 << 23,
+  B24 = 1 << 24,
+  B25 = 1 << 25,
+  B26 = 1 << 26,
+  B27 = 1 << 27
+};
+
 // Number of registers in normal ARM mode.
 static const int kNumRegisters = 16;
 
 // VFP support.
 static const int kNumVFPRegisters = 48;
 
 // PC is register 15.
 static const int kPCRegister = 15;
 static const int kNoRegister = -1;
 
@@ skipping 24 matching lines @@
   GE = 10,  // signed greater than or equal
   LT = 11,  // signed less than
   GT = 12,  // signed greater than
   LE = 13,  // signed less than or equal
   AL = 14,  // always (unconditional)
   special_condition = 15,  // special condition (refer to section A3.2.1)
   max_condition = 16
 };
 
 
-// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
-// as defined in section A3.4
-enum Opcode {
-  no_operand = -1,
-  AND =  0,  // Logical AND
-  EOR =  1,  // Logical Exclusive OR
-  SUB =  2,  // Subtract
-  RSB =  3,  // Reverse Subtract
-  ADD =  4,  // Add
-  ADC =  5,  // Add with Carry
-  SBC =  6,  // Subtract with Carry
-  RSC =  7,  // Reverse Subtract with Carry
-  TST =  8,  // Test
-  TEQ =  9,  // Test Equivalence
-  CMP = 10,  // Compare
-  CMN = 11,  // Compare Negated
-  ORR = 12,  // Logical (inclusive) OR
-  MOV = 13,  // Move
-  BIC = 14,  // Bit Clear
-  MVN = 15,  // Move Not
-  max_operand = 16
-};
-
-
 // Some special instructions encoded as a TEQ with S=0 (bit 20).
 enum Opcode9Bits {
   BX   =  1,
   BXJ  =  2,
   BLX  =  3,
   BKPT =  7
 };
 
 
 // Some special instructions encoded as a CMN with S=0 (bit 20).
 enum Opcode11Bits {
   CLZ  =  1
 };
 
 
 // S
 
 
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 enum Shift {
   no_shift = -1,
+  RRX = -2,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   max_shift = 4
 };
 
 
 // Special Software Interrupt codes when used in the presence of the ARM
 // simulator.
@@ skipping 18 matching lines @@
 //   Instr* instr = Instr::At(ptr);
 //   int type = instr->TypeField();
 //   return ((type == 0) || (type == 1)) && instr->HasS();
 // }
 //
 class Instr {
  public:
   enum {
     kInstrSize = 4,
     kInstrSizeLog2 = 2,
-    kPCReadOffset = 8
+    kPCReadOffset = 8,
+    kPCReadOffsetThumb = 4
   };
 
   // Get the raw instruction bits.
   inline instr_t InstructionBits() const {
     return *reinterpret_cast<const instr_t*>(this);
   }
 
   // Set the raw instruction bits to value.
   inline void SetInstructionBits(instr_t value) {
     *reinterpret_cast<instr_t*>(this) = value;
@@ skipping 122 matching lines @@
 // Helper functions for converting between VFP register numbers and names.
 class VFPRegisters {
  public:
   // Return the name of the register.
   static const char* Name(int reg);
 
  private:
   static const char* names_[kNumVFPRegisters];
 };
 
+// Thumb2 sepcific stuff starts here
+enum SetFlags {
+  FALSE = 0,
+  TRUE = 1,
+  AUTO = 2
+};
+
+
+enum Operation {
+  OP_UNSUPPORTED,
+
+  OP_ADC, OP_ADD, OP_ADR, OP_AND, OP_ASR,
+
+  OP_B, OP_BFC, OP_BFI, OP_BIC, OP_BKPT, OP_BL, OP_BLX, OP_BX, OP_BXJ,
+
+  OP_CBNZ, OP_CBZ, OP_CDP, OP_CDP2, OP_CHKA, OP_CLREX, OP_CLZ, OP_CNN,
+  OP_CMN_IMM, OP_CMP, OP_CMP_IMM, OP_CPS,
+
+  OP_DBG, OP_DMB, OP_DSB,
+
+  OP_EOR,
+
+  OP_ISB, OP_IT,
+
+  OP_LDC, OP_LDC2, OP_LDM, OP_LDMIA, OP_LDMFD, OP_LDMDA, OP_LDMDB, OP_LDMEA,
+  OP_LDMIB, OP_LDMED, OP_LDR, OP_LDR_LITERAL, OP_LDRB, OP_LDRBT, OP_LDRD,
+  OP_LDREX, OP_LDREXB, OP_LDREXD, OP_LDREXH, OP_LDRH, OP_LDRHT, OP_LDRSB,
+  OP_LDRSBT, OP_LDRSH, OP_LDRSHT, OP_LDRT, OP_LSL, OP_LSR, OP_MCR, OP_MCR2,
+  OP_MCRR, OP_MCRR2, OP_MLA, OP_MLS, OP_MOV, OP_MOVT, OP_MRC, OP_MRC2,
+  OP_MRRC, OP_MRRC2, OP_MRS, OP_MSR, OP_MUL, OP_MVN,
+
+  OP_NEG, OP_NOP,
+
+  OP_ORN, OP_ORR, OP_PKH, OP_PLD, OP_PLDW, OP_PLI, OP_POP, OP_PUSH,
+
+  OP_QADD, OP_QADD16, OP_QADD8, OP_QASX, OP_QDADD, OP_QDSUB, OP_QSAX, OP_QSUB,
+  OP_QSUB16, OP_QSUB8,
+
+  OP_RBIT, OP_REV, OP_REV16, OP_REVSH, OP_RFE, OP_ROR, OP_RRX, OP_RSB,
+  OP_RSC,
+
+  OP_SADD16, OP_SADD8, OP_SASX, OP_SBC, OP_SBFX, OP_SDIV, OP_SEL, OP_SETEND,
+  OP_SEV, OP_SHADD16, OP_SHADD8, OP_SHASX, OP_SHSAX, OP_SHSUB16, OP_SHSUB8,
+  OP_SMC, OP_SMLABB, OP_SMLABT, OP_SMLATB, OP_SMLATT, OP_SMLAD, OP_SMLAL,
+  OP_SMLALBB, OP_SMLALBT, OP_SMLALTB, OP_SMLALTT, OP_SMLALD, OP_SMLAWB,
+  OP_SMLAWT, OP_SMLSD, OP_SMLSLD, OP_SMMLA, OP_SMMLS, OP_SMMUL, OP_SMUAD,
+  OP_SMULBB, OP_SMULBT, OP_SMULTB, OP_SMULTT, OP_SMULL, OP_SMULWB, OP_SMULWT,
+  OP_SMUSD, OP_SRS, OP_SSAT, OP_SSAT16, OP_SSAX, OP_SSUB16, OP_SSUB8,
+  OP_STC, OP_STC2, OP_STM, OP_STMIA, OP_STMEA, OP_STMDA, OP_STMED,
+  OP_STMDB, OP_STMFD, OP_STMIB, OP_STMFA, OP_STR, OP_STRB, OP_STRBT, OP_STRD,
+  OP_STREX, OP_STREXB, OP_STREXD, OP_STREXH, OP_STRH, OP_STRHT, OP_STRT, OP_SUB,
+  OP_SVC, OP_SWC, OP_SWPB, OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_SXTB, OP_SXTB16,
+  OP_SXTH,
+
+  OP_TBB, OP_TBH, OP_TEQ, OP_TST,
+
+  OP_UADD16, OP_UADD8, OP_UASX, OP_UBFX, OP_UDIV, OP_UHADD16, OP_UHADD8,
+  OP_UHASX, OP_UHSAX, OP_UHSUB16, OP_UHSUB8, OP_UMAAL, OP_UMLAL, OP_UMULL,
+  OP_UQADD16, OP_UQADD8, OP_UQASX, OP_UQSAX, OP_UQSUB16, OP_UQSUB8,
+  OP_USADD8, OP_USADA8, OP_USAT, OP_USAT16, OP_USAX, OP_USUB16, OP_USUB8,
+  OP_UXTAB, OP_UXTAB16, OP_UXTAH, OP_UXTB, OP_UXTB16, OP_UXTH,
+
+  OP_VABA, OP_VABAL, OP_VABD_INT, OP_VABDL, OP_VABD_FP, OP_VABS, OP_VACGE,
+  OP_VACGT, OP_VACLE, OP_VACLT, OP_VADD_INT, OP_VADD_FP, OP_VADDHN,
+  OP_VADDL, OP_VADDW, OP_VAND, OP_VBIC, OP_VBIF, OP_VBIT, OP_VBSL,
+  OP_VCEQ, OP_VCGE, OP_VCGT, OP_VCLE, OP_VCLS, OP_VCLT, OP_VCLZ, OP_VCMP,
+  OP_VCMPE, OP_VCNT, OP_VCVT, OP_VCVTR, OP_VDIV, OP_VDUP, OP_VEOR, OP_VEXT,
+  OP_VHADD, OP_VHSUB, OP_VLD1, OP_VLD2, OP_VLD3, OP_VLD4, OP_VLDM,
+  OP_VLDR, OP_VMAX, OP_VMIN, OP_VMLA, OP_VMLAL, OP_VMLS, OP_VMLSL,
+  OP_VMOV, OP_VMOVL, OP_VMOVN, OP_VMRS, OP_VMSR, OP_VMUL, OP_VMULL, OP_VMVN,
+  OP_VMVN_IMM, OP_VNEG, OP_VNMLA, OP_VNMLS, OP_VNMUL, OP_VORN, OP_VORR,
+  OP_VPADAL, OP_VPADD, OP_VPADDL, OP_VPMAX, OP_VPMIN, OP_VPOP, OP_VPUSH,
+  OP_VQABS, OP_VQADD, OP_VQDMLAL, OP_VQDMLSL, OP_VQDMULH, OP_VQDMULL, OP_VQMOVN,
+  OP_VQMOVUN, OP_VQNEG, OP_VQRDMULH, OP_VQRSHL, OP_VQRSHRN, OP_VQRSHRUN,
+  OP_VQSHL, OP_VQSHLU, OP_VQSHRN, OP_VQSHRUN, OP_VQSUB, OP_VRADDHN, OP_VRECPE,
+  OP_VRECPS, OP_VREV15, OP_VREV32, OP_VREV64, OP_VRHADD, OP_VRSHL, OP_VRSHR,
+  OP_VRSHRN, OP_VRSQRTE, OP_VRSQRTS, OP_VRSRA, OP_VRSUBHN, OP_VSHL, OP_VSHLL,
+  OP_VSHR, OP_VSHRN, OP_VSLI, OP_VSQRT, OP_VSRA, OP_VSRI, OP_VST1, OP_VST2,
+  OP_VST3, OP_VST4, OP_VSTM, OP_VSTR, OP_VSUB, OP_VSUBHN, OP_VSUBL, OP_VSUBW,
+  OP_VSWP, OP_VTBL, OP_VTBX, OP_VTRN, OP_VTST, OP_VUZP, OP_VZIP,
+
+  OP_WFE, OP_WFI,
+
+  OP_YIELD
+};
+
+enum OpVariant {
+  VARIANT_NONE,
+  VARIANT_REGISTER,
+  VARIANT_IMMEDIATE,
+  VARIANT_REGISTER_SHIFTED_REGISTER,
+  VARIANT_SP_PLUS_IMMEDIATE
+};
+
+// Thumb 2 Instruction
+
+const uint16_t kMax16BitThumbOpcode = 0xe7ff;
+
+class InstrThumb2 {
+ public:
+  explicit InstrThumb2(byte* pc);
+
+
+  // Get the pc
+  inline byte* Pc() const {
+    return pc_;
+  }
+
+  inline byte* Address() const {
+    return reinterpret_cast<byte*>(reinterpret_cast<uint32_t>(pc_) & ~1);
+  }
+
+  // Read one particular bit out of the instruction bits (16 bit or hi).
+  inline int Bit0(int nr) const {
+    return (instr0_ >> nr) & 1;
+  }
+
+  // Read a bit field out of the instruction bits (16 bit or hi).
+  inline int Bits0(int hi, int lo) const {
+    return (instr0_ >> lo) & ((2 << (hi - lo)) - 1);
+  }
+
+  // Read one particular bit out of the instruction bits (16 bit or hi).
+  inline int Bit1(int nr) const {
+    return (instr1_ >> nr) & 1;
+  }
+
+  // Read a bit field out of the instruction bits (16 bit or hi).
+  inline int Bits1(int hi, int lo) const {
+    return (instr1_ >> lo) & ((2 << (hi - lo)) - 1);
+  }
+
+  inline int Type() const {
+    return type_;
+  }
+
+  inline int Variant() const {
+    return variant_;
+  }
+
+  inline bool HasS() const {
+    return s_;
+  }
+
+  inline int Rd() const {
+    return rd_;
+  }
+
+  inline int Rm() const {
+    return rm_;
+  }
+
+  inline int Rn() const {
+    return rn_;
+  }
+
+  inline int Rs() const {
+    return rs_;
+  }
+
+  inline int Rt() const {
+    return rt_;
+  }
+
+  inline int Imm() const {
+    return imm_;
+  }
+
+  inline int Size() const {
+    return size_;
+  }
+
+  inline Operation Op() const {
+    return op_;
+  }
+
+ private:
+  byte* pc_;
+  uint16_t instr0_;
+  uint16_t instr1_;
+  int size_;
+
+  Operation op_;
+  OpVariant variant_;
+  bool s_;
+  int type_;
+  int rd_;
+  int rm_;
+  int rn_;
+  int rs_;
+  int rt_;
+  int cond_;
+  int imm_;
+
+  void Decode16();
+  void Decode32();
+
+  void Decode16_Imm11(Operation op, OpVariant variant);
+  void Decode16_Rdn3Imm8(Operation op, OpVariant variant);
+
+  void Decode32_SRn4XImm3Rd4Imm2Type2Rm4(Operation op, OpVariant variant);
+  void Decode32_ImmX5SRn4XImm3Rd4Imm8(Operation op, OpVariant variant);
+
+  void DecodeImmShift();
+  void ThumbExpandImm();
+
+  void UnsupportedInstruction();
+
+  // We need to prevent the creation of instances of class Instr.
+  DISALLOW_IMPLICIT_CONSTRUCTORS(InstrThumb2);
+};
 
 } }  // namespace assembler::arm
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_