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1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// | 1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file defines properties of lowered x86-32 instructions in the | 10 // This file defines properties of lowered x86-32 instructions in the |
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71 #define REGX8632_BYTEREG_TABLE \ | 71 #define REGX8632_BYTEREG_TABLE \ |
72 /* val, encode */ \ | 72 /* val, encode */ \ |
73 X(Reg_al, = 0) \ | 73 X(Reg_al, = 0) \ |
74 X(Reg_cl, = 1) \ | 74 X(Reg_cl, = 1) \ |
75 X(Reg_dl, = 2) \ | 75 X(Reg_dl, = 2) \ |
76 X(Reg_bl, = 3) \ | 76 X(Reg_bl, = 3) \ |
77 X(Reg_ah, = 4) | 77 X(Reg_ah, = 4) |
78 //#define X(val, encode) | 78 //#define X(val, encode) |
79 | 79 |
80 // X86 segment registers. | 80 // X86 segment registers. |
81 #define SEG_REGX8632_TABLE \ | 81 #define SEG_REGX8632_TABLE \ |
82 /* enum value, name */ \ | 82 /* enum value, name, prefix */ \ |
83 X(SegReg_CS, "cs") \ | 83 X(SegReg_CS, "cs", 0x2E) \ |
84 X(SegReg_DS, "ds") \ | 84 X(SegReg_DS, "ds", 0x3E) \ |
85 X(SegReg_ES, "es") \ | 85 X(SegReg_ES, "es", 0x26) \ |
86 X(SegReg_SS, "ss") \ | 86 X(SegReg_SS, "ss", 0x36) \ |
87 X(SegReg_FS, "fs") \ | 87 X(SegReg_FS, "fs", 0x64) \ |
88 X(SegReg_GS, "gs") \ | 88 X(SegReg_GS, "gs", 0x65) \ |
89 //#define X(val, name) | 89 //#define X(val, name, prefix) |
90 | 90 |
91 // X87 ST(n) registers. | 91 // X87 ST(n) registers. |
92 #define X87ST_REGX8632_TABLE \ | 92 #define X87ST_REGX8632_TABLE \ |
93 /* enum value, encode, name */ \ | 93 /* enum value, encode, name */ \ |
94 X(X87ST_First, = 0, "st(0)") \ | 94 X(X87ST_First, = 0, "st(0)") \ |
95 X(X87ST_0, = 0, "st(0)") \ | 95 X(X87ST_0, = 0, "st(0)") \ |
96 X(X87ST_1, = 1, "st(1)") \ | 96 X(X87ST_1, = 1, "st(1)") \ |
97 X(X87ST_2, = 2, "st(2)") \ | 97 X(X87ST_2, = 2, "st(2)") \ |
98 X(X87ST_3, = 3, "st(3)") \ | 98 X(X87ST_3, = 3, "st(3)") \ |
99 X(X87ST_4, = 4, "st(4)") \ | 99 X(X87ST_4, = 4, "st(4)") \ |
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148 X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "xmmword ptr") \ | 148 X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "xmmword ptr") \ |
149 X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ | 149 X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ |
150 X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ | 150 X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ |
151 X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ | 151 X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ |
152 X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ | 152 X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ |
153 X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "xmmword ptr") \ | 153 X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "xmmword ptr") \ |
154 X(IceType_v4f32, IceType_f32 , "ps", "" , "" , "xmmword ptr") \ | 154 X(IceType_v4f32, IceType_f32 , "ps", "" , "" , "xmmword ptr") \ |
155 //#define X(tag, elementty, cvt, sdss, width) | 155 //#define X(tag, elementty, cvt, sdss, width) |
156 | 156 |
157 #endif // SUBZERO_SRC_ICEINSTX8632_DEF | 157 #endif // SUBZERO_SRC_ICEINSTX8632_DEF |
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