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1 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like | 1 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like |
2 ; those for pmull vary more wildly depending on operand size (rather than | 2 ; those for pmull vary more wildly depending on operand size (rather than |
3 ; follow a usual pattern). | 3 ; follow a usual pattern). |
4 | 4 |
5 ; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \ | 5 ; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 -sandbox --verbose none \ |
6 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ | 6 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
7 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 7 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
8 ; RUN: %p2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s | 8 ; RUN: %p2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s |
9 | 9 |
10 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { | 10 define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { |
11 entry: | 11 entry: |
12 %res = mul <8 x i16> %arg0, %arg1 | 12 %res = mul <8 x i16> %arg0, %arg1 |
13 ret <8 x i16> %res | 13 ret <8 x i16> %res |
14 ; CHECK-LABEL: test_mul_v8i16 | 14 ; CHECK-LABEL: test_mul_v8i16 |
15 ; CHECK: 66 0f d5 c1 pmullw xmm0, xmm1 | 15 ; CHECK: 66 0f d5 c1 pmullw xmm0, xmm1 |
(...skipping 104 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
120 %res1 = load <16 x i8>* %addr2_v16xI8, align 1 | 120 %res1 = load <16 x i8>* %addr2_v16xI8, align 1 |
121 %res2 = load <16 x i8>* %addr_v16xI8, align 1 | 121 %res2 = load <16 x i8>* %addr_v16xI8, align 1 |
122 %res3 = load <16 x i8>* %addr3_v16xI8, align 1 | 122 %res3 = load <16 x i8>* %addr3_v16xI8, align 1 |
123 %res12 = add <16 x i8> %res1, %res2 | 123 %res12 = add <16 x i8> %res1, %res2 |
124 %res123 = add <16 x i8> %res12, %res3 | 124 %res123 = add <16 x i8> %res12, %res3 |
125 ret <16 x i8> %res123 | 125 ret <16 x i8> %res123 |
126 } | 126 } |
127 ; CHECK-LABEL: load_v16xI8 | 127 ; CHECK-LABEL: load_v16xI8 |
128 ; CHECK: 0f 10 0{{.*}} movups xmm0, xmmword ptr [e{{.*}}] | 128 ; CHECK: 0f 10 0{{.*}} movups xmm0, xmmword ptr [e{{.*}}] |
129 | 129 |
| 130 ; Test segment override prefix. This happens w/ nacl.read.tp. |
| 131 declare i8* @llvm.nacl.read.tp() |
| 132 |
| 133 ; Also test more address complex operands via address-mode-optimization. |
| 134 define i32 @test_nacl_read_tp_more_addressing() { |
| 135 entry: |
| 136 %ptr = call i8* @llvm.nacl.read.tp() |
| 137 %__1 = ptrtoint i8* %ptr to i32 |
| 138 %x = add i32 %__1, %__1 |
| 139 %__3 = inttoptr i32 %x to i32* |
| 140 %v = load i32* %__3, align 1 |
| 141 %v_add = add i32 %v, 1 |
| 142 |
| 143 %ptr2 = call i8* @llvm.nacl.read.tp() |
| 144 %__6 = ptrtoint i8* %ptr2 to i32 |
| 145 %y = add i32 %__6, -128 |
| 146 %__8 = inttoptr i32 %y to i32* |
| 147 %v_add2 = add i32 %v, 4 |
| 148 store i32 %v_add2, i32* %__8, align 1 |
| 149 |
| 150 %z = add i32 %__6, 256 |
| 151 %__9 = inttoptr i32 %z to i32* |
| 152 %v_add3 = add i32 %v, 91 |
| 153 store i32 %v_add2, i32* %__9, align 1 |
| 154 |
| 155 ret i32 %v |
| 156 } |
| 157 ; CHECK-LABEL: test_nacl_read_tp_more_addressing |
| 158 ; CHECK: 65 8b 05 00 00 00 00 mov eax, dword ptr gs:[0] |
| 159 ; CHECK: 8b 04 00 mov eax, dword ptr [eax + eax] |
| 160 ; CHECK: 65 8b 0d 00 00 00 00 mov ecx, dword ptr gs:[0] |
| 161 ; CHECK: 89 51 80 mov dword ptr [ecx - 128], edx |
| 162 ; CHECK: 89 91 00 01 00 00 mov dword ptr [ecx + 256], edx |
| 163 |
130 ; ERRORS-NOT: ICE translation error | 164 ; ERRORS-NOT: ICE translation error |
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