Handle "Mov" which is mov, movss, movsd, and used for nacl.read.tp.

src/assembler_ia32.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===- subzero/src/assembler_ia32.h - Assembler for x86-32 ----------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the Assembler class for x86-32.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ASSEMBLER_IA32_H_
 #define SUBZERO_SRC_ASSEMBLER_IA32_H_
 
-#include "IceDefs.h"
 #include "IceConditionCodesX8632.h"
+#include "IceOperand.h"
 #include "IceRegistersX8632.h"
 #include "IceTypes.h"
 #include "IceUtils.h"
 
 #include "assembler.h"
 
 namespace Ice {
 
 class Assembler;
-class ConstantRelocatable;
 
 using RegX8632::GPRRegister;
 using RegX8632::XmmRegister;
 using RegX8632::ByteRegister;
 using RegX8632::X87STRegister;
 
 namespace x86 {
 
 const int MAX_NOP_SIZE = 8;
 
@@ skipping 15 matching lines @@
 
 private:
   DisplacementRelocation(FixupKind Kind, const ConstantRelocatable *Sym)
       : AssemblerFixup(Kind, Sym) {}
   DisplacementRelocation(const DisplacementRelocation &) = delete;
   DisplacementRelocation &operator=(const DisplacementRelocation &) = delete;
 };
 
 class Immediate {
 public:
-  explicit Immediate(int32_t value) : value_(value) {}
+  explicit Immediate(int32_t value) : value_(value), fixup_(NULL) {}
 
-  Immediate(const Immediate &other) : value_(other.value_) {}
+  explicit Immediate(const Immediate &other)
+      : value_(other.value_),
+        fixup_(other.fixup_) {
+  }
+
+  explicit Immediate(AssemblerFixup *fixup)
+      : value_(fixup->value()->getOffset()), fixup_(fixup) {
+    // Use the Offset in the "value" for now. If the symbol is part of
+    // ".bss", then the relocation's symbol will be plain ".bss" and
+    // the value will need to be adjusted further to be sym's
+    // bss offset + Offset.
+  }
 
   int32_t value() const { return value_; }
+  AssemblerFixup *fixup() const { return fixup_; }
 
-  bool is_int8() const { return Utils::IsInt(8, value_); }
-  bool is_uint8() const { return Utils::IsUint(8, value_); }
-  bool is_uint16() const { return Utils::IsUint(16, value_); }
+  bool is_int8() const {
+    // We currently only allow 32-bit fixups, and they usually have value = 0,
+    // so if fixup_ != NULL, it shouldn't be classified as int8/16.
+    return fixup_ == NULL && Utils::IsInt(8, value_);
+  }
+  bool is_uint8() const {
+    return fixup_ == NULL && Utils::IsUint(8, value_);
+  }
+  bool is_uint16() const {
+    return fixup_ == NULL && Utils::IsUint(16, value_);
+  }
 
 private:
   const int32_t value_;
+  AssemblerFixup *fixup_;
 };
 
 class Operand {
 public:
   uint8_t mod() const { return (encoding_at(0) >> 6) & 3; }
 
   GPRRegister rm() const {
     return static_cast<GPRRegister>(encoding_at(0) & 7);
   }
 
@@ skipping 129 matching lines @@
     }
   }
 
   Address(const Address &other) : Operand(other) {}
 
   Address &operator=(const Address &other) {
     Operand::operator=(other);
     return *this;
   }
 
-  static Address Absolute(const uintptr_t addr, AssemblerFixup *fixup) {
+  static Address Absolute(const uintptr_t addr) {
     Address result;
     result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
     result.SetDisp32(addr);
+    return result;
+  }
+
+  static Address Absolute(AssemblerFixup *fixup) {
+    Address result;
+    result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
+    // Use the Offset in the displacement for now. If the symbol is part of
+    // ".bss", then the relocation's symbol will be plain .bss and the
+    // displacement will need to be adjusted further to be sym's
+    // bss offset + Offset.
+    result.SetDisp32(fixup->value()->getOffset());
     result.SetFixup(fixup);
     return result;
   }
 
   static Address ofConstPool(GlobalContext *Ctx, Assembler *Asm,
                              const Constant *Imm);
 
 private:
   Address() {} // Needed by Address::Absolute.
 };
@@ skipping 175 matching lines @@
   void pushl(GPRRegister reg);
 
   void popl(GPRRegister reg);
   void popl(const Address &address);
 
   void pushal();
   void popal();
 
   void setcc(CondX86::BrCond condition, ByteRegister dst);
 
-  void movl(GPRRegister dst, const Immediate &src);
-  void movl(GPRRegister dst, GPRRegister src);
+  void mov(Type Ty, GPRRegister dst, const Immediate &src);
+  void mov(Type Ty, GPRRegister dst, GPRRegister src);
 
-  void movl(GPRRegister dst, const Address &src);
-  void movl(const Address &dst, GPRRegister src);
-  void movl(const Address &dst, const Immediate &imm);
+  void mov(Type Ty, GPRRegister dst, const Address &src);
+  void mov(Type Ty, const Address &dst, GPRRegister src);
+  void mov(Type Ty, const Address &dst, const Immediate &imm);
 
   void movzxb(GPRRegister dst, ByteRegister src);
   void movzxb(GPRRegister dst, const Address &src);
   void movsxb(GPRRegister dst, ByteRegister src);
   void movsxb(GPRRegister dst, const Address &src);
 
-  void movb(ByteRegister dst, const Address &src);
-  void movb(const Address &dst, ByteRegister src);
-  void movb(const Address &dst, const Immediate &imm);
-
   void movzxw(GPRRegister dst, GPRRegister src);
   void movzxw(GPRRegister dst, const Address &src);
   void movsxw(GPRRegister dst, GPRRegister src);
   void movsxw(GPRRegister dst, const Address &src);
-  void movw(GPRRegister dst, const Address &src);
-  void movw(const Address &dst, GPRRegister src);
 
   void lea(Type Ty, GPRRegister dst, const Address &src);
 
   void cmov(CondX86::BrCond cond, GPRRegister dst, GPRRegister src);
 
   void rep_movsb();
 
   void movss(Type Ty, XmmRegister dst, const Address &src);
   void movss(Type Ty, const Address &dst, XmmRegister src);
   void movss(Type Ty, XmmRegister dst, XmmRegister src);
@@ skipping 270 matching lines @@
   void cmpxchg(Type Ty, const Address &address, GPRRegister reg);
   void cmpxchg8b(const Address &address);
   void xadd(Type Ty, const Address &address, GPRRegister reg);
   void xchg(Type Ty, const Address &address, GPRRegister reg);
 
   void LockCmpxchg(Type Ty, const Address &address, GPRRegister reg) {
     lock();
     cmpxchg(Ty, address, reg);
   }
 
+  void EmitSegmentOverride(uint8_t prefix) { EmitUint8(prefix); }
+
   intptr_t PreferredLoopAlignment() { return 16; }
   void Align(intptr_t alignment, intptr_t offset);
   void Bind(Label *label);
 
   intptr_t CodeSize() const { return buffer_.Size(); }
 
   void FinalizeInstructions(const MemoryRegion &region) {
     buffer_.FinalizeInstructions(region);
   }
 
@@ skipping 57 matching lines @@
 inline void AssemblerX86::EmitFixup(AssemblerFixup *fixup) {
   buffer_.EmitFixup(fixup);
 }
 
 inline void AssemblerX86::EmitOperandSizeOverride() { EmitUint8(0x66); }
 
 } // end of namespace x86
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ASSEMBLER_IA32_H_