Implement bigint absAdd, absSub, mulAdd, sqrAdd, estQuotientDigit intrinsics,

runtime/vm/assembler_x64.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/heap.h"
@@ skipping 1809 matching lines @@
 
 void Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::addl(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_NONE);
+  EmitUint8(0x03);
+  EmitOperand(dst & 7, address);
+}
+
+
+void Assembler::addl(const Address& address, Register src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(src, address, REX_NONE);
+  EmitUint8(0x01);
+  EmitOperand(src & 7, address);
+}
+
+
+void Assembler::adcl(Register dst, Register src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_NONE);
+  EmitUint8(0x13);
+  EmitOperand(dst & 7, operand);
+}
+
+
+void Assembler::adcl(Register dst, const Immediate& imm) {
+  ASSERT(imm.is_int32());
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(dst, REX_NONE);
+  EmitComplex(2, Operand(dst), imm);
+}
+
+
+void Assembler::adcl(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_NONE);
+  EmitUint8(0x13);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::addq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::addq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x03);
   EmitOperand(dst & 7, address);
 }
 
 
-void Assembler::addl(const Address& address, const Immediate& imm) {
-  UNIMPLEMENTED();
-}
-
-
-void Assembler::addq(Register reg, const Immediate& imm) {
+void Assembler::addq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-    EmitRegisterREX(reg, REX_W);
-    EmitComplex(0, Operand(reg), imm);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(0, Operand(dst), imm);
   } else {
     movq(TMP, imm);
-    addq(reg, TMP);
+    addq(dst, TMP);
   }
 }
 
 
 void Assembler::addq(const Address& address, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitOperandREX(0, address, REX_W);
     EmitComplex(0, Operand(address), imm);
   } else {
     movq(TMP, imm);
     addq(address, TMP);
   }
 }
 
 
-void Assembler::addq(const Address& address, Register reg) {
+void Assembler::addq(const Address& address, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitOperandREX(reg, address, REX_W);
+  EmitOperandREX(src, address, REX_W);
   EmitUint8(0x01);
-  EmitOperand(reg & 7, address);
-}
-
-
-void Assembler::adcl(Register dst, Register src) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  Operand operand(src);
-  EmitOperandREX(dst, operand, REX_NONE);
-  EmitUint8(0x13);
-  EmitOperand(dst & 7, operand);
+  EmitOperand(src & 7, address);
 }
 
 
 void Assembler::subl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x2B);
   EmitOperand(dst & 7, operand);
 }
 
 
+void Assembler::subl(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_NONE);
+  EmitUint8(0x2B);
+  EmitOperand(dst & 7, address);
+}
+
+
+void Assembler::sbbl(Register dst, Register src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_NONE);
+  EmitUint8(0x1B);
+  EmitOperand(dst & 7, operand);
+}
+
+
+void Assembler::sbbl(Register dst, const Immediate& imm) {
+  ASSERT(imm.is_int32());
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(dst, REX_NONE);
+  EmitComplex(3, Operand(dst), imm);
+}
+
+
+void Assembler::sbbl(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_NONE);
+  EmitUint8(0x1B);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
 }
 
 
 void Assembler::cqo() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(RAX, REX_W);
   EmitUint8(0x99);
 }
 
 
 void Assembler::idivl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(reg, REX_NONE);
   EmitUint8(0xF7);
-  EmitUint8(0xF8 | (reg & 7));
+  EmitOperand(7, Operand(reg));
+}
+
+
+void Assembler::divl(Register reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(reg, REX_NONE);
+  EmitUint8(0xF7);
+  EmitOperand(6, Operand(reg));
 }
 
 
 void Assembler::idivq(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(reg, REX_W);
   EmitUint8(0xF7);
-  EmitUint8(0xF8 | (reg & 7));
+  EmitOperand(7, Operand(reg));
 }
 
 
 void Assembler::imull(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, Operand(src));
 }
 
 
 void Assembler::imull(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(reg);
   EmitOperandREX(reg, operand, REX_NONE);
   EmitUint8(0x69);
   EmitOperand(reg & 7, Operand(reg));
   EmitImmediate(imm);
 }
 
 
+void Assembler::mull(Register reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(reg, REX_NONE);
+  EmitUint8(0xF7);
+  EmitOperand(4, Operand(reg));
+}
+
+
 void Assembler::imulq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, operand);
 }
 
 
@@ skipping 104 matching lines @@
 void Assembler::sarl(Register reg, const Immediate& imm) {
   EmitGenericShift(false, 7, reg, imm);
 }
 
 
 void Assembler::sarl(Register operand, Register shifter) {
   EmitGenericShift(false, 7, operand, shifter);
 }
 
 
+void Assembler::shldl(Register dst, Register src, const Immediate& imm) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  ASSERT(imm.is_int8());
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_NONE);
+  EmitUint8(0x0F);
+  EmitUint8(0xA4);
+  EmitOperand(src & 7, Operand(dst));
+  EmitUint8(imm.value() & 0xFF);
+}
+
+
 void Assembler::shlq(Register reg, const Immediate& imm) {
   EmitGenericShift(true, 4, reg, imm);
 }
 
 
 void Assembler::shlq(Register operand, Register shifter) {
   EmitGenericShift(true, 4, operand, shifter);
 }
 
 
@@ skipping 1490 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64