Implement bigint absAdd, absSub, mulAdd, sqrAdd, estQuotientDigit intrinsics,

runtime/vm/disassembler_x64.cc

 // Copyright (c) 2012, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_IA32.
 #if defined(TARGET_ARCH_X64)
 #include "platform/utils.h"
 #include "vm/allocation.h"
@@ skipping 616 matching lines @@
     switch (regop) {
       case 2:
         mnem = "not";
         break;
       case 3:
         mnem = "neg";
         break;
       case 4:
         mnem = "mul";
         break;
+      case 6:
+        mnem = "div";
+        break;
       case 7:
         mnem = "idiv";
         break;
       default:
         UnimplementedInstruction();
     }
     AppendToBuffer("%s%c %s",
                    mnem,
                    operand_size_code(),
                    NameOfCPURegister(rm));
@@ skipping 865 matching lines @@
 
   } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
              opcode == 0xB7 || opcode == 0xAF) {
     // Size-extending moves, IMUL.
     current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);
 
   } else if ((opcode & 0xF0) == 0x90) {
     // SETcc: Set byte on condition. Needs pointer to beginning of instruction.
     current = data + SetCC(data);
 
-  } else if (opcode == 0xAB || opcode == 0xA5 || opcode == 0xAD) {
-    // SHLD, SHRD (double-precision shift), BTS (bit set).
-    AppendToBuffer("%s ", mnemonic);
+  } else if ((opcode & 0xFE) == 0xA4 || (opcode & 0xFE) == 0xAC ||
+             opcode == 0xAB || opcode == 0xA3) {
+    // SHLD, SHRD (double-prec. shift), BTS (bit test and set), BT (bit test).
+    AppendToBuffer("%s%c ", mnemonic, operand_size_code());
     int mod, regop, rm;
     get_modrm(*current, &mod, &regop, &rm);
     current += PrintRightOperand(current);
-    if (opcode == 0xAB) {
-      AppendToBuffer(",%s", NameOfCPURegister(regop));
+    AppendToBuffer(",%s", NameOfCPURegister(regop));
+    if (opcode == 0xAB || opcode == 0xA3) {
+      // Done.
+    } else if (opcode == 0xA5 || opcode == 0xAD) {
+      AppendToBuffer(",cl");
     } else {
-      AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
+      AppendToBuffer(",");
+      current += PrintImmediate(current, BYTE_SIZE);
     }
   } else {
     UnimplementedInstruction();
   }
   return static_cast<int>(current - data);
 }
 
 
 // Mnemonics for two-byte opcode instructions starting with 0x0F.
 // The argument is the second byte of the two-byte opcode.
@@ skipping 11 matching lines @@
     case 0x58:  // F2 prefix.
       return "addsd";
     case 0x59:  // F2 prefix.
       return "mulsd";
     case 0x5C:  // F2 prefix.
       return "subsd";
     case 0x5E:  // F2 prefix.
       return "divsd";
     case 0xA2:
       return "cpuid";
+    case 0xA3:
+      return "bt";
+    case 0xA4:
     case 0xA5:
       return "shld";
     case 0xAB:
       return "bts";
+    case 0xAC:
     case 0xAD:
       return "shrd";
     case 0xAF:
       return "imul";
     case 0xB6:
       return "movzxb";
     case 0xB7:
       return "movzxw";
     case 0xBE:
       return "movsxb";
@@ skipping 390 matching lines @@
                                   pc);
     pc += instruction_length;
   }
 
   return;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64