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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
| 6 #if defined(TARGET_ARCH_IA32) | 6 #if defined(TARGET_ARCH_IA32) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/code_generator.h" | 9 #include "vm/code_generator.h" |
| 10 #include "vm/cpu.h" | 10 #include "vm/cpu.h" |
| (...skipping 1736 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1747 void Assembler::sarl(Register operand, Register shifter) { | 1747 void Assembler::sarl(Register operand, Register shifter) { |
| 1748 EmitGenericShift(7, Operand(operand), shifter); | 1748 EmitGenericShift(7, Operand(operand), shifter); |
| 1749 } | 1749 } |
| 1750 | 1750 |
| 1751 | 1751 |
| 1752 void Assembler::sarl(const Address& address, Register shifter) { | 1752 void Assembler::sarl(const Address& address, Register shifter) { |
| 1753 EmitGenericShift(7, Operand(address), shifter); | 1753 EmitGenericShift(7, Operand(address), shifter); |
| 1754 } | 1754 } |
| 1755 | 1755 |
| 1756 | 1756 |
| 1757 void Assembler::shld(Register dst, Register src) { | 1757 void Assembler::shldl(Register dst, Register src) { |
| 1758 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1758 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1759 EmitUint8(0x0F); | 1759 EmitUint8(0x0F); |
| 1760 EmitUint8(0xA5); | 1760 EmitUint8(0xA5); |
| 1761 EmitRegisterOperand(src, dst); | 1761 EmitRegisterOperand(src, dst); |
| 1762 } | 1762 } |
| 1763 | 1763 |
| 1764 | 1764 |
| 1765 void Assembler::shld(Register dst, Register src, const Immediate& imm) { | 1765 void Assembler::shldl(Register dst, Register src, const Immediate& imm) { |
| 1766 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1766 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1767 ASSERT(imm.is_int8()); | 1767 ASSERT(imm.is_int8()); |
| 1768 EmitUint8(0x0F); | 1768 EmitUint8(0x0F); |
| 1769 EmitUint8(0xA4); | 1769 EmitUint8(0xA4); |
| 1770 EmitRegisterOperand(src, dst); | 1770 EmitRegisterOperand(src, dst); |
| 1771 EmitUint8(imm.value() & 0xFF); | 1771 EmitUint8(imm.value() & 0xFF); |
| 1772 } | 1772 } |
| 1773 | 1773 |
| 1774 | 1774 |
| 1775 void Assembler::shld(const Address& operand, Register src) { | 1775 void Assembler::shldl(const Address& operand, Register src) { |
| 1776 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1776 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1777 EmitUint8(0x0F); | 1777 EmitUint8(0x0F); |
| 1778 EmitUint8(0xA5); | 1778 EmitUint8(0xA5); |
| 1779 EmitOperand(src, Operand(operand)); | 1779 EmitOperand(src, Operand(operand)); |
| 1780 } | 1780 } |
| 1781 | 1781 |
| 1782 | 1782 |
| 1783 void Assembler::shrd(Register dst, Register src) { | 1783 void Assembler::shrdl(Register dst, Register src) { |
| 1784 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1784 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1785 EmitUint8(0x0F); | 1785 EmitUint8(0x0F); |
| 1786 EmitUint8(0xAD); | 1786 EmitUint8(0xAD); |
| 1787 EmitRegisterOperand(src, dst); | 1787 EmitRegisterOperand(src, dst); |
| 1788 } | 1788 } |
| 1789 | 1789 |
| 1790 | 1790 |
| 1791 void Assembler::shrd(Register dst, Register src, const Immediate& imm) { | 1791 void Assembler::shrdl(Register dst, Register src, const Immediate& imm) { |
| 1792 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1792 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1793 ASSERT(imm.is_int8()); | 1793 ASSERT(imm.is_int8()); |
| 1794 EmitUint8(0x0F); | 1794 EmitUint8(0x0F); |
| 1795 EmitUint8(0xAC); | 1795 EmitUint8(0xAC); |
| 1796 EmitRegisterOperand(src, dst); | 1796 EmitRegisterOperand(src, dst); |
| 1797 EmitUint8(imm.value() & 0xFF); | 1797 EmitUint8(imm.value() & 0xFF); |
| 1798 } | 1798 } |
| 1799 | 1799 |
| 1800 | 1800 |
| 1801 void Assembler::shrd(const Address& dst, Register src) { | 1801 void Assembler::shrdl(const Address& dst, Register src) { |
| 1802 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1802 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1803 EmitUint8(0x0F); | 1803 EmitUint8(0x0F); |
| 1804 EmitUint8(0xAD); | 1804 EmitUint8(0xAD); |
| 1805 EmitOperand(src, Operand(dst)); | 1805 EmitOperand(src, Operand(dst)); |
| 1806 } | 1806 } |
| 1807 | 1807 |
| 1808 | 1808 |
| 1809 void Assembler::negl(Register reg) { | 1809 void Assembler::negl(Register reg) { |
| 1810 AssemblerBuffer::EnsureCapacity ensured(&buffer_); | 1810 AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1811 EmitUint8(0xF7); | 1811 EmitUint8(0xF7); |
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| 2878 | 2878 |
| 2879 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 2879 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 2880 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); | 2880 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); |
| 2881 return xmm_reg_names[reg]; | 2881 return xmm_reg_names[reg]; |
| 2882 } | 2882 } |
| 2883 | 2883 |
| 2884 | 2884 |
| 2885 } // namespace dart | 2885 } // namespace dart |
| 2886 | 2886 |
| 2887 #endif // defined TARGET_ARCH_IA32 | 2887 #endif // defined TARGET_ARCH_IA32 |
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