OLD | NEW |
1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
(...skipping 1078 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1089 } else { | 1089 } else { |
1090 UNREACHABLE(); | 1090 UNREACHABLE(); |
1091 } | 1091 } |
1092 break; | 1092 break; |
1093 } | 1093 } |
1094 } | 1094 } |
1095 } | 1095 } |
1096 break; | 1096 break; |
1097 } | 1097 } |
1098 case db_x: { | 1098 case db_x: { |
| 1099 if (instr->Bits(22, 20) == 0x5) { |
| 1100 if (instr->Bits(7, 4) == 0xd) { |
| 1101 // SMMLS (in V8 notation matching ARM ISA format) |
| 1102 Format(instr, "smmls'cond 'rn, 'rm, 'rs, 'rd"); |
| 1103 break; |
| 1104 } |
| 1105 if (instr->Bits(7, 4) == 0x1) { |
| 1106 if (instr->Bits(15, 12) == 0xF) { |
| 1107 Format(instr, "smmul'cond 'rn, 'rm, 'rs"); |
| 1108 } else { |
| 1109 // SMMLA (in V8 notation matching ARM ISA format) |
| 1110 Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd"); |
| 1111 } |
| 1112 break; |
| 1113 } |
| 1114 } |
1099 if (FLAG_enable_sudiv) { | 1115 if (FLAG_enable_sudiv) { |
1100 if (instr->Bits(5, 4) == 0x1) { | 1116 if (instr->Bits(5, 4) == 0x1) { |
1101 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { | 1117 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { |
1102 if (instr->Bit(21) == 0x1) { | 1118 if (instr->Bit(21) == 0x1) { |
1103 // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs | 1119 // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs |
1104 Format(instr, "udiv'cond'b 'rn, 'rm, 'rs"); | 1120 Format(instr, "udiv'cond'b 'rn, 'rm, 'rs"); |
1105 } else { | 1121 } else { |
1106 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs | 1122 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs |
1107 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); | 1123 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); |
1108 } | 1124 } |
(...skipping 672 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1781 v8::internal::PrintF( | 1797 v8::internal::PrintF( |
1782 f, "%p %08x %s\n", | 1798 f, "%p %08x %s\n", |
1783 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1799 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1784 } | 1800 } |
1785 } | 1801 } |
1786 | 1802 |
1787 | 1803 |
1788 } // namespace disasm | 1804 } // namespace disasm |
1789 | 1805 |
1790 #endif // V8_TARGET_ARCH_ARM | 1806 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |