Change usage of naclcall and nacljmp pseudo-instructions to match x86 gas

lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp

 //=== X86MCNaCl.cpp - Expansion of NaCl pseudo-instructions      --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //===----------------------------------------------------------------------===//
@@ skipping 259 matching lines @@
     assert(!Is64Bit);
     MCInst ADDInst;
     unsigned ADDReg = X86::ESP;
     ADDInst.setOpcode(X86::ADD32ri);
     ADDInst.addOperand(MCOperand::CreateReg(ADDReg));
     ADDInst.addOperand(MCOperand::CreateReg(ADDReg));
     ADDInst.addOperand(*AmtOp);
     Out.EmitInstruction(ADDInst);
   }
 
-  MCInst JMPInst;
-  JMPInst.setOpcode(Is64Bit ? X86::NACL_JMP64r : X86::NACL_JMP32r);
-  JMPInst.addOperand(MCOperand::CreateReg(RegTarget));
-  Out.EmitInstruction(JMPInst);
+  EmitIndirectBranch(MCOperand::CreateReg(RegTarget), Is64Bit, false, Out);
 }
 
 // Fix a register after being truncated to 32-bits.
 static void EmitRegFix(unsigned Reg64, MCStreamer &Out) {
   // lea (%rsp, %r15, 1), %rsp
   // We do not need to add the R15 base for the zero-based sandbox model
   if (!FlagUseZeroBasedSandbox) {
     MCInst Tmp;
     Tmp.setOpcode(X86::LEA64r);
     Tmp.addOperand(MCOperand::CreateReg(Reg64));    // DestReg
@@ skipping 180 matching lines @@
              SandboxedInst.getOperand(3).getImm(),  // Offset
              SandboxedInst.getOperand(4).getReg(),  // SegmentReg
              Out);
   }
 
   EmitRegFix(Reg64, Out);
   Out.EmitBundleUnlock();
 }
 
 
+namespace {
+// RAII holder for the recursion guard.
+class EmitRawState {
+ public:
+  EmitRawState(X86MCNaClSFIState &S) : State(S) {
+    State.EmitRaw = true;
+  }
+  ~EmitRawState() {
+    State.EmitRaw = false;
+  }
+ private:
+  X86MCNaClSFIState &State;
+};
+}
+
 namespace llvm {
 // CustomExpandInstNaClX86 -
 //   If Inst is a NaCl pseudo instruction, emits the substitute
 //   expansion to the MCStreamer and returns true.
 //   Otherwise, returns false.
 //
 //   NOTE: Each time this function calls Out.EmitInstruction(), it will be
 //   called again recursively to rewrite the new instruction being emitted.
 //   Care must be taken to ensure that this does not result in an infinite
 //   loop. Also, global state must be managed carefully so that it is
 //   consistent during recursive calls.
 //
 //   We need global state to keep track of the explicit prefix (PREFIX_*)
 //   instructions. Unfortunately, the assembly parser prefers to generate
 //   these instead of combined instructions. At this time, having only
 //   one explicit prefix is supported.
 bool CustomExpandInstNaClX86(const MCInst &Inst, MCStreamer &Out,
                              X86MCNaClSFIState &State) {
   // If we are emitting to .s, just emit all pseudo-instructions directly.
   if (Out.hasRawTextSupport()) {
     return false;
   }
+  // If we make a call to EmitInstruction, we will be called recursively. In
+  // this case we just want the raw instruction to be emitted instead of
+  // handling the insruction here.
+  if (State.EmitRaw == true && !State.PrefixPass) {
+    return false;
+  }
+  EmitRawState E(State);
   unsigned Opc = Inst.getOpcode();
   DEBUG(dbgs() << "CustomExpandInstNaClX86("; Inst.dump(); dbgs() << ")\n");
   switch (Opc) {
   case X86::LOCK_PREFIX:
   case X86::REP_PREFIX:
   case X86::REPNE_PREFIX:
   case X86::REX64_PREFIX:
     // Ugly hack because LLVM AsmParser is not smart enough to combine
     // prefixes back into the instruction they modify.
     if (State.PrefixPass) {
       State.PrefixPass = false;
       State.PrefixSaved = 0;
       return false;
     }
     assert(State.PrefixSaved == 0);
     State.PrefixSaved = Opc;
     return true;
-  case X86::NACL_CALL32d:
+  case X86::CALLpcrel32:
     assert(State.PrefixSaved == 0);
     EmitDirectCall(Inst.getOperand(0), false, Out);
     return true;
+  case X86::CALL64pcrel32:
   case X86::NACL_CALL64d:
     assert(State.PrefixSaved == 0);
     EmitDirectCall(Inst.getOperand(0), true, Out);
     return true;
   case X86::NACL_CALL32r:
     assert(State.PrefixSaved == 0);
     EmitIndirectBranch(Inst.getOperand(0), false, true, Out);
     return true;
   case X86::NACL_CALL64r:
     assert(State.PrefixSaved == 0);
@@ skipping 297 matching lines @@
 
 unsigned DemoteRegTo32_(unsigned RegIn) {
   if (RegIn == 0)
     return 0;
   unsigned RegOut = getX86SubSuperRegister_(RegIn, MVT::i32, false);
   assert(RegOut != 0);
   return RegOut;
 }
 } //namespace
 // @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@