Change usage of naclcall and nacljmp pseudo-instructions to match x86 gas

lib/Target/X86/X86NaClRewritePass.cpp

 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass that ensures stores and loads and stack/frame
@@ skipping 444 matching lines @@
     // sandbox base address.
     unsigned RegTarget;
     if (Is64Bit) {
       RegTarget = (HideSandboxBase ? X86::R11 : X86::RCX);
       BuildMI(MBB, MBBI, DL, TII->get(X86::POP64r), RegTarget);
       if (Opc == X86::RETI) {
         BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_ASPi32))
           .addOperand(MI.getOperand(0))
           .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15);
       }
+
       BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_JMP64r))
-        .addReg(RegTarget)
+        .addReg(getX86SubSuperRegister(RegTarget, MVT::i32, false))
         .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15);
     } else {
       RegTarget = X86::ECX;
       BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r), RegTarget);
       if (Opc == X86::RETI) {
         BuildMI(MBB, MBBI, DL, TII->get(X86::ADD32ri), X86::ESP)
           .addReg(X86::ESP)
           .addOperand(MI.getOperand(0));
       }
       BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_JMP32r))
@@ skipping 270 matching lines @@
   }
   return Modified;
 }
 
 /// createX86NaClRewritePassPass - returns an instance of the pass.
 namespace llvm {
   FunctionPass* createX86NaClRewritePass() {
     return new X86NaClRewritePass();
   }
 }