Change usage of naclcall and nacljmp pseudo-instructions to match x86 gas

lib/Target/X86/X86InstrNaCl.td

 //====- X86InstrNaCl.td - Describe NaCl Instructions ----*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the modifications to the X86 instruction set needed for
@@ skipping 43 matching lines @@
   def NACL_RETI32 : NaClPI32<(outs), (ins i16imm:$amt), "naclreti\t$amt">;
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1,
     isAsmParserOnly = 1 in {
   def NACL_JMP32r : NaClPI32<(outs), (ins GR32:$dst), "nacljmp\t$dst">;
 }
 
 let isCall = 1, isAsmParserOnly = 1 in {
   def NACL_CALL32d : NaClPI32<(outs), (ins i32imm_pcrel:$dst),
-                     "naclcall\t$dst">;
+                     "call\t$dst">;

[jvoung (off chromium), 2014/10/14 15:30:23]

How does this affect the asm parser, if someone was to use llvm-mc? Would it
have trouble deciding between NACL_CALL32d and CALLpcrel32?

[Derek Schuff, 2014/10/14 23:39:32]

I had thought that it would work by making CALLpcrel32 requires<NotNaCl> but
apparently that doesn't work with the asm parser.
So I went back to my previous idea of removing NACL_CALL32d and fixing up the
recursion behavior of CustomExpandInstNaClX86; PTAL

   def NACL_CALL32r : NaClPI32<(outs), (ins GR32:$dst),
                      "naclcall\t$dst">;
 }
 
 // nacltlsaddr32 gets rewritten to:
 //     .bundle_align_end
 //     .bundle_lock
 //     leal\t$sym@TLSGD, %eax
 //     call\t___tls_get_addr@PLT
 //     .bundle_unlock
@@ skipping 23 matching lines @@
     isAsmParserOnly = 1 in {
   def NACL_JMP64r : NaClPI64<(outs), (ins GR32:$dst, GR64:$rZP),
                     "nacljmp\t{$dst, $rZP|$rZP, $dst}">;
   def NACL_JMP64z : NaClPI64<(outs), (ins GR32:$dst),
                     "nacljmp\t$dst">;
 }
 
 
 let isCall = 1, isAsmParserOnly = 1 in {
   def NACL_CALL64d : NaClPI64<(outs), (ins i32imm_pcrel:$dst),
-                     "naclcall\t$dst">;
+                     "call\t$dst">;
   def NACL_CALL64r : NaClPI64<(outs), (ins GR32:$dst, GR64:$rZP),
                      "naclcall\t$dst,$rZP">;
 }
 
 let Defs = [RSP, EFLAGS], Uses = [RSP], isAsmParserOnly = 1 in {
   def NACL_ASPi8 : NaClPI64<(outs), (ins i64i8imm:$off, GR64:$rZP),
                    "naclasp{q}\t{$off, $rZP|$rZP, $off}">;
 
   def NACL_ASPi32: NaClPI64<(outs), (ins i64i32imm:$off, GR64:$rZP),
                    "naclasp{q}\t{$off, $rZP|$rZP, $off}">;
@@ skipping 61 matching lines @@
                            [(brind GR32:$dst)]>,
                            Requires<[IsNaCl, In64BitMode]>;
 }
 
 // RSP is marked as a use to prevent stack-pointer assignments that appear
 // immediately before calls from potentially appearing dead. Uses for argument
 // registers are added manually.
 let isCall = 1, Uses = [RSP] in {
     def NACL_CG_CALL64pcrel32 : I<0, Pseudo, (outs),
                                 (ins i32imm_pcrel:$dst),
-                                "naclcall\t$dst", []>,
+                                "call\t$dst", []>,
                                 Requires<[IsNaCl, In64BitMode]>;
 
     def NACL_CG_CALL64r       : I<0, Pseudo, (outs), (ins GR32:$dst),
                                 "naclcall\t$dst,%r15",
                                 [(X86call GR32:$dst)]>,
                                 Requires<[IsNaCl, In64BitMode]>;
 }
 
 def : Pat<(X86call (i32 tglobaladdr:$dst)),
           (NACL_CG_CALL64pcrel32 tglobaladdr:$dst)>,
@@ skipping 82 matching lines @@
 
 let usesCustomInserter = 1, Defs = [EFLAGS] in
 def NACL_CG_VAARG_64 : I<0, Pseudo,
                      (outs GR32:$dst),
                      (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
                      "#NACL_VAARG_64 $dst, $ap, $size, $mode, $align",
                      [(set GR32:$dst,
                      (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
                      (implicit EFLAGS)]>,
                      Requires<[IsNaCl, In64BitMode]>;