emitIAS for movsx and movzx.

tests_lit/llvm2ice_tests/test_i1.ll

 ; Tests various aspects of i1 related lowering.
 
 ; RUN: %p2i -i %s -a -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s -a -Om1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s -a --verbose none | FileCheck --check-prefix=ERRORS %s
 ; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s
@@ skipping 61 matching lines @@
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i16 = zext i1 %arg_i1 to i16
   %result = zext i16 %result_i16 to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testZextI16
 ; match the trunc instruction
 ; CHECK: and {{.*}}, 1
 ; match the zext i1 instruction
-; CHECK: movzx
-; CHECK: and {{.*}}, 1
+; CHECK: movzx [[REG:.*]], {{[a-d]l|byte ptr}}

[Jim Stichnoth, 2014/10/15 20:08:45]

Should this be something like [[REG:e.*]] to indicate the 32-bit dest register?

Also, it puzzled me that the following "and" instruction uses the 32-bit
register instead of 16-bit, but I see that lowering code explicitly uses
IceType_i32.  Something like the diff below seems to work; maybe at least mark
it with a TODO?

diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index dfb1fda..36ddebe 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -2018,8 +2018,11 @@ void TargetX8632::lowerCast(const InstCast *Inst) {
     } else if (Src0RM->getType() == IceType_i1) {
       // t = Src0RM; t &= 1; Dest = t
       Constant *One = Ctx->getConstantInt32(IceType_i32, 1);
-      Variable *T = makeReg(IceType_i32);
-      _movzx(T, Src0RM);
+      Variable *T = makeReg(Dest->getType());
+      if (Dest->getType() == IceType_i8)
+        _mov(T, Src0RM);
+      else
+        _movzx(T, Src0RM);
       _and(T, One);
       _mov(Dest, T);
     } else {

[jvoung (off chromium), 2014/10/15 21:07:29]

Hmm, yes it's a bit puzzling.

Thinking about it more, the 16-bit version will end up being longer than the
32-bit version because of the 66 prefix. Since the immediate is just "1" they
can both take advantage of the shorter imm8 form.

However, the:
part does help some, because it can notice that the mov is redundant when the
same register is chosen, and eliminate it, while the movzx is not eliminated.
The 8-bit one is also one byte shorter, if the register happens to be "al". On
the other hand, the 32-bit version gives you more choices for registers?

So, would it make sense to use the Dest type for 8-bit only, and then leave a
comment about 16-bit vs 32-bit?

+; CHECK: and [[REG]], 1
 
 ; Test zext to i32.
 define internal i32 @testZextI32(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i32 = zext i1 %arg_i1 to i32
   ret i32 %result_i32
 }
 ; CHECK-LABEL: testZextI32
 ; match the trunc instruction
@@ skipping 37 matching lines @@
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i16 = sext i1 %arg_i1 to i16
   %result = sext i16 %result_i16 to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testSextI16
 ; match the trunc instruction
 ; CHECK: and {{.*}}, 1
 ; match the sext i1 instruction
-; CHECK: movzx [[REG:.*]],
+; CHECK: movzx e[[REG:.*]], {{[a-d]l|byte ptr}}
 ; CHECK-NEXT: shl [[REG]], 15
 ; CHECK-NEXT: sar [[REG]], 15
 
 ; Test sext to i32.
 define internal i32 @testSextI32(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i32 = sext i1 %arg_i1 to i32
   ret i32 %result_i32
 }
@@ skipping 43 matching lines @@
 }
 ; CHECK-LABEL: testFptosiDouble
 ; CHECK: cvttsd2si
 ; CHECK: and {{.*}}, 1
 ; CHECK: movzx [[REG:.*]],
 ; CHECK-NEXT: shl [[REG]], 31
 ; CHECK-NEXT: sar [[REG]], 31
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ