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Issue 646923003: MIPS: Fix loading Float64 constants in turbofan. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 2 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #include "src/v8.h" 7 #include "src/v8.h"
8 8
9 #if V8_TARGET_ARCH_MIPS 9 #if V8_TARGET_ARCH_MIPS
10 10
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1518 } 1518 }
1519 } 1519 }
1520 } 1520 }
1521 1521
1522 if (bd == PROTECT) { 1522 if (bd == PROTECT) {
1523 nop(); 1523 nop();
1524 } 1524 }
1525 } 1525 }
1526 1526
1527 1527
1528 void MacroAssembler::Move(FPURegister dst, double imm) { 1528 void MacroAssembler::Move(FPURegister dst, double imm, bool force_load) {
1529 static const DoubleRepresentation minus_zero(-0.0); 1529 static const DoubleRepresentation minus_zero(-0.0);
1530 static const DoubleRepresentation zero(0.0); 1530 static const DoubleRepresentation zero(0.0);
1531 DoubleRepresentation value_rep(imm); 1531 DoubleRepresentation value_rep(imm);
1532 // Handle special values first. 1532 // Handle special values first.
1533 bool force_load = dst.is(kDoubleRegZero);
1534 if (value_rep == zero && !force_load) { 1533 if (value_rep == zero && !force_load) {
1535 mov_d(dst, kDoubleRegZero); 1534 mov_d(dst, kDoubleRegZero);
1536 } else if (value_rep == minus_zero && !force_load) { 1535 } else if (value_rep == minus_zero && !force_load) {
1537 neg_d(dst, kDoubleRegZero); 1536 neg_d(dst, kDoubleRegZero);
1538 } else { 1537 } else {
1539 uint32_t lo, hi; 1538 uint32_t lo, hi;
1540 DoubleAsTwoUInt32(imm, &lo, &hi); 1539 DoubleAsTwoUInt32(imm, &lo, &hi);
1541 // Move the low part of the double into the lower of the corresponding FPU 1540 // Move the low part of the double into the lower of the corresponding FPU
1542 // register of FPU register pair. 1541 // register of FPU register pair.
1543 if (lo != 0) { 1542 if (lo != 0) {
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6214 } 6213 }
6215 if (mag.shift > 0) sra(result, result, mag.shift); 6214 if (mag.shift > 0) sra(result, result, mag.shift);
6216 srl(at, dividend, 31); 6215 srl(at, dividend, 31);
6217 Addu(result, result, Operand(at)); 6216 Addu(result, result, Operand(at));
6218 } 6217 }
6219 6218
6220 6219
6221 } } // namespace v8::internal 6220 } } // namespace v8::internal
6222 6221
6223 #endif // V8_TARGET_ARCH_MIPS 6222 #endif // V8_TARGET_ARCH_MIPS
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