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| 1 //------------------------------------------------------------------------------ |
| 2 // <copyright file="target_reg_table.h" company="Atheros"> |
| 3 // Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. |
| 4 // |
| 5 // This program is free software; you can redistribute it and/or modify |
| 6 // it under the terms of the GNU General Public License version 2 as |
| 7 // published by the Free Software Foundation; |
| 8 // |
| 9 // Software distributed under the License is distributed on an "AS |
| 10 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 11 // implied. See the License for the specific language governing |
| 12 // rights and limitations under the License. |
| 13 // |
| 14 // |
| 15 //------------------------------------------------------------------------------ |
| 16 //============================================================================== |
| 17 // Target register table macros and structure definitions |
| 18 // |
| 19 // Author(s): ="Atheros" |
| 20 //============================================================================== |
| 21 |
| 22 #ifndef TARGET_REG_TABLE_H_ |
| 23 #define TARGET_REG_TABLE_H_ |
| 24 |
| 25 #include "targaddrs.h" |
| 26 |
| 27 /*** WARNING : Add to the end of the TABLE! do not change the order ****/ |
| 28 typedef struct targetdef_s { |
| 29 A_UINT32 d_RTC_BASE_ADDRESS; |
| 30 A_UINT32 d_SYSTEM_SLEEP_OFFSET; |
| 31 A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB; |
| 32 A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK; |
| 33 A_UINT32 d_CLOCK_CONTROL_OFFSET; |
| 34 A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK; |
| 35 A_UINT32 d_RESET_CONTROL_OFFSET; |
| 36 A_UINT32 d_RESET_CONTROL_SI0_RST_MASK; |
| 37 A_UINT32 d_GPIO_BASE_ADDRESS; |
| 38 A_UINT32 d_GPIO_PIN0_OFFSET; |
| 39 A_UINT32 d_GPIO_PIN1_OFFSET; |
| 40 A_UINT32 d_GPIO_PIN0_CONFIG_MASK; |
| 41 A_UINT32 d_GPIO_PIN1_CONFIG_MASK; |
| 42 A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB; |
| 43 A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK; |
| 44 A_UINT32 d_SI_CONFIG_I2C_LSB; |
| 45 A_UINT32 d_SI_CONFIG_I2C_MASK; |
| 46 A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB; |
| 47 A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK; |
| 48 A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB; |
| 49 A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK; |
| 50 A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB; |
| 51 A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK; |
| 52 A_UINT32 d_SI_CONFIG_DIVIDER_LSB; |
| 53 A_UINT32 d_SI_CONFIG_DIVIDER_MASK; |
| 54 A_UINT32 d_SI_BASE_ADDRESS; |
| 55 A_UINT32 d_SI_CONFIG_OFFSET; |
| 56 A_UINT32 d_SI_TX_DATA0_OFFSET; |
| 57 A_UINT32 d_SI_TX_DATA1_OFFSET; |
| 58 A_UINT32 d_SI_RX_DATA0_OFFSET; |
| 59 A_UINT32 d_SI_RX_DATA1_OFFSET; |
| 60 A_UINT32 d_SI_CS_OFFSET; |
| 61 A_UINT32 d_SI_CS_DONE_ERR_MASK; |
| 62 A_UINT32 d_SI_CS_DONE_INT_MASK; |
| 63 A_UINT32 d_SI_CS_START_LSB; |
| 64 A_UINT32 d_SI_CS_START_MASK; |
| 65 A_UINT32 d_SI_CS_RX_CNT_LSB; |
| 66 A_UINT32 d_SI_CS_RX_CNT_MASK; |
| 67 A_UINT32 d_SI_CS_TX_CNT_LSB; |
| 68 A_UINT32 d_SI_CS_TX_CNT_MASK; |
| 69 A_UINT32 d_BOARD_DATA_SZ; |
| 70 } TARGET_REGISTER_TABLE; |
| 71 |
| 72 #define BOARD_DATA_SZ_MAX 2048 |
| 73 |
| 74 #if defined(MY_TARGET_DEF) /* { */ |
| 75 |
| 76 #ifdef ATH_REG_TABLE_DIRECT_ASSIGN |
| 77 |
| 78 static struct targetdef_s my_target_def = { |
| 79 RTC_BASE_ADDRESS, |
| 80 SYSTEM_SLEEP_OFFSET, |
| 81 SYSTEM_SLEEP_DISABLE_LSB, |
| 82 SYSTEM_SLEEP_DISABLE_MASK, |
| 83 CLOCK_CONTROL_OFFSET, |
| 84 CLOCK_CONTROL_SI0_CLK_MASK, |
| 85 RESET_CONTROL_OFFSET, |
| 86 RESET_CONTROL_SI0_RST_MASK, |
| 87 GPIO_BASE_ADDRESS, |
| 88 GPIO_PIN0_OFFSET, |
| 89 GPIO_PIN0_CONFIG_MASK, |
| 90 GPIO_PIN1_OFFSET, |
| 91 GPIO_PIN1_CONFIG_MASK, |
| 92 SI_CONFIG_BIDIR_OD_DATA_LSB, |
| 93 SI_CONFIG_BIDIR_OD_DATA_MASK, |
| 94 SI_CONFIG_I2C_LSB, |
| 95 SI_CONFIG_I2C_MASK, |
| 96 SI_CONFIG_POS_SAMPLE_LSB, |
| 97 SI_CONFIG_POS_SAMPLE_MASK, |
| 98 SI_CONFIG_INACTIVE_CLK_LSB, |
| 99 SI_CONFIG_INACTIVE_CLK_MASK, |
| 100 SI_CONFIG_INACTIVE_DATA_LSB, |
| 101 SI_CONFIG_INACTIVE_DATA_MASK, |
| 102 SI_CONFIG_DIVIDER_LSB, |
| 103 SI_CONFIG_DIVIDER_MASK, |
| 104 SI_BASE_ADDRESS, |
| 105 SI_CONFIG_OFFSET, |
| 106 SI_TX_DATA0_OFFSET, |
| 107 SI_TX_DATA1_OFFSET, |
| 108 SI_RX_DATA0_OFFSET, |
| 109 SI_RX_DATA1_OFFSET, |
| 110 SI_CS_OFFSET, |
| 111 SI_CS_DONE_ERR_MASK, |
| 112 SI_CS_DONE_INT_MASK, |
| 113 SI_CS_START_LSB, |
| 114 SI_CS_START_MASK, |
| 115 SI_CS_RX_CNT_LSB, |
| 116 SI_CS_RX_CNT_MASK, |
| 117 SI_CS_TX_CNT_LSB, |
| 118 SI_CS_TX_CNT_MASK, |
| 119 MY_TARGET_BOARD_DATA_SZ, |
| 120 }; |
| 121 |
| 122 #else |
| 123 |
| 124 static struct targetdef_s my_target_def = { |
| 125 .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS, |
| 126 .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET, |
| 127 .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB, |
| 128 .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK, |
| 129 .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, |
| 130 .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, |
| 131 .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET, |
| 132 .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, |
| 133 .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, |
| 134 .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, |
| 135 .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, |
| 136 .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, |
| 137 .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, |
| 138 .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, |
| 139 .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, |
| 140 .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, |
| 141 .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, |
| 142 .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, |
| 143 .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, |
| 144 .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, |
| 145 .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, |
| 146 .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, |
| 147 .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, |
| 148 .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, |
| 149 .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, |
| 150 .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, |
| 151 .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, |
| 152 .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, |
| 153 .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, |
| 154 .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, |
| 155 .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, |
| 156 .d_SI_CS_OFFSET = SI_CS_OFFSET, |
| 157 .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, |
| 158 .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, |
| 159 .d_SI_CS_START_LSB = SI_CS_START_LSB, |
| 160 .d_SI_CS_START_MASK = SI_CS_START_MASK, |
| 161 .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, |
| 162 .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, |
| 163 .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, |
| 164 .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, |
| 165 .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, |
| 166 }; |
| 167 |
| 168 #endif |
| 169 |
| 170 #if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX |
| 171 #error "BOARD_DATA_SZ_MAX is too small" |
| 172 #endif |
| 173 |
| 174 struct targetdef_s *MY_TARGET_DEF = &my_target_def; |
| 175 |
| 176 #else /* } { */ |
| 177 |
| 178 #define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS) |
| 179 #define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET) |
| 180 #define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB) |
| 181 #define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK) |
| 182 #define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET) |
| 183 #define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) |
| 184 #define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET) |
| 185 #define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK) |
| 186 #define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS) |
| 187 #define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET) |
| 188 #define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK) |
| 189 #define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET) |
| 190 #define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK) |
| 191 #define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) |
| 192 #define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) |
| 193 #define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB) |
| 194 #define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK) |
| 195 #define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) |
| 196 #define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) |
| 197 #define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) |
| 198 #define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) |
| 199 #define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) |
| 200 #define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) |
| 201 #define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB) |
| 202 #define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK) |
| 203 #define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS) |
| 204 #define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET) |
| 205 #define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET) |
| 206 #define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET) |
| 207 #define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET) |
| 208 #define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET) |
| 209 #define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET) |
| 210 #define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK) |
| 211 #define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK) |
| 212 #define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB) |
| 213 #define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK) |
| 214 #define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB) |
| 215 #define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK) |
| 216 #define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB) |
| 217 #define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK) |
| 218 #define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ) |
| 219 |
| 220 /* SET macros */ |
| 221 #define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_L
SB) & SYSTEM_SLEEP_DISABLE_MASK) |
| 222 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & S
I_CONFIG_BIDIR_OD_DATA_MASK) |
| 223 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) |
| 224 #define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONF
IG_POS_SAMPLE_MASK) |
| 225 #define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_
CONFIG_INACTIVE_CLK_MASK) |
| 226 #define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & S
I_CONFIG_INACTIVE_DATA_MASK) |
| 227 #define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIV
IDER_MASK) |
| 228 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) |
| 229 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) |
| 230 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) |
| 231 |
| 232 #endif /* } */ |
| 233 |
| 234 #endif /*TARGET_REG_TABLE_H_*/ |
| 235 |
| 236 |
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