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| 1 //------------------------------------------------------------------------------ |
| 2 // <copyright file="targaddrs.h" company="Atheros"> |
| 3 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 4 // |
| 5 // This program is free software; you can redistribute it and/or modify |
| 6 // it under the terms of the GNU General Public License version 2 as |
| 7 // published by the Free Software Foundation; |
| 8 // |
| 9 // Software distributed under the License is distributed on an "AS |
| 10 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 11 // implied. See the License for the specific language governing |
| 12 // rights and limitations under the License. |
| 13 // |
| 14 // |
| 15 //------------------------------------------------------------------------------ |
| 16 //============================================================================== |
| 17 // Author(s): ="Atheros" |
| 18 //============================================================================== |
| 19 |
| 20 #ifndef __TARGADDRS_H__ |
| 21 #define __TARGADDRS_H__ |
| 22 #if defined(AR6001) |
| 23 #include "AR6001/addrs.h" |
| 24 #endif |
| 25 #if defined(AR6002) |
| 26 #include "AR6002/addrs.h" |
| 27 #endif |
| 28 |
| 29 /* |
| 30 * AR6K option bits, to enable/disable various features. |
| 31 * By default, all option bits are 0. |
| 32 * These bits can be set in LOCAL_SCRATCH register 0. |
| 33 */ |
| 34 #define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ |
| 35 #define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ |
| 36 #define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ |
| 37 #define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ |
| 38 #define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ |
| 39 #define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ |
| 40 #define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ |
| 41 #define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ |
| 42 |
| 43 /* |
| 44 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the |
| 45 * host_interest structure. It must match the address of the _host_interest |
| 46 * symbol (see linker script). |
| 47 * |
| 48 * Host Interest is shared between Host and Target in order to coordinate |
| 49 * between the two, and is intended to remain constant (with additions only |
| 50 * at the end) across software releases. |
| 51 * |
| 52 * All addresses are available here so that it's possible to |
| 53 * write a single binary that works with all Target Types. |
| 54 * May be used in assembler code as well as C. |
| 55 */ |
| 56 #define AR6001_HOST_INTEREST_ADDRESS 0x80000600 |
| 57 #define AR6002_HOST_INTEREST_ADDRESS 0x00500400 |
| 58 #define AR6003_HOST_INTEREST_ADDRESS 0x00540600 |
| 59 |
| 60 |
| 61 #define HOST_INTEREST_MAX_SIZE 0x100 |
| 62 |
| 63 #if !defined(__ASSEMBLER__) |
| 64 struct register_dump_s; |
| 65 struct dbglog_hdr_s; |
| 66 |
| 67 /* |
| 68 * These are items that the Host may need to access |
| 69 * via BMI or via the Diagnostic Window. The position |
| 70 * of items in this structure must remain constant |
| 71 * across firmware revisions! |
| 72 * |
| 73 * Types for each item must be fixed size across |
| 74 * target and host platforms. |
| 75 * |
| 76 * More items may be added at the end. |
| 77 */ |
| 78 struct host_interest_s { |
| 79 /* |
| 80 * Pointer to application-defined area, if any. |
| 81 * Set by Target application during startup. |
| 82 */ |
| 83 A_UINT32 hi_app_host_interest; /* 0x00 */ |
| 84 |
| 85 /* Pointer to register dump area, valid after Target crash. */ |
| 86 A_UINT32 hi_failure_state; /* 0x04 */ |
| 87 |
| 88 /* Pointer to debug logging header */ |
| 89 A_UINT32 hi_dbglog_hdr; /* 0x08 */ |
| 90 |
| 91 /* Indicates whether or not flash is present on Target. |
| 92 * NB: flash_is_present indicator is here not just |
| 93 * because it might be of interest to the Host; but |
| 94 * also because it's set early on by Target's startup |
| 95 * asm code and we need it to have a special RAM address |
| 96 * so that it doesn't get reinitialized with the rest |
| 97 * of data. |
| 98 */ |
| 99 A_UINT32 hi_flash_is_present; /* 0x0c */ |
| 100 |
| 101 /* |
| 102 * General-purpose flag bits, similar to AR6000_OPTION_* flags. |
| 103 * Can be used by application rather than by OS. |
| 104 */ |
| 105 A_UINT32 hi_option_flag; /* 0x10 */ |
| 106 |
| 107 /* |
| 108 * Boolean that determines whether or not to |
| 109 * display messages on the serial port. |
| 110 */ |
| 111 A_UINT32 hi_serial_enable; /* 0x14 */ |
| 112 |
| 113 /* Start address of Flash DataSet index, if any */ |
| 114 A_UINT32 hi_dset_list_head; /* 0x18 */ |
| 115 |
| 116 /* Override Target application start address */ |
| 117 A_UINT32 hi_app_start; /* 0x1c */ |
| 118 |
| 119 /* Clock and voltage tuning */ |
| 120 A_UINT32 hi_skip_clock_init; /* 0x20 */ |
| 121 A_UINT32 hi_core_clock_setting; /* 0x24 */ |
| 122 A_UINT32 hi_cpu_clock_setting; /* 0x28 */ |
| 123 A_UINT32 hi_system_sleep_setting; /* 0x2c */ |
| 124 A_UINT32 hi_xtal_control_setting; /* 0x30 */ |
| 125 A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ |
| 126 A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ |
| 127 A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ |
| 128 A_UINT32 hi_clock_info; /* 0x40 */ |
| 129 |
| 130 /* |
| 131 * Flash configuration overrides, used only |
| 132 * when firmware is not executing from flash. |
| 133 * (When using flash, modify the global variables |
| 134 * with equivalent names.) |
| 135 */ |
| 136 A_UINT32 hi_bank0_addr_value; /* 0x44 */ |
| 137 A_UINT32 hi_bank0_read_value; /* 0x48 */ |
| 138 A_UINT32 hi_bank0_write_value; /* 0x4c */ |
| 139 A_UINT32 hi_bank0_config_value; /* 0x50 */ |
| 140 |
| 141 /* Pointer to Board Data */ |
| 142 A_UINT32 hi_board_data; /* 0x54 */ |
| 143 A_UINT32 hi_board_data_initialized; /* 0x58 */ |
| 144 |
| 145 A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ |
| 146 |
| 147 A_UINT32 hi_desired_baud_rate; /* 0x60 */ |
| 148 A_UINT32 hi_dbglog_config; /* 0x64 */ |
| 149 A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ |
| 150 A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ |
| 151 |
| 152 A_UINT32 hi_num_bpatch_streams; /* 0x70 --
unused */ |
| 153 A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ |
| 154 |
| 155 A_UINT32 hi_refclk_hz; /* 0x78 */ |
| 156 A_UINT32 hi_ext_clk_detected; /* 0x7c */ |
| 157 A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ |
| 158 A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ |
| 159 A_UINT32 hi_hci_uart_baud; /* 0x88 */ |
| 160 A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ |
| 161 /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin *
/ |
| 162 A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ |
| 163 A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ |
| 164 |
| 165 A_UINT32 hi_allocram_start; /* 0x98 */ |
| 166 A_UINT32 hi_allocram_sz; /* 0x9c */ |
| 167 A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ |
| 168 A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ |
| 169 /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] ar
e for future use */ |
| 170 }; |
| 171 |
| 172 /* Bits defined in hi_option_flag */ |
| 173 #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ |
| 174 #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ |
| 175 #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ |
| 176 #define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */ |
| 177 #define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */ |
| 178 #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ |
| 179 #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ |
| 180 #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ |
| 181 |
| 182 /* 2 bits of hi_option_flag are used to represent 3 modes */ |
| 183 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ |
| 184 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ |
| 185 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ |
| 186 |
| 187 /* Fw Mode Mask */ |
| 188 #define HI_OPTION_FW_MODE_MASK 0x3 |
| 189 #define HI_OPTION_FW_MODE_SHIFT 0x3 |
| 190 |
| 191 /* |
| 192 * Intended for use by Host software, this macro returns the Target RAM |
| 193 * address of any item in the host_interest structure. |
| 194 * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); |
| 195 */ |
| 196 #define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 197 ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->it
em))) |
| 198 |
| 199 #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 200 ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->it
em))) |
| 201 |
| 202 #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 203 ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->it
em))) |
| 204 |
| 205 #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ |
| 206 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) |
| 207 |
| 208 #define HOST_INTEREST_PROFILE_IS_ENABLED() \ |
| 209 (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) |
| 210 |
| 211 /* Convert a Target virtual address into a Target physical address */ |
| 212 #define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff) |
| 213 #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) |
| 214 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) |
| 215 #define TARG_VTOP(TargetType, vaddr) \ |
| 216 (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \ |
| 217 (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP
(vaddr))) |
| 218 |
| 219 /* override REV2 ROM's app start address */ |
| 220 //#define AR6002_REV2_APP_START_OVERRIDE 0x914800 |
| 221 #define AR6002_REV2_APP_START_OVERRIDE 0x911A00 |
| 222 #define AR6003_REV1_APP_START_OVERRIDE 0x944c00 |
| 223 |
| 224 /* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ |
| 225 #define AR6003_FETCH_TARG_REGS_COUNT 64 |
| 226 |
| 227 #endif /* !__ASSEMBLER__ */ |
| 228 |
| 229 #endif /* __TARGADDRS_H__ */ |
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