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| 1 //------------------------------------------------------------------------------ |
| 2 // <copyright file="hif.h" company="Atheros"> |
| 3 // Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. |
| 4 // |
| 5 // This program is free software; you can redistribute it and/or modify |
| 6 // it under the terms of the GNU General Public License version 2 as |
| 7 // published by the Free Software Foundation; |
| 8 // |
| 9 // Software distributed under the License is distributed on an "AS |
| 10 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 11 // implied. See the License for the specific language governing |
| 12 // rights and limitations under the License. |
| 13 // |
| 14 // |
| 15 //------------------------------------------------------------------------------ |
| 16 //============================================================================== |
| 17 // HIF specific declarations and prototypes |
| 18 // |
| 19 // Author(s): ="Atheros" |
| 20 //============================================================================== |
| 21 #ifndef _HIF_H_ |
| 22 #define _HIF_H_ |
| 23 |
| 24 #ifdef __cplusplus |
| 25 extern "C" { |
| 26 #endif /* __cplusplus */ |
| 27 |
| 28 /* Header files */ |
| 29 #include "a_config.h" |
| 30 #include "athdefs.h" |
| 31 #include "a_types.h" |
| 32 #include "a_osapi.h" |
| 33 #include "dl_list.h" |
| 34 |
| 35 |
| 36 typedef struct htc_callbacks HTC_CALLBACKS; |
| 37 typedef struct hif_device HIF_DEVICE; |
| 38 |
| 39 /* |
| 40 * direction - Direction of transfer (HIF_READ/HIF_WRITE). |
| 41 */ |
| 42 #define HIF_READ 0x00000001 |
| 43 #define HIF_WRITE 0x00000002 |
| 44 #define HIF_DIR_MASK (HIF_READ | HIF_WRITE) |
| 45 |
| 46 /* |
| 47 * type - An interface may support different kind of read/write commands. |
| 48 * For example: SDIO supports CMD52/CMD53s. In case of MSIO it |
| 49 * translates to using different kinds of TPCs. The command type |
| 50 * is thus divided into a basic and an extended command and can |
| 51 * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. |
| 52 */ |
| 53 #define HIF_BASIC_IO 0x00000004 |
| 54 #define HIF_EXTENDED_IO 0x00000008 |
| 55 #define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) |
| 56 |
| 57 /* |
| 58 * emode - This indicates the whether the command is to be executed in a |
| 59 * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ |
| 60 * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been |
| 61 * implemented using the asynchronous mode allowing the the bus |
| 62 * driver to indicate the completion of operation through the |
| 63 * registered callback routine. The requirement primarily comes |
| 64 * from the contexts these operations get called from (a driver's |
| 65 * transmit context or the ISR context in case of receive). |
| 66 * Support for both of these modes is essential. |
| 67 */ |
| 68 #define HIF_SYNCHRONOUS 0x00000010 |
| 69 #define HIF_ASYNCHRONOUS 0x00000020 |
| 70 #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) |
| 71 |
| 72 /* |
| 73 * dmode - An interface may support different kinds of commands based on |
| 74 * the tradeoff between the amount of data it can carry and the |
| 75 * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ |
| 76 * HIF_BLOCK_BASIS). In case of latter, the data is rounded off |
| 77 * to the nearest block size by padding. The size of the block is |
| 78 * configurable at compile time using the HIF_BLOCK_SIZE and is |
| 79 * negotiated with the target during initialization after the |
| 80 * AR6000 interrupts are enabled. |
| 81 */ |
| 82 #define HIF_BYTE_BASIS 0x00000040 |
| 83 #define HIF_BLOCK_BASIS 0x00000080 |
| 84 #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) |
| 85 |
| 86 /* |
| 87 * amode - This indicates if the address has to be incremented on AR6000 |
| 88 * after every read/write operation (HIF?FIXED_ADDRESS/ |
| 89 * HIF_INCREMENTAL_ADDRESS). |
| 90 */ |
| 91 #define HIF_FIXED_ADDRESS 0x00000100 |
| 92 #define HIF_INCREMENTAL_ADDRESS 0x00000200 |
| 93 #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS
) |
| 94 |
| 95 #define HIF_WR_ASYNC_BYTE_FIX \ |
| 96 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED
_ADDRESS) |
| 97 #define HIF_WR_ASYNC_BYTE_INC \ |
| 98 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCRE
MENTAL_ADDRESS) |
| 99 #define HIF_WR_ASYNC_BLOCK_INC \ |
| 100 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCR
EMENTAL_ADDRESS) |
| 101 #define HIF_WR_SYNC_BYTE_FIX \ |
| 102 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_
ADDRESS) |
| 103 #define HIF_WR_SYNC_BYTE_INC \ |
| 104 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREM
ENTAL_ADDRESS) |
| 105 #define HIF_WR_SYNC_BLOCK_INC \ |
| 106 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCRE
MENTAL_ADDRESS) |
| 107 #define HIF_WR_ASYNC_BLOCK_FIX \ |
| 108 (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXE
D_ADDRESS) |
| 109 #define HIF_WR_SYNC_BLOCK_FIX \ |
| 110 (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED
_ADDRESS) |
| 111 #define HIF_RD_SYNC_BYTE_INC \ |
| 112 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREME
NTAL_ADDRESS) |
| 113 #define HIF_RD_SYNC_BYTE_FIX \ |
| 114 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_A
DDRESS) |
| 115 #define HIF_RD_ASYNC_BYTE_FIX \ |
| 116 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_
ADDRESS) |
| 117 #define HIF_RD_ASYNC_BLOCK_FIX \ |
| 118 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED
_ADDRESS) |
| 119 #define HIF_RD_ASYNC_BYTE_INC \ |
| 120 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREM
ENTAL_ADDRESS) |
| 121 #define HIF_RD_ASYNC_BLOCK_INC \ |
| 122 (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCRE
MENTAL_ADDRESS) |
| 123 #define HIF_RD_SYNC_BLOCK_INC \ |
| 124 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREM
ENTAL_ADDRESS) |
| 125 #define HIF_RD_SYNC_BLOCK_FIX \ |
| 126 (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_
ADDRESS) |
| 127 |
| 128 typedef enum { |
| 129 HIF_DEVICE_POWER_STATE = 0, |
| 130 HIF_DEVICE_GET_MBOX_BLOCK_SIZE, |
| 131 HIF_DEVICE_GET_MBOX_ADDR, |
| 132 HIF_DEVICE_GET_PENDING_EVENTS_FUNC, |
| 133 HIF_DEVICE_GET_IRQ_PROC_MODE, |
| 134 HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, |
| 135 HIF_DEVICE_POWER_STATE_CHANGE, |
| 136 HIF_DEVICE_GET_IRQ_YIELD_PARAMS, |
| 137 HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT, |
| 138 HIF_DEVICE_GET_OS_DEVICE, |
| 139 HIF_DEVICE_DEBUG_BUS_STATE, |
| 140 } HIF_DEVICE_CONFIG_OPCODE; |
| 141 |
| 142 /* |
| 143 * HIF CONFIGURE definitions: |
| 144 * |
| 145 * HIF_DEVICE_GET_MBOX_BLOCK_SIZE |
| 146 * input : none |
| 147 * output : array of 4 A_UINT32s |
| 148 * notes: block size is returned for each mailbox (4) |
| 149 * |
| 150 * HIF_DEVICE_GET_MBOX_ADDR |
| 151 * input : none |
| 152 * output : HIF_DEVICE_MBOX_INFO |
| 153 * notes: |
| 154 * |
| 155 * HIF_DEVICE_GET_PENDING_EVENTS_FUNC |
| 156 * input : none |
| 157 * output: HIF_PENDING_EVENTS_FUNC function pointer |
| 158 * notes: this is optional for the HIF layer, if the request is |
| 159 * not handled then it indicates that the upper layer can use |
| 160 * the standard device methods to get pending events (IRQs, mailbox mes
sages etc..) |
| 161 * otherwise it can call the function pointer to check pending events. |
| 162 * |
| 163 * HIF_DEVICE_GET_IRQ_PROC_MODE |
| 164 * input : none |
| 165 * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) |
| 166 * note: the hif layer interfaces with the underlying OS-specific bus driver.
The HIF |
| 167 * layer can report whether IRQ processing is requires synchronous behav
ior or |
| 168 * can be processed using asynchronous bus requests (typically faster). |
| 169 * |
| 170 * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC |
| 171 * input : |
| 172 * output : HIF_MASK_UNMASK_RECV_EVENT function pointer |
| 173 * notes: this is optional for the HIF layer. The HIF layer may require a spe
cial mechanism |
| 174 * to mask receive message events. The upper layer can call this point
er when it needs |
| 175 * to mask/unmask receive events (in case it runs out of buffers). |
| 176 * |
| 177 * HIF_DEVICE_POWER_STATE_CHANGE |
| 178 * |
| 179 * input : HIF_DEVICE_POWER_CHANGE_TYPE |
| 180 * output : none |
| 181 * note: this is optional for the HIF layer. The HIF layer can handle power o
n/off state change |
| 182 * requests in an interconnect specific way. This is highly OS and bus
driver dependent. |
| 183 * The caller must guarantee that no HIF read/write requests will be mad
e after the device |
| 184 * is powered down. |
| 185 * |
| 186 * HIF_DEVICE_GET_IRQ_YIELD_PARAMS |
| 187 * |
| 188 * input : none |
| 189 * output : HIF_DEVICE_IRQ_YIELD_PARAMS |
| 190 * note: This query checks if the HIF layer wishes to impose a processing yiel
d count for the DSR handler. |
| 191 * The DSR callback handler will exit after a fixed number of RX packets or ev
ents are processed. |
| 192 * This query is only made if the device reports an IRQ processing mode of HIF
_DEVICE_IRQ_SYNC_ONLY. |
| 193 * The HIF implementation can ignore this command if it does not desire the DS
R callback to yield. |
| 194 * The HIF layer can indicate the maximum number of IRQ processing units (RX p
ackets) before the |
| 195 * DSR handler callback must yield and return control back to the HIF layer.
When a yield limit is |
| 196 * used the DSR callback will not call HIFAckInterrupts() as it would normally
do before returning. |
| 197 * The HIF implementation that requires a yield count must call HIFAckInterrup
t() when it is prepared |
| 198 * to process interrupts again. |
| 199 * |
| 200 * HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT |
| 201 * input : none |
| 202 * output : HIF_DEVICE_SCATTER_SUPPORT_INFO |
| 203 * note: This query checks if the HIF layer implements the SCATTER request in
terface. Scatter requests |
| 204 * allows upper layers to submit mailbox I/O operations using a list of buffer
s. This is useful for |
| 205 * multi-message transfers that can better utilize the bus interconnect. |
| 206 * |
| 207 * |
| 208 * HIF_DEVICE_GET_OS_DEVICE |
| 209 * intput : none |
| 210 * output : HIF_DEVICE_OS_DEVICE_INFO; |
| 211 * note: On some operating systems, the HIF layer has a parent device object f
or the bus. This object |
| 212 * may be required to register certain types of logical devices. |
| 213 * |
| 214 * HIF_DEVICE_DEBUG_BUS_STATE |
| 215 * input : none |
| 216 * output : none |
| 217 * note: This configure option triggers the HIF interface to dump as much bus
interface state. This |
| 218 * configuration request is optional (No-OP on some HIF implementations) |
| 219 * |
| 220 */ |
| 221 |
| 222 typedef struct { |
| 223 A_UINT32 ExtendedAddress; /* extended address for larger writes */ |
| 224 A_UINT32 ExtendedSize; |
| 225 } HIF_MBOX_PROPERTIES; |
| 226 |
| 227 typedef struct { |
| 228 A_UINT32 MboxAddresses[4]; /* must be first element for legacy HIFs that re
turn the address in |
| 229 and ARRAY of 32-bit words */ |
| 230 |
| 231 /* the following describe extended mailbox properties */ |
| 232 HIF_MBOX_PROPERTIES MboxProp[4]; |
| 233 /* if the HIF supports the GMbox extended address region it can report i
t |
| 234 * here, some interfaces cannot support the GMBOX address range and not
set this */ |
| 235 A_UINT32 GMboxAddress; |
| 236 A_UINT32 GMboxSize; |
| 237 } HIF_DEVICE_MBOX_INFO; |
| 238 |
| 239 typedef enum { |
| 240 HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR
to process all |
| 241 interrupts before returning */ |
| 242 HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to pro
cess interrupts |
| 243 using ASYNC I/O (that is HIFAckInterrupt can
be called at a |
| 244 later time */ |
| 245 } HIF_DEVICE_IRQ_PROCESSING_MODE; |
| 246 |
| 247 typedef enum { |
| 248 HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module
*/ |
| 249 HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures t
o minimize power */ |
| 250 HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR pla
tform-specific measures |
| 251 to completely power-off the module and associated
hardware (i.e. cut power supplies) |
| 252 */ |
| 253 } HIF_DEVICE_POWER_CHANGE_TYPE; |
| 254 |
| 255 typedef struct { |
| 256 int RecvPacketYieldCount; /* max number of packets to force DSR to retur
n */ |
| 257 } HIF_DEVICE_IRQ_YIELD_PARAMS; |
| 258 |
| 259 |
| 260 typedef struct _HIF_SCATTER_ITEM { |
| 261 A_UINT8 *pBuffer; /* CPU accessible address of buffer */ |
| 262 int Length; /* length of transfer to/from this buffer
*/ |
| 263 void *pCallerContexts[2]; /* space for caller to insert a context as
sociated with this item */ |
| 264 } HIF_SCATTER_ITEM; |
| 265 |
| 266 struct _HIF_SCATTER_REQ; |
| 267 |
| 268 typedef void ( *HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *); |
| 269 |
| 270 typedef enum _HIF_SCATTER_METHOD { |
| 271 HIF_SCATTER_NONE = 0, |
| 272 HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */ |
| 273 HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA but HIF layer uses an inte
rnal bounce buffer */ |
| 274 } HIF_SCATTER_METHOD; |
| 275 |
| 276 typedef struct _HIF_SCATTER_REQ { |
| 277 DL_LIST ListLink; /* link management */ |
| 278 A_UINT32 Address; /* address for the read/write operat
ion */ |
| 279 A_UINT32 Request; /* request flags */ |
| 280 A_UINT32 TotalLength; /* total length of entire transfer *
/ |
| 281 A_UINT32 CallerFlags; /* caller specific flags can be stor
ed here */ |
| 282 HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller
*/ |
| 283 A_STATUS CompletionStatus; /* status of completion */ |
| 284 void *Context; /* caller context for this request *
/ |
| 285 int ValidScatterEntries; /* number of valid entries set by
caller */ |
| 286 HIF_SCATTER_METHOD ScatterMethod; /* scatter method handled by HIF *
/ |
| 287 void *HIFPrivate[4]; /* HIF private area */ |
| 288 A_UINT8 *pScatterBounceBuffer; /* bounce buffer for upper layer
s to copy to/from */ |
| 289 HIF_SCATTER_ITEM ScatterList[1]; /* start of scatter list */ |
| 290 } HIF_SCATTER_REQ; |
| 291 |
| 292 typedef HIF_SCATTER_REQ * ( *HIF_ALLOCATE_SCATTER_REQUEST)(HIF_DEVICE *device); |
| 293 typedef void ( *HIF_FREE_SCATTER_REQUEST)(HIF_DEVICE *device, HIF_SCATTER_REQ *r
equest); |
| 294 typedef A_STATUS ( *HIF_READWRITE_SCATTER)(HIF_DEVICE *device, HIF_SCATTER_REQ *
request); |
| 295 |
| 296 typedef struct _HIF_DEVICE_SCATTER_SUPPORT_INFO { |
| 297 /* information returned from HIF layer */ |
| 298 HIF_ALLOCATE_SCATTER_REQUEST pAllocateReqFunc; |
| 299 HIF_FREE_SCATTER_REQUEST pFreeReqFunc; |
| 300 HIF_READWRITE_SCATTER pReadWriteScatterFunc; |
| 301 int MaxScatterEntries; |
| 302 int MaxTransferSizePerScatterReq; |
| 303 } HIF_DEVICE_SCATTER_SUPPORT_INFO; |
| 304 |
| 305 typedef struct { |
| 306 void *pOSDevice; |
| 307 } HIF_DEVICE_OS_DEVICE_INFO; |
| 308 |
| 309 #define HIF_MAX_DEVICES 1 |
| 310 |
| 311 struct htc_callbacks { |
| 312 void *context; /* context to pass to the dsrhandler |
| 313 note : rwCompletionHandler is provided the contex
t passed to HIFReadWrite */ |
| 314 A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status); |
| 315 A_STATUS (* dsrHandler)(void *context); |
| 316 }; |
| 317 |
| 318 typedef struct osdrv_callbacks { |
| 319 void *context; /* context to pass for all callbacks except deviceRe
movedHandler |
| 320 the deviceRemovedHandler is only called if the de
vice is claimed */ |
| 321 A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle); |
| 322 A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle); |
| 323 A_STATUS (* deviceSuspendHandler)(void *context); |
| 324 A_STATUS (* deviceResumeHandler)(void *context); |
| 325 A_STATUS (* deviceWakeupHandler)(void *context); |
| 326 } OSDRV_CALLBACKS; |
| 327 |
| 328 #define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pendi
ng, host |
| 329 needs to read the register table to f
igure out what */ |
| 330 #define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ |
| 331 |
| 332 typedef struct _HIF_PENDING_EVENTS_INFO { |
| 333 A_UINT32 Events; |
| 334 A_UINT32 LookAhead; |
| 335 A_UINT32 AvailableRecvBytes; |
| 336 } HIF_PENDING_EVENTS_INFO; |
| 337 |
| 338 /* function to get pending events , some HIF modules use special mechanisms |
| 339 * to detect packet available and other interrupts */ |
| 340 typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, |
| 341 HIF_PENDING_EVENTS_INFO *pEvents, |
| 342 void *AsyncConte
xt); |
| 343 |
| 344 #define HIF_MASK_RECV TRUE |
| 345 #define HIF_UNMASK_RECV FALSE |
| 346 /* function to mask recv events */ |
| 347 typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, |
| 348 A_BOOL Mask, |
| 349 void *AsyncContext); |
| 350 |
| 351 |
| 352 /* |
| 353 * This API is used to perform any global initialization of the HIF layer |
| 354 * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer |
| 355 * |
| 356 */ |
| 357 A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks); |
| 358 |
| 359 /* This API claims the HIF device and provides a context for handling removal. |
| 360 * The device removal callback is only called when the OSDRV layer claims |
| 361 * a device. The claimed context must be non-NULL */ |
| 362 void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext); |
| 363 /* release the claimed device */ |
| 364 void HIFReleaseDevice(HIF_DEVICE *device); |
| 365 |
| 366 /* This API allows the HTC layer to attach to the HIF device */ |
| 367 A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks); |
| 368 /* This API detaches the HTC layer from the HIF device */ |
| 369 void HIFDetachHTC(HIF_DEVICE *device); |
| 370 |
| 371 /* |
| 372 * This API is used to provide the read/write interface over the specific bus |
| 373 * interface. |
| 374 * address - Starting address in the AR6000's address space. For mailbox |
| 375 * writes, it refers to the start of the mbox boundary. It should |
| 376 * be ensured that the last byte falls on the mailbox's EOM. For |
| 377 * mailbox reads, it refers to the end of the mbox boundary. |
| 378 * buffer - Pointer to the buffer containg the data to be transmitted or |
| 379 * received. |
| 380 * length - Amount of data to be transmitted or received. |
| 381 * request - Characterizes the attributes of the command. |
| 382 */ |
| 383 A_STATUS |
| 384 HIFReadWrite(HIF_DEVICE *device, |
| 385 A_UINT32 address, |
| 386 A_UCHAR *buffer, |
| 387 A_UINT32 length, |
| 388 A_UINT32 request, |
| 389 void *context); |
| 390 |
| 391 /* |
| 392 * This can be initiated from the unload driver context when the OSDRV layer has
no more use for |
| 393 * the device. |
| 394 */ |
| 395 void HIFShutDownDevice(HIF_DEVICE *device); |
| 396 |
| 397 /* |
| 398 * This should translate to an acknowledgment to the bus driver indicating that |
| 399 * the previous interrupt request has been serviced and the all the relevant |
| 400 * sources have been cleared. HTC is ready to process more interrupts. |
| 401 * This should prevent the bus driver from raising an interrupt unless the |
| 402 * previous one has been serviced and acknowledged using the previous API. |
| 403 */ |
| 404 void HIFAckInterrupt(HIF_DEVICE *device); |
| 405 |
| 406 void HIFMaskInterrupt(HIF_DEVICE *device); |
| 407 |
| 408 void HIFUnMaskInterrupt(HIF_DEVICE *device); |
| 409 |
| 410 A_STATUS |
| 411 HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, |
| 412 void *config, A_UINT32 configLen); |
| 413 |
| 414 #ifdef __cplusplus |
| 415 } |
| 416 #endif |
| 417 |
| 418 #endif /* _HIF_H_ */ |
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