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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _UART_REG_REG_H_ |
| 21 #define _UART_REG_REG_H_ |
| 22 |
| 23 #define UART_DATA_ADDRESS 0x00000000 |
| 24 #define UART_DATA_OFFSET 0x00000000 |
| 25 #define UART_DATA_TX_CSR_MSB 9 |
| 26 #define UART_DATA_TX_CSR_LSB 9 |
| 27 #define UART_DATA_TX_CSR_MASK 0x00000200 |
| 28 #define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK)
>> UART_DATA_TX_CSR_LSB) |
| 29 #define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB)
& UART_DATA_TX_CSR_MASK) |
| 30 #define UART_DATA_RX_CSR_MSB 8 |
| 31 #define UART_DATA_RX_CSR_LSB 8 |
| 32 #define UART_DATA_RX_CSR_MASK 0x00000100 |
| 33 #define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK)
>> UART_DATA_RX_CSR_LSB) |
| 34 #define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB)
& UART_DATA_RX_CSR_MASK) |
| 35 #define UART_DATA_TXRX_DATA_MSB 7 |
| 36 #define UART_DATA_TXRX_DATA_LSB 0 |
| 37 #define UART_DATA_TXRX_DATA_MASK 0x000000ff |
| 38 #define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MAS
K) >> UART_DATA_TXRX_DATA_LSB) |
| 39 #define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LS
B) & UART_DATA_TXRX_DATA_MASK) |
| 40 |
| 41 #define UART_CONTROL_ADDRESS 0x00000004 |
| 42 #define UART_CONTROL_OFFSET 0x00000004 |
| 43 #define UART_CONTROL_RX_BUSY_MSB 15 |
| 44 #define UART_CONTROL_RX_BUSY_LSB 15 |
| 45 #define UART_CONTROL_RX_BUSY_MASK 0x00008000 |
| 46 #define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MA
SK) >> UART_CONTROL_RX_BUSY_LSB) |
| 47 #define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_L
SB) & UART_CONTROL_RX_BUSY_MASK) |
| 48 #define UART_CONTROL_TX_BUSY_MSB 14 |
| 49 #define UART_CONTROL_TX_BUSY_LSB 14 |
| 50 #define UART_CONTROL_TX_BUSY_MASK 0x00004000 |
| 51 #define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MA
SK) >> UART_CONTROL_TX_BUSY_LSB) |
| 52 #define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_L
SB) & UART_CONTROL_TX_BUSY_MASK) |
| 53 #define UART_CONTROL_HOST_INT_ENABLE_MSB 13 |
| 54 #define UART_CONTROL_HOST_INT_ENABLE_LSB 13 |
| 55 #define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000 |
| 56 #define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_E
NABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB) |
| 57 #define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_
ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK) |
| 58 #define UART_CONTROL_HOST_INT_MSB 12 |
| 59 #define UART_CONTROL_HOST_INT_LSB 12 |
| 60 #define UART_CONTROL_HOST_INT_MASK 0x00001000 |
| 61 #define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_M
ASK) >> UART_CONTROL_HOST_INT_LSB) |
| 62 #define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_
LSB) & UART_CONTROL_HOST_INT_MASK) |
| 63 #define UART_CONTROL_TX_BREAK_MSB 11 |
| 64 #define UART_CONTROL_TX_BREAK_LSB 11 |
| 65 #define UART_CONTROL_TX_BREAK_MASK 0x00000800 |
| 66 #define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_M
ASK) >> UART_CONTROL_TX_BREAK_LSB) |
| 67 #define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_
LSB) & UART_CONTROL_TX_BREAK_MASK) |
| 68 #define UART_CONTROL_RX_BREAK_MSB 10 |
| 69 #define UART_CONTROL_RX_BREAK_LSB 10 |
| 70 #define UART_CONTROL_RX_BREAK_MASK 0x00000400 |
| 71 #define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_M
ASK) >> UART_CONTROL_RX_BREAK_LSB) |
| 72 #define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_
LSB) & UART_CONTROL_RX_BREAK_MASK) |
| 73 #define UART_CONTROL_SERIAL_TX_READY_MSB 9 |
| 74 #define UART_CONTROL_SERIAL_TX_READY_LSB 9 |
| 75 #define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200 |
| 76 #define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_
READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB) |
| 77 #define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX
_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK) |
| 78 #define UART_CONTROL_TX_READY_ORIDE_MSB 8 |
| 79 #define UART_CONTROL_TX_READY_ORIDE_LSB 8 |
| 80 #define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100 |
| 81 #define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_O
RIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB) |
| 82 #define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_
ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK) |
| 83 #define UART_CONTROL_RX_READY_ORIDE_MSB 7 |
| 84 #define UART_CONTROL_RX_READY_ORIDE_LSB 7 |
| 85 #define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080 |
| 86 #define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_O
RIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB) |
| 87 #define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_
ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK) |
| 88 #define UART_CONTROL_DMA_ENABLE_MSB 6 |
| 89 #define UART_CONTROL_DMA_ENABLE_LSB 6 |
| 90 #define UART_CONTROL_DMA_ENABLE_MASK 0x00000040 |
| 91 #define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE
_MASK) >> UART_CONTROL_DMA_ENABLE_LSB) |
| 92 #define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABL
E_LSB) & UART_CONTROL_DMA_ENABLE_MASK) |
| 93 #define UART_CONTROL_FLOW_ENABLE_MSB 5 |
| 94 #define UART_CONTROL_FLOW_ENABLE_LSB 5 |
| 95 #define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020 |
| 96 #define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABL
E_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB) |
| 97 #define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENAB
LE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK) |
| 98 #define UART_CONTROL_FLOW_INVERT_MSB 4 |
| 99 #define UART_CONTROL_FLOW_INVERT_LSB 4 |
| 100 #define UART_CONTROL_FLOW_INVERT_MASK 0x00000010 |
| 101 #define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVER
T_MASK) >> UART_CONTROL_FLOW_INVERT_LSB) |
| 102 #define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVE
RT_LSB) & UART_CONTROL_FLOW_INVERT_MASK) |
| 103 #define UART_CONTROL_IFC_ENABLE_MSB 3 |
| 104 #define UART_CONTROL_IFC_ENABLE_LSB 3 |
| 105 #define UART_CONTROL_IFC_ENABLE_MASK 0x00000008 |
| 106 #define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE
_MASK) >> UART_CONTROL_IFC_ENABLE_LSB) |
| 107 #define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABL
E_LSB) & UART_CONTROL_IFC_ENABLE_MASK) |
| 108 #define UART_CONTROL_IFC_DCE_MSB 2 |
| 109 #define UART_CONTROL_IFC_DCE_LSB 2 |
| 110 #define UART_CONTROL_IFC_DCE_MASK 0x00000004 |
| 111 #define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MA
SK) >> UART_CONTROL_IFC_DCE_LSB) |
| 112 #define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_L
SB) & UART_CONTROL_IFC_DCE_MASK) |
| 113 #define UART_CONTROL_PARITY_ENABLE_MSB 1 |
| 114 #define UART_CONTROL_PARITY_ENABLE_LSB 1 |
| 115 #define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002 |
| 116 #define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENA
BLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB) |
| 117 #define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_EN
ABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK) |
| 118 #define UART_CONTROL_PARITY_EVEN_MSB 0 |
| 119 #define UART_CONTROL_PARITY_EVEN_LSB 0 |
| 120 #define UART_CONTROL_PARITY_EVEN_MASK 0x00000001 |
| 121 #define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVE
N_MASK) >> UART_CONTROL_PARITY_EVEN_LSB) |
| 122 #define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EV
EN_LSB) & UART_CONTROL_PARITY_EVEN_MASK) |
| 123 |
| 124 #define UART_CLKDIV_ADDRESS 0x00000008 |
| 125 #define UART_CLKDIV_OFFSET 0x00000008 |
| 126 #define UART_CLKDIV_CLK_SCALE_MSB 23 |
| 127 #define UART_CLKDIV_CLK_SCALE_LSB 16 |
| 128 #define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000 |
| 129 #define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_M
ASK) >> UART_CLKDIV_CLK_SCALE_LSB) |
| 130 #define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_
LSB) & UART_CLKDIV_CLK_SCALE_MASK) |
| 131 #define UART_CLKDIV_CLK_STEP_MSB 15 |
| 132 #define UART_CLKDIV_CLK_STEP_LSB 0 |
| 133 #define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff |
| 134 #define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MA
SK) >> UART_CLKDIV_CLK_STEP_LSB) |
| 135 #define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_L
SB) & UART_CLKDIV_CLK_STEP_MASK) |
| 136 |
| 137 #define UART_INT_ADDRESS 0x0000000c |
| 138 #define UART_INT_OFFSET 0x0000000c |
| 139 #define UART_INT_TX_EMPTY_INT_MSB 9 |
| 140 #define UART_INT_TX_EMPTY_INT_LSB 9 |
| 141 #define UART_INT_TX_EMPTY_INT_MASK 0x00000200 |
| 142 #define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_M
ASK) >> UART_INT_TX_EMPTY_INT_LSB) |
| 143 #define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_
LSB) & UART_INT_TX_EMPTY_INT_MASK) |
| 144 #define UART_INT_RX_FULL_INT_MSB 8 |
| 145 #define UART_INT_RX_FULL_INT_LSB 8 |
| 146 #define UART_INT_RX_FULL_INT_MASK 0x00000100 |
| 147 #define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MA
SK) >> UART_INT_RX_FULL_INT_LSB) |
| 148 #define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_L
SB) & UART_INT_RX_FULL_INT_MASK) |
| 149 #define UART_INT_RX_BREAK_OFF_INT_MSB 7 |
| 150 #define UART_INT_RX_BREAK_OFF_INT_LSB 7 |
| 151 #define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080 |
| 152 #define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_I
NT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB) |
| 153 #define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_
INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK) |
| 154 #define UART_INT_RX_BREAK_ON_INT_MSB 6 |
| 155 #define UART_INT_RX_BREAK_ON_INT_LSB 6 |
| 156 #define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040 |
| 157 #define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_IN
T_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB) |
| 158 #define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_I
NT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK) |
| 159 #define UART_INT_RX_PARITY_ERR_INT_MSB 5 |
| 160 #define UART_INT_RX_PARITY_ERR_INT_LSB 5 |
| 161 #define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020 |
| 162 #define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_
INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB) |
| 163 #define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR
_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK) |
| 164 #define UART_INT_TX_OFLOW_ERR_INT_MSB 4 |
| 165 #define UART_INT_TX_OFLOW_ERR_INT_LSB 4 |
| 166 #define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010 |
| 167 #define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_I
NT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB) |
| 168 #define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_
INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK) |
| 169 #define UART_INT_RX_OFLOW_ERR_INT_MSB 3 |
| 170 #define UART_INT_RX_OFLOW_ERR_INT_LSB 3 |
| 171 #define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008 |
| 172 #define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_I
NT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB) |
| 173 #define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_
INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK) |
| 174 #define UART_INT_RX_FRAMING_ERR_INT_MSB 2 |
| 175 #define UART_INT_RX_FRAMING_ERR_INT_LSB 2 |
| 176 #define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004 |
| 177 #define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR
_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB) |
| 178 #define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ER
R_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK) |
| 179 #define UART_INT_TX_READY_INT_MSB 1 |
| 180 #define UART_INT_TX_READY_INT_LSB 1 |
| 181 #define UART_INT_TX_READY_INT_MASK 0x00000002 |
| 182 #define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_M
ASK) >> UART_INT_TX_READY_INT_LSB) |
| 183 #define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_
LSB) & UART_INT_TX_READY_INT_MASK) |
| 184 #define UART_INT_RX_VALID_INT_MSB 0 |
| 185 #define UART_INT_RX_VALID_INT_LSB 0 |
| 186 #define UART_INT_RX_VALID_INT_MASK 0x00000001 |
| 187 #define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_M
ASK) >> UART_INT_RX_VALID_INT_LSB) |
| 188 #define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_
LSB) & UART_INT_RX_VALID_INT_MASK) |
| 189 |
| 190 #define UART_INT_EN_ADDRESS 0x00000010 |
| 191 #define UART_INT_EN_OFFSET 0x00000010 |
| 192 #define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9 |
| 193 #define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9 |
| 194 #define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200 |
| 195 #define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_IN
T_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB) |
| 196 #define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_I
NT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) |
| 197 #define UART_INT_EN_RX_FULL_INT_EN_MSB 8 |
| 198 #define UART_INT_EN_RX_FULL_INT_EN_LSB 8 |
| 199 #define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100 |
| 200 #define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT
_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB) |
| 201 #define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_IN
T_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK) |
| 202 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7 |
| 203 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7 |
| 204 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080 |
| 205 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OF
F_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) |
| 206 #define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_O
FF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) |
| 207 #define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6 |
| 208 #define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6 |
| 209 #define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040 |
| 210 #define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON
_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) |
| 211 #define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_O
N_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) |
| 212 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5 |
| 213 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5 |
| 214 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020 |
| 215 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_E
RR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) |
| 216 #define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_
ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) |
| 217 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4 |
| 218 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4 |
| 219 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010 |
| 220 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ER
R_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) |
| 221 #define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_E
RR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) |
| 222 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3 |
| 223 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3 |
| 224 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008 |
| 225 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ER
R_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) |
| 226 #define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_E
RR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) |
| 227 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2 |
| 228 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2 |
| 229 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004 |
| 230 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_
ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) |
| 231 #define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING
_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) |
| 232 #define UART_INT_EN_TX_READY_INT_EN_MSB 1 |
| 233 #define UART_INT_EN_TX_READY_INT_EN_LSB 1 |
| 234 #define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002 |
| 235 #define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_IN
T_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB) |
| 236 #define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_I
NT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK) |
| 237 #define UART_INT_EN_RX_VALID_INT_EN_MSB 0 |
| 238 #define UART_INT_EN_RX_VALID_INT_EN_LSB 0 |
| 239 #define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001 |
| 240 #define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_IN
T_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB) |
| 241 #define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_I
NT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK) |
| 242 |
| 243 |
| 244 #ifndef __ASSEMBLER__ |
| 245 |
| 246 typedef struct uart_reg_reg_s { |
| 247 volatile unsigned int uart_data; |
| 248 volatile unsigned int uart_control; |
| 249 volatile unsigned int uart_clkdiv; |
| 250 volatile unsigned int uart_int; |
| 251 volatile unsigned int uart_int_en; |
| 252 } uart_reg_reg_t; |
| 253 |
| 254 #endif /* __ASSEMBLER__ */ |
| 255 |
| 256 #endif /* _UART_REG_H_ */ |
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