OLD | NEW |
(Empty) | |
| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _MBOX_WLAN_HOST_REG_REG_H_ |
| 21 #define _MBOX_WLAN_HOST_REG_REG_H_ |
| 22 |
| 23 #define HOST_INT_STATUS_ADDRESS 0x00000400 |
| 24 #define HOST_INT_STATUS_OFFSET 0x00000400 |
| 25 #define HOST_INT_STATUS_ERROR_MSB 7 |
| 26 #define HOST_INT_STATUS_ERROR_LSB 7 |
| 27 #define HOST_INT_STATUS_ERROR_MASK 0x00000080 |
| 28 #define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_M
ASK) >> HOST_INT_STATUS_ERROR_LSB) |
| 29 #define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_
LSB) & HOST_INT_STATUS_ERROR_MASK) |
| 30 #define HOST_INT_STATUS_CPU_MSB 6 |
| 31 #define HOST_INT_STATUS_CPU_LSB 6 |
| 32 #define HOST_INT_STATUS_CPU_MASK 0x00000040 |
| 33 #define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MAS
K) >> HOST_INT_STATUS_CPU_LSB) |
| 34 #define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LS
B) & HOST_INT_STATUS_CPU_MASK) |
| 35 #define HOST_INT_STATUS_INT_MSB 5 |
| 36 #define HOST_INT_STATUS_INT_LSB 5 |
| 37 #define HOST_INT_STATUS_INT_MASK 0x00000020 |
| 38 #define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MAS
K) >> HOST_INT_STATUS_INT_LSB) |
| 39 #define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LS
B) & HOST_INT_STATUS_INT_MASK) |
| 40 #define HOST_INT_STATUS_COUNTER_MSB 4 |
| 41 #define HOST_INT_STATUS_COUNTER_LSB 4 |
| 42 #define HOST_INT_STATUS_COUNTER_MASK 0x00000010 |
| 43 #define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER
_MASK) >> HOST_INT_STATUS_COUNTER_LSB) |
| 44 #define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTE
R_LSB) & HOST_INT_STATUS_COUNTER_MASK) |
| 45 #define HOST_INT_STATUS_MBOX_DATA_MSB 3 |
| 46 #define HOST_INT_STATUS_MBOX_DATA_LSB 0 |
| 47 #define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f |
| 48 #define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DA
TA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) |
| 49 #define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_D
ATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) |
| 50 |
| 51 #define CPU_INT_STATUS_ADDRESS 0x00000401 |
| 52 #define CPU_INT_STATUS_OFFSET 0x00000401 |
| 53 #define CPU_INT_STATUS_BIT_MSB 7 |
| 54 #define CPU_INT_STATUS_BIT_LSB 0 |
| 55 #define CPU_INT_STATUS_BIT_MASK 0x000000ff |
| 56 #define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK
) >> CPU_INT_STATUS_BIT_LSB) |
| 57 #define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB
) & CPU_INT_STATUS_BIT_MASK) |
| 58 |
| 59 #define ERROR_INT_STATUS_ADDRESS 0x00000402 |
| 60 #define ERROR_INT_STATUS_OFFSET 0x00000402 |
| 61 #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 |
| 62 #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 |
| 63 #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 |
| 64 #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STA
TUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ER
ROR_LSB) |
| 65 #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_ST
ATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERR
OR_MASK) |
| 66 #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5 |
| 67 #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5 |
| 68 #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 |
| 69 #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATU
S_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LS
B) |
| 70 #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STAT
US_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MAS
K) |
| 71 #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4 |
| 72 #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4 |
| 73 #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 |
| 74 #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STAT
US_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW
_LSB) |
| 75 #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STA
TUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_
MASK) |
| 76 #define ERROR_INT_STATUS_SPI_MSB 3 |
| 77 #define ERROR_INT_STATUS_SPI_LSB 3 |
| 78 #define ERROR_INT_STATUS_SPI_MASK 0x00000008 |
| 79 #define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MA
SK) >> ERROR_INT_STATUS_SPI_LSB) |
| 80 #define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_L
SB) & ERROR_INT_STATUS_SPI_MASK) |
| 81 #define ERROR_INT_STATUS_WAKEUP_MSB 2 |
| 82 #define ERROR_INT_STATUS_WAKEUP_LSB 2 |
| 83 #define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 |
| 84 #define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP
_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) |
| 85 #define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEU
P_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) |
| 86 #define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 |
| 87 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 |
| 88 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 |
| 89 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UND
ERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) |
| 90 #define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UN
DERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) |
| 91 #define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 |
| 92 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 |
| 93 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 |
| 94 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVE
RFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) |
| 95 #define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OV
ERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) |
| 96 |
| 97 #define COUNTER_INT_STATUS_ADDRESS 0x00000403 |
| 98 #define COUNTER_INT_STATUS_OFFSET 0x00000403 |
| 99 #define COUNTER_INT_STATUS_COUNTER_MSB 7 |
| 100 #define COUNTER_INT_STATUS_COUNTER_LSB 0 |
| 101 #define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff |
| 102 #define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUN
TER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) |
| 103 #define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COU
NTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) |
| 104 |
| 105 #define MBOX_FRAME_ADDRESS 0x00000404 |
| 106 #define MBOX_FRAME_OFFSET 0x00000404 |
| 107 #define MBOX_FRAME_RX_EOM_MSB 7 |
| 108 #define MBOX_FRAME_RX_EOM_LSB 4 |
| 109 #define MBOX_FRAME_RX_EOM_MASK 0x000000f0 |
| 110 #define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK)
>> MBOX_FRAME_RX_EOM_LSB) |
| 111 #define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB)
& MBOX_FRAME_RX_EOM_MASK) |
| 112 #define MBOX_FRAME_RX_SOM_MSB 3 |
| 113 #define MBOX_FRAME_RX_SOM_LSB 0 |
| 114 #define MBOX_FRAME_RX_SOM_MASK 0x0000000f |
| 115 #define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK)
>> MBOX_FRAME_RX_SOM_LSB) |
| 116 #define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB)
& MBOX_FRAME_RX_SOM_MASK) |
| 117 |
| 118 #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 |
| 119 #define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 |
| 120 #define RX_LOOKAHEAD_VALID_MBOX_MSB 3 |
| 121 #define RX_LOOKAHEAD_VALID_MBOX_LSB 0 |
| 122 #define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f |
| 123 #define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX
_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) |
| 124 #define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBO
X_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) |
| 125 |
| 126 #define HOST_INT_STATUS2_ADDRESS 0x00000406 |
| 127 #define HOST_INT_STATUS2_OFFSET 0x00000406 |
| 128 #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2 |
| 129 #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2 |
| 130 #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004 |
| 131 #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBO
X_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) |
| 132 #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMB
OX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) |
| 133 #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1 |
| 134 #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1 |
| 135 #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002 |
| 136 #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX
_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) |
| 137 #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBO
X_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) |
| 138 #define HOST_INT_STATUS2_GMBOX_DATA_MSB 0 |
| 139 #define HOST_INT_STATUS2_GMBOX_DATA_LSB 0 |
| 140 #define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001 |
| 141 #define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_
DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB) |
| 142 #define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX
_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK) |
| 143 |
| 144 #define GMBOX_RX_AVAIL_ADDRESS 0x00000407 |
| 145 #define GMBOX_RX_AVAIL_OFFSET 0x00000407 |
| 146 #define GMBOX_RX_AVAIL_BYTE_MSB 6 |
| 147 #define GMBOX_RX_AVAIL_BYTE_LSB 0 |
| 148 #define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f |
| 149 #define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MAS
K) >> GMBOX_RX_AVAIL_BYTE_LSB) |
| 150 #define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LS
B) & GMBOX_RX_AVAIL_BYTE_MASK) |
| 151 |
| 152 #define RX_LOOKAHEAD0_ADDRESS 0x00000408 |
| 153 #define RX_LOOKAHEAD0_OFFSET 0x00000408 |
| 154 #define RX_LOOKAHEAD0_DATA_MSB 7 |
| 155 #define RX_LOOKAHEAD0_DATA_LSB 0 |
| 156 #define RX_LOOKAHEAD0_DATA_MASK 0x000000ff |
| 157 #define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK
) >> RX_LOOKAHEAD0_DATA_LSB) |
| 158 #define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB
) & RX_LOOKAHEAD0_DATA_MASK) |
| 159 |
| 160 #define RX_LOOKAHEAD1_ADDRESS 0x0000040c |
| 161 #define RX_LOOKAHEAD1_OFFSET 0x0000040c |
| 162 #define RX_LOOKAHEAD1_DATA_MSB 7 |
| 163 #define RX_LOOKAHEAD1_DATA_LSB 0 |
| 164 #define RX_LOOKAHEAD1_DATA_MASK 0x000000ff |
| 165 #define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK
) >> RX_LOOKAHEAD1_DATA_LSB) |
| 166 #define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB
) & RX_LOOKAHEAD1_DATA_MASK) |
| 167 |
| 168 #define RX_LOOKAHEAD2_ADDRESS 0x00000410 |
| 169 #define RX_LOOKAHEAD2_OFFSET 0x00000410 |
| 170 #define RX_LOOKAHEAD2_DATA_MSB 7 |
| 171 #define RX_LOOKAHEAD2_DATA_LSB 0 |
| 172 #define RX_LOOKAHEAD2_DATA_MASK 0x000000ff |
| 173 #define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK
) >> RX_LOOKAHEAD2_DATA_LSB) |
| 174 #define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB
) & RX_LOOKAHEAD2_DATA_MASK) |
| 175 |
| 176 #define RX_LOOKAHEAD3_ADDRESS 0x00000414 |
| 177 #define RX_LOOKAHEAD3_OFFSET 0x00000414 |
| 178 #define RX_LOOKAHEAD3_DATA_MSB 7 |
| 179 #define RX_LOOKAHEAD3_DATA_LSB 0 |
| 180 #define RX_LOOKAHEAD3_DATA_MASK 0x000000ff |
| 181 #define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK
) >> RX_LOOKAHEAD3_DATA_LSB) |
| 182 #define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB
) & RX_LOOKAHEAD3_DATA_MASK) |
| 183 |
| 184 #define INT_STATUS_ENABLE_ADDRESS 0x00000418 |
| 185 #define INT_STATUS_ENABLE_OFFSET 0x00000418 |
| 186 #define INT_STATUS_ENABLE_ERROR_MSB 7 |
| 187 #define INT_STATUS_ENABLE_ERROR_LSB 7 |
| 188 #define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 |
| 189 #define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR
_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) |
| 190 #define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERRO
R_LSB) & INT_STATUS_ENABLE_ERROR_MASK) |
| 191 #define INT_STATUS_ENABLE_CPU_MSB 6 |
| 192 #define INT_STATUS_ENABLE_CPU_LSB 6 |
| 193 #define INT_STATUS_ENABLE_CPU_MASK 0x00000040 |
| 194 #define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_M
ASK) >> INT_STATUS_ENABLE_CPU_LSB) |
| 195 #define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_
LSB) & INT_STATUS_ENABLE_CPU_MASK) |
| 196 #define INT_STATUS_ENABLE_INT_MSB 5 |
| 197 #define INT_STATUS_ENABLE_INT_LSB 5 |
| 198 #define INT_STATUS_ENABLE_INT_MASK 0x00000020 |
| 199 #define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_M
ASK) >> INT_STATUS_ENABLE_INT_LSB) |
| 200 #define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_
LSB) & INT_STATUS_ENABLE_INT_MASK) |
| 201 #define INT_STATUS_ENABLE_COUNTER_MSB 4 |
| 202 #define INT_STATUS_ENABLE_COUNTER_LSB 4 |
| 203 #define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 |
| 204 #define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNT
ER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) |
| 205 #define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUN
TER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) |
| 206 #define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 |
| 207 #define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 |
| 208 #define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f |
| 209 #define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_
DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) |
| 210 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX
_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) |
| 211 |
| 212 #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 |
| 213 #define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 |
| 214 #define CPU_INT_STATUS_ENABLE_BIT_MSB 7 |
| 215 #define CPU_INT_STATUS_ENABLE_BIT_LSB 0 |
| 216 #define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff |
| 217 #define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_B
IT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) |
| 218 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_
BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) |
| 219 |
| 220 #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a |
| 221 #define ERROR_STATUS_ENABLE_OFFSET 0x0000041a |
| 222 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 |
| 223 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 |
| 224 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 |
| 225 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STAT
US_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAME
R_SYNC_ERROR_LSB) |
| 226 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STA
TUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER
_SYNC_ERROR_MASK) |
| 227 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5 |
| 228 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5 |
| 229 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 |
| 230 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS
_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OV
ERFLOW_LSB) |
| 231 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATU
S_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVE
RFLOW_MASK) |
| 232 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4 |
| 233 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4 |
| 234 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 |
| 235 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATU
S_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_
UNDERFLOW_LSB) |
| 236 #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STAT
US_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_U
NDERFLOW_MASK) |
| 237 #define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 |
| 238 #define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 |
| 239 #define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 |
| 240 #define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAK
EUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) |
| 241 #define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WA
KEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) |
| 242 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 |
| 243 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 |
| 244 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 |
| 245 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_
UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) |
| 246 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX
_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) |
| 247 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 |
| 248 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 |
| 249 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 |
| 250 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_
OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) |
| 251 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX
_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) |
| 252 |
| 253 #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b |
| 254 #define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b |
| 255 #define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 |
| 256 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 |
| 257 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff |
| 258 #define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENAB
LE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) |
| 259 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENA
BLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) |
| 260 |
| 261 #define COUNT_ADDRESS 0x00000420 |
| 262 #define COUNT_OFFSET 0x00000420 |
| 263 #define COUNT_VALUE_MSB 7 |
| 264 #define COUNT_VALUE_LSB 0 |
| 265 #define COUNT_VALUE_MASK 0x000000ff |
| 266 #define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> CO
UNT_VALUE_LSB) |
| 267 #define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COU
NT_VALUE_MASK) |
| 268 |
| 269 #define COUNT_DEC_ADDRESS 0x00000440 |
| 270 #define COUNT_DEC_OFFSET 0x00000440 |
| 271 #define COUNT_DEC_VALUE_MSB 7 |
| 272 #define COUNT_DEC_VALUE_LSB 0 |
| 273 #define COUNT_DEC_VALUE_MASK 0x000000ff |
| 274 #define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >
> COUNT_DEC_VALUE_LSB) |
| 275 #define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) &
COUNT_DEC_VALUE_MASK) |
| 276 |
| 277 #define SCRATCH_ADDRESS 0x00000460 |
| 278 #define SCRATCH_OFFSET 0x00000460 |
| 279 #define SCRATCH_VALUE_MSB 7 |
| 280 #define SCRATCH_VALUE_LSB 0 |
| 281 #define SCRATCH_VALUE_MASK 0x000000ff |
| 282 #define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >>
SCRATCH_VALUE_LSB) |
| 283 #define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & S
CRATCH_VALUE_MASK) |
| 284 |
| 285 #define FIFO_TIMEOUT_ADDRESS 0x00000468 |
| 286 #define FIFO_TIMEOUT_OFFSET 0x00000468 |
| 287 #define FIFO_TIMEOUT_VALUE_MSB 7 |
| 288 #define FIFO_TIMEOUT_VALUE_LSB 0 |
| 289 #define FIFO_TIMEOUT_VALUE_MASK 0x000000ff |
| 290 #define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK
) >> FIFO_TIMEOUT_VALUE_LSB) |
| 291 #define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB
) & FIFO_TIMEOUT_VALUE_MASK) |
| 292 |
| 293 #define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 |
| 294 #define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 |
| 295 #define FIFO_TIMEOUT_ENABLE_SET_MSB 0 |
| 296 #define FIFO_TIMEOUT_ENABLE_SET_LSB 0 |
| 297 #define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 |
| 298 #define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET
_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) |
| 299 #define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SE
T_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) |
| 300 |
| 301 #define DISABLE_SLEEP_ADDRESS 0x0000046a |
| 302 #define DISABLE_SLEEP_OFFSET 0x0000046a |
| 303 #define DISABLE_SLEEP_FOR_INT_MSB 1 |
| 304 #define DISABLE_SLEEP_FOR_INT_LSB 1 |
| 305 #define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 |
| 306 #define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_M
ASK) >> DISABLE_SLEEP_FOR_INT_LSB) |
| 307 #define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_
LSB) & DISABLE_SLEEP_FOR_INT_MASK) |
| 308 #define DISABLE_SLEEP_ON_MSB 0 |
| 309 #define DISABLE_SLEEP_ON_LSB 0 |
| 310 #define DISABLE_SLEEP_ON_MASK 0x00000001 |
| 311 #define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK)
>> DISABLE_SLEEP_ON_LSB) |
| 312 #define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB)
& DISABLE_SLEEP_ON_MASK) |
| 313 |
| 314 #define LOCAL_BUS_ADDRESS 0x00000470 |
| 315 #define LOCAL_BUS_OFFSET 0x00000470 |
| 316 #define LOCAL_BUS_STATE_MSB 1 |
| 317 #define LOCAL_BUS_STATE_LSB 0 |
| 318 #define LOCAL_BUS_STATE_MASK 0x00000003 |
| 319 #define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >
> LOCAL_BUS_STATE_LSB) |
| 320 #define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) &
LOCAL_BUS_STATE_MASK) |
| 321 |
| 322 #define INT_WLAN_ADDRESS 0x00000472 |
| 323 #define INT_WLAN_OFFSET 0x00000472 |
| 324 #define INT_WLAN_VECTOR_MSB 7 |
| 325 #define INT_WLAN_VECTOR_LSB 0 |
| 326 #define INT_WLAN_VECTOR_MASK 0x000000ff |
| 327 #define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >
> INT_WLAN_VECTOR_LSB) |
| 328 #define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) &
INT_WLAN_VECTOR_MASK) |
| 329 |
| 330 #define WINDOW_DATA_ADDRESS 0x00000474 |
| 331 #define WINDOW_DATA_OFFSET 0x00000474 |
| 332 #define WINDOW_DATA_DATA_MSB 7 |
| 333 #define WINDOW_DATA_DATA_LSB 0 |
| 334 #define WINDOW_DATA_DATA_MASK 0x000000ff |
| 335 #define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK)
>> WINDOW_DATA_DATA_LSB) |
| 336 #define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB)
& WINDOW_DATA_DATA_MASK) |
| 337 |
| 338 #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 |
| 339 #define WINDOW_WRITE_ADDR_OFFSET 0x00000478 |
| 340 #define WINDOW_WRITE_ADDR_ADDR_MSB 7 |
| 341 #define WINDOW_WRITE_ADDR_ADDR_LSB 0 |
| 342 #define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff |
| 343 #define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_
MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) |
| 344 #define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR
_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) |
| 345 |
| 346 #define WINDOW_READ_ADDR_ADDRESS 0x0000047c |
| 347 #define WINDOW_READ_ADDR_OFFSET 0x0000047c |
| 348 #define WINDOW_READ_ADDR_ADDR_MSB 7 |
| 349 #define WINDOW_READ_ADDR_ADDR_LSB 0 |
| 350 #define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff |
| 351 #define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_M
ASK) >> WINDOW_READ_ADDR_ADDR_LSB) |
| 352 #define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_
LSB) & WINDOW_READ_ADDR_ADDR_MASK) |
| 353 |
| 354 #define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480 |
| 355 #define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480 |
| 356 #define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4 |
| 357 #define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4 |
| 358 #define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010 |
| 359 #define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SP
I_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) |
| 360 #define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_S
PI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) |
| 361 #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 |
| 362 #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 |
| 363 #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 |
| 364 #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFI
G_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) |
| 365 #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONF
IG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) |
| 366 #define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2 |
| 367 #define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2 |
| 368 #define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004 |
| 369 #define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TE
ST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) |
| 370 #define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_T
EST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) |
| 371 #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1 |
| 372 #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0 |
| 373 #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003 |
| 374 #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DA
TA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) |
| 375 #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_D
ATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) |
| 376 |
| 377 #define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481 |
| 378 #define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481 |
| 379 #define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3 |
| 380 #define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3 |
| 381 #define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008 |
| 382 #define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_AD
DR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) |
| 383 #define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_A
DDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) |
| 384 #define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2 |
| 385 #define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2 |
| 386 #define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004 |
| 387 #define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD
_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB) |
| 388 #define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_R
D_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) |
| 389 #define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1 |
| 390 #define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1 |
| 391 #define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002 |
| 392 #define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR
_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB) |
| 393 #define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_W
R_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) |
| 394 #define HOST_CTRL_SPI_STATUS_READY_MSB 0 |
| 395 #define HOST_CTRL_SPI_STATUS_READY_LSB 0 |
| 396 #define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001 |
| 397 #define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RE
ADY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB) |
| 398 #define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_R
EADY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK) |
| 399 |
| 400 #define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 |
| 401 #define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 |
| 402 #define NON_ASSOC_SLEEP_EN_BIT_MSB 0 |
| 403 #define NON_ASSOC_SLEEP_EN_BIT_LSB 0 |
| 404 #define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 |
| 405 #define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_
MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) |
| 406 #define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT
_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) |
| 407 |
| 408 #define CPU_DBG_SEL_ADDRESS 0x00000483 |
| 409 #define CPU_DBG_SEL_OFFSET 0x00000483 |
| 410 #define CPU_DBG_SEL_BIT_MSB 5 |
| 411 #define CPU_DBG_SEL_BIT_LSB 0 |
| 412 #define CPU_DBG_SEL_BIT_MASK 0x0000003f |
| 413 #define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >
> CPU_DBG_SEL_BIT_LSB) |
| 414 #define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) &
CPU_DBG_SEL_BIT_MASK) |
| 415 |
| 416 #define CPU_DBG_ADDRESS 0x00000484 |
| 417 #define CPU_DBG_OFFSET 0x00000484 |
| 418 #define CPU_DBG_DATA_MSB 7 |
| 419 #define CPU_DBG_DATA_LSB 0 |
| 420 #define CPU_DBG_DATA_MASK 0x000000ff |
| 421 #define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> C
PU_DBG_DATA_LSB) |
| 422 #define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CP
U_DBG_DATA_MASK) |
| 423 |
| 424 #define INT_STATUS2_ENABLE_ADDRESS 0x00000488 |
| 425 #define INT_STATUS2_ENABLE_OFFSET 0x00000488 |
| 426 #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2 |
| 427 #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2 |
| 428 #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004 |
| 429 #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_
GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) |
| 430 #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE
_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) |
| 431 #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1 |
| 432 #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1 |
| 433 #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002 |
| 434 #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_G
MBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) |
| 435 #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_
GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) |
| 436 #define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0 |
| 437 #define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0 |
| 438 #define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001 |
| 439 #define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBO
X_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB) |
| 440 #define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMB
OX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) |
| 441 |
| 442 #define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490 |
| 443 #define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490 |
| 444 #define GMBOX_RX_LOOKAHEAD_DATA_MSB 7 |
| 445 #define GMBOX_RX_LOOKAHEAD_DATA_LSB 0 |
| 446 #define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff |
| 447 #define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA
_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB) |
| 448 #define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DAT
A_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK) |
| 449 |
| 450 #define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498 |
| 451 #define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498 |
| 452 #define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0 |
| 453 #define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0 |
| 454 #define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001 |
| 455 #define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_
SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) |
| 456 #define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX
_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) |
| 457 |
| 458 #define CIS_WINDOW_ADDRESS 0x00000600 |
| 459 #define CIS_WINDOW_OFFSET 0x00000600 |
| 460 #define CIS_WINDOW_DATA_MSB 7 |
| 461 #define CIS_WINDOW_DATA_LSB 0 |
| 462 #define CIS_WINDOW_DATA_MASK 0x000000ff |
| 463 #define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >
> CIS_WINDOW_DATA_LSB) |
| 464 #define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) &
CIS_WINDOW_DATA_MASK) |
| 465 |
| 466 |
| 467 #ifndef __ASSEMBLER__ |
| 468 |
| 469 typedef struct mbox_wlan_host_reg_reg_s { |
| 470 unsigned char pad0[1024]; /* pad to 0x400 */ |
| 471 volatile unsigned char host_int_status; |
| 472 volatile unsigned char cpu_int_status; |
| 473 volatile unsigned char error_int_status; |
| 474 volatile unsigned char counter_int_status; |
| 475 volatile unsigned char mbox_frame; |
| 476 volatile unsigned char rx_lookahead_valid; |
| 477 volatile unsigned char host_int_status2; |
| 478 volatile unsigned char gmbox_rx_avail; |
| 479 volatile unsigned char rx_lookahead0[4]; |
| 480 volatile unsigned char rx_lookahead1[4]; |
| 481 volatile unsigned char rx_lookahead2[4]; |
| 482 volatile unsigned char rx_lookahead3[4]; |
| 483 volatile unsigned char int_status_enable; |
| 484 volatile unsigned char cpu_int_status_enable; |
| 485 volatile unsigned char error_status_enable; |
| 486 volatile unsigned char counter_int_status_enable; |
| 487 unsigned char pad1[4]; /* pad to 0x420 */ |
| 488 volatile unsigned char count[8]; |
| 489 unsigned char pad2[24]; /* pad to 0x440 */ |
| 490 volatile unsigned char count_dec[32]; |
| 491 volatile unsigned char scratch[8]; |
| 492 volatile unsigned char fifo_timeout; |
| 493 volatile unsigned char fifo_timeout_enable; |
| 494 volatile unsigned char disable_sleep; |
| 495 unsigned char pad3[5]; /* pad to 0x470 */ |
| 496 volatile unsigned char local_bus; |
| 497 unsigned char pad4[1]; /* pad to 0x472 */ |
| 498 volatile unsigned char int_wlan; |
| 499 unsigned char pad5[1]; /* pad to 0x474 */ |
| 500 volatile unsigned char window_data[4]; |
| 501 volatile unsigned char window_write_addr[4]; |
| 502 volatile unsigned char window_read_addr[4]; |
| 503 volatile unsigned char host_ctrl_spi_config; |
| 504 volatile unsigned char host_ctrl_spi_status; |
| 505 volatile unsigned char non_assoc_sleep_en; |
| 506 volatile unsigned char cpu_dbg_sel; |
| 507 volatile unsigned char cpu_dbg[4]; |
| 508 volatile unsigned char int_status2_enable; |
| 509 unsigned char pad6[7]; /* pad to 0x490 */ |
| 510 volatile unsigned char gmbox_rx_lookahead[8]; |
| 511 volatile unsigned char gmbox_rx_lookahead_mux; |
| 512 unsigned char pad7[359]; /* pad to 0x600 */ |
| 513 volatile unsigned char cis_window[512]; |
| 514 } mbox_wlan_host_reg_reg_t; |
| 515 |
| 516 #endif /* __ASSEMBLER__ */ |
| 517 |
| 518 #endif /* _MBOX_WLAN_HOST_REG_H_ */ |
OLD | NEW |