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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _MAC_PCU_REG_H_ |
| 21 #define _MAC_PCU_REG_H_ |
| 22 |
| 23 #define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000 |
| 24 #define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000 |
| 25 #define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31 |
| 26 #define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0 |
| 27 #define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff |
| 28 #define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_AD
DR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) |
| 29 #define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_A
DDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) |
| 30 |
| 31 #define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004 |
| 32 #define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004 |
| 33 #define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31 |
| 34 #define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31 |
| 35 #define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000 |
| 36 #define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_
U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) |
| 37 #define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR
_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) |
| 38 #define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30 |
| 39 #define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30 |
| 40 #define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000 |
| 41 #define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CB
CIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) |
| 42 #define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_C
BCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) |
| 43 #define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29 |
| 44 #define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29 |
| 45 #define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000 |
| 46 #define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16
_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) |
| 47 #define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U1
6_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) |
| 48 #define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28 |
| 49 #define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28 |
| 50 #define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000 |
| 51 #define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KS
RCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) |
| 52 #define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_K
SRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) |
| 53 #define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27 |
| 54 #define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27 |
| 55 #define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000 |
| 56 #define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16
_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) |
| 57 #define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U1
6_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) |
| 58 #define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26 |
| 59 #define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26 |
| 60 #define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000 |
| 61 #define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16
_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) |
| 62 #define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U1
6_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) |
| 63 #define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25 |
| 64 #define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25 |
| 65 #define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000 |
| 66 #define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_B
ASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) |
| 67 #define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_
BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) |
| 68 #define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24 |
| 69 #define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24 |
| 70 #define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000 |
| 71 #define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_AC
KCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) |
| 72 #define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_A
CKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) |
| 73 #define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23 |
| 74 #define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23 |
| 75 #define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000 |
| 76 #define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RT
S_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) |
| 77 #define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_R
TS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) |
| 78 #define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22 |
| 79 #define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22 |
| 80 #define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000 |
| 81 #define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_D
EFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) |
| 82 #define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_
DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) |
| 83 #define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21 |
| 84 #define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21 |
| 85 #define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000 |
| 86 #define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_US
E_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) |
| 87 #define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_U
SE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) |
| 88 #define MAC_PCU_STA_ADDR_U16_PCF_MSB 20 |
| 89 #define MAC_PCU_STA_ADDR_U16_PCF_LSB 20 |
| 90 #define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000 |
| 91 #define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PC
F_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB) |
| 92 #define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_P
CF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK) |
| 93 #define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19 |
| 94 #define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19 |
| 95 #define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000 |
| 96 #define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KE
YSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) |
| 97 #define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_K
EYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) |
| 98 #define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18 |
| 99 #define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18 |
| 100 #define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000 |
| 101 #define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW
_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) |
| 102 #define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_P
W_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) |
| 103 #define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17 |
| 104 #define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17 |
| 105 #define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000 |
| 106 #define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_AD
HOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB) |
| 107 #define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_A
DHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) |
| 108 #define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16 |
| 109 #define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16 |
| 110 #define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000 |
| 111 #define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ST
A_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB) |
| 112 #define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_S
TA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) |
| 113 #define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15 |
| 114 #define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0 |
| 115 #define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff |
| 116 #define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_AD
DR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) |
| 117 #define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_A
DDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) |
| 118 |
| 119 #define MAC_PCU_BSSID_L32_ADDRESS 0x00008008 |
| 120 #define MAC_PCU_BSSID_L32_OFFSET 0x00000008 |
| 121 #define MAC_PCU_BSSID_L32_ADDR_MSB 31 |
| 122 #define MAC_PCU_BSSID_L32_ADDR_LSB 0 |
| 123 #define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff |
| 124 #define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_
MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB) |
| 125 #define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR
_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK) |
| 126 |
| 127 #define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c |
| 128 #define MAC_PCU_BSSID_U16_OFFSET 0x0000000c |
| 129 #define MAC_PCU_BSSID_U16_AID_MSB 26 |
| 130 #define MAC_PCU_BSSID_U16_AID_LSB 16 |
| 131 #define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000 |
| 132 #define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_M
ASK) >> MAC_PCU_BSSID_U16_AID_LSB) |
| 133 #define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_
LSB) & MAC_PCU_BSSID_U16_AID_MASK) |
| 134 #define MAC_PCU_BSSID_U16_ADDR_MSB 15 |
| 135 #define MAC_PCU_BSSID_U16_ADDR_LSB 0 |
| 136 #define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff |
| 137 #define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_
MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB) |
| 138 #define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR
_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK) |
| 139 |
| 140 #define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010 |
| 141 #define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010 |
| 142 #define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11 |
| 143 #define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0 |
| 144 #define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff |
| 145 #define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VA
LUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) |
| 146 #define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_V
ALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) |
| 147 |
| 148 #define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014 |
| 149 #define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014 |
| 150 #define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29 |
| 151 #define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16 |
| 152 #define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000 |
| 153 #define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEO
UT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) |
| 154 #define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIME
OUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) |
| 155 #define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13 |
| 156 #define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0 |
| 157 #define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff |
| 158 #define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEO
UT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) |
| 159 #define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIME
OUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) |
| 160 |
| 161 #define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018 |
| 162 #define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018 |
| 163 #define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29 |
| 164 #define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29 |
| 165 #define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000 |
| 166 #define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RE
SET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB) |
| 167 #define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_R
ESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) |
| 168 #define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28 |
| 169 #define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24 |
| 170 #define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000 |
| 171 #define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WE
IGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) |
| 172 #define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_W
EIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) |
| 173 #define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23 |
| 174 #define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16 |
| 175 #define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000 |
| 176 #define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CT
L_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) |
| 177 #define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_C
TL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) |
| 178 #define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15 |
| 179 #define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8 |
| 180 #define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00 |
| 181 #define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MI
SS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) |
| 182 #define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_M
ISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) |
| 183 #define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7 |
| 184 #define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0 |
| 185 #define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff |
| 186 #define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL
_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) |
| 187 #define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CT
L_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) |
| 188 |
| 189 #define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c |
| 190 #define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c |
| 191 #define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28 |
| 192 #define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23 |
| 193 #define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000 |
| 194 #define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX
_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) |
| 195 #define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_R
X_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) |
| 196 #define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22 |
| 197 #define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14 |
| 198 #define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000 |
| 199 #define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX
_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) |
| 200 #define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_T
X_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) |
| 201 #define MAC_PCU_USEC_LATENCY_USEC_MSB 7 |
| 202 #define MAC_PCU_USEC_LATENCY_USEC_LSB 0 |
| 203 #define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff |
| 204 #define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_US
EC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB) |
| 205 #define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_U
SEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK) |
| 206 |
| 207 #define PCU_MAX_CFP_DUR_ADDRESS 0x00008020 |
| 208 #define PCU_MAX_CFP_DUR_OFFSET 0x00000020 |
| 209 #define PCU_MAX_CFP_DUR_VALUE_MSB 15 |
| 210 #define PCU_MAX_CFP_DUR_VALUE_LSB 0 |
| 211 #define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff |
| 212 #define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_M
ASK) >> PCU_MAX_CFP_DUR_VALUE_LSB) |
| 213 #define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_
LSB) & PCU_MAX_CFP_DUR_VALUE_MASK) |
| 214 |
| 215 #define MAC_PCU_RX_FILTER_ADDRESS 0x00008024 |
| 216 #define MAC_PCU_RX_FILTER_OFFSET 0x00000024 |
| 217 #define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25 |
| 218 #define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24 |
| 219 #define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000 |
| 220 #define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENER
IC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) |
| 221 #define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENE
RIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) |
| 222 #define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23 |
| 223 #define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18 |
| 224 #define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000 |
| 225 #define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENER
IC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) |
| 226 #define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENE
RIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) |
| 227 #define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17 |
| 228 #define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17 |
| 229 #define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000 |
| 230 #define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_
TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) |
| 231 #define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM
_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) |
| 232 #define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16 |
| 233 #define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16 |
| 234 #define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000 |
| 235 #define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER
_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) |
| 236 #define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTE
R_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) |
| 237 #define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15 |
| 238 #define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15 |
| 239 #define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000 |
| 240 #define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST
_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) |
| 241 #define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAS
T_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) |
| 242 #define MAC_PCU_RX_FILTER_PS_POLL_MSB 14 |
| 243 #define MAC_PCU_RX_FILTER_PS_POLL_LSB 14 |
| 244 #define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000 |
| 245 #define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_PO
LL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB) |
| 246 #define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_P
OLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK) |
| 247 #define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13 |
| 248 #define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13 |
| 249 #define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000 |
| 250 #define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUM
E_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) |
| 251 #define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSU
ME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) |
| 252 #define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12 |
| 253 #define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12 |
| 254 #define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000 |
| 255 #define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_U
NCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) |
| 256 #define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_
UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) |
| 257 #define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11 |
| 258 #define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11 |
| 259 #define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800 |
| 260 #define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPR
ESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) |
| 261 #define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMP
RESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) |
| 262 #define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10 |
| 263 #define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10 |
| 264 #define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400 |
| 265 #define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPR
ESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) |
| 266 #define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMP
RESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) |
| 267 #define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9 |
| 268 #define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9 |
| 269 #define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200 |
| 270 #define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BE
ACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB) |
| 271 #define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_B
EACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) |
| 272 #define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8 |
| 273 #define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8 |
| 274 #define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100 |
| 275 #define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_
FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) |
| 276 #define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC
_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) |
| 277 #define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7 |
| 278 #define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7 |
| 279 #define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080 |
| 280 #define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE
_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB) |
| 281 #define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROB
E_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) |
| 282 #define MAC_PCU_RX_FILTER_XR_POLL_MSB 6 |
| 283 #define MAC_PCU_RX_FILTER_XR_POLL_LSB 6 |
| 284 #define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040 |
| 285 #define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_PO
LL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB) |
| 286 #define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_P
OLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK) |
| 287 #define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5 |
| 288 #define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5 |
| 289 #define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020 |
| 290 #define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMI
SCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) |
| 291 #define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROM
ISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) |
| 292 #define MAC_PCU_RX_FILTER_BEACON_MSB 4 |
| 293 #define MAC_PCU_RX_FILTER_BEACON_LSB 4 |
| 294 #define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010 |
| 295 #define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACO
N_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB) |
| 296 #define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEAC
ON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK) |
| 297 #define MAC_PCU_RX_FILTER_CONTROL_MSB 3 |
| 298 #define MAC_PCU_RX_FILTER_CONTROL_LSB 3 |
| 299 #define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008 |
| 300 #define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTR
OL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB) |
| 301 #define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONT
ROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK) |
| 302 #define MAC_PCU_RX_FILTER_BROADCAST_MSB 2 |
| 303 #define MAC_PCU_RX_FILTER_BROADCAST_LSB 2 |
| 304 #define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004 |
| 305 #define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROAD
CAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB) |
| 306 #define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROA
DCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK) |
| 307 #define MAC_PCU_RX_FILTER_MULTICAST_MSB 1 |
| 308 #define MAC_PCU_RX_FILTER_MULTICAST_LSB 1 |
| 309 #define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002 |
| 310 #define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTI
CAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB) |
| 311 #define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULT
ICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK) |
| 312 #define MAC_PCU_RX_FILTER_UNICAST_MSB 0 |
| 313 #define MAC_PCU_RX_FILTER_UNICAST_LSB 0 |
| 314 #define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001 |
| 315 #define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICA
ST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB) |
| 316 #define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNIC
AST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK) |
| 317 |
| 318 #define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028 |
| 319 #define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028 |
| 320 #define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31 |
| 321 #define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0 |
| 322 #define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff |
| 323 #define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L3
2_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) |
| 324 #define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L
32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) |
| 325 |
| 326 #define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c |
| 327 #define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c |
| 328 #define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31 |
| 329 #define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0 |
| 330 #define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff |
| 331 #define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U3
2_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) |
| 332 #define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U
32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) |
| 333 |
| 334 #define MAC_PCU_DIAG_SW_ADDRESS 0x00008030 |
| 335 #define MAC_PCU_DIAG_SW_OFFSET 0x00000030 |
| 336 #define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31 |
| 337 #define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30 |
| 338 #define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000 |
| 339 #define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_M
ODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) |
| 340 #define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_
MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) |
| 341 #define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29 |
| 342 #define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29 |
| 343 #define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000 |
| 344 #define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEA
R_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) |
| 345 #define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLE
AR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) |
| 346 #define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28 |
| 347 #define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28 |
| 348 #define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000 |
| 349 #define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEA
R_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) |
| 350 #define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLE
AR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) |
| 351 #define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27 |
| 352 #define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27 |
| 353 #define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000 |
| 354 #define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL
_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) |
| 355 #define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SE
L_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) |
| 356 #define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26 |
| 357 #define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26 |
| 358 #define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000 |
| 359 #define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURA
TE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) |
| 360 #define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATUR
ATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) |
| 361 #define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25 |
| 362 #define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25 |
| 363 #define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000 |
| 364 #define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_R
X_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) |
| 365 #define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_
RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) |
| 366 #define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24 |
| 367 #define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24 |
| 368 #define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000 |
| 369 #define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL
_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) |
| 370 #define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUA
L_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) |
| 371 #define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23 |
| 372 #define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23 |
| 373 #define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000 |
| 374 #define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PH
YERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) |
| 375 #define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_P
HYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) |
| 376 #define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22 |
| 377 #define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22 |
| 378 #define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000 |
| 379 #define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_ID
LE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) |
| 380 #define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_I
DLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) |
| 381 #define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21 |
| 382 #define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21 |
| 383 #define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000 |
| 384 #define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_
NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) |
| 385 #define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE
_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) |
| 386 #define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20 |
| 387 #define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20 |
| 388 #define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000 |
| 389 #define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEA
R_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) |
| 390 #define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLE
AR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) |
| 391 #define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19 |
| 392 #define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18 |
| 393 #define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000 |
| 394 #define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL
_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) |
| 395 #define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SE
L_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) |
| 396 #define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17 |
| 397 #define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17 |
| 398 #define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000 |
| 399 #define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_
NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) |
| 400 #define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT
_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) |
| 401 #define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8 |
| 402 #define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8 |
| 403 #define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100 |
| 404 #define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CH
AN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) |
| 405 #define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_C
HAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) |
| 406 #define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7 |
| 407 #define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7 |
| 408 #define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080 |
| 409 #define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT
_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) |
| 410 #define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUP
T_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) |
| 411 #define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6 |
| 412 #define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6 |
| 413 #define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040 |
| 414 #define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BA
CK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB) |
| 415 #define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_B
ACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) |
| 416 #define MAC_PCU_DIAG_SW_HALT_RX_MSB 5 |
| 417 #define MAC_PCU_DIAG_SW_HALT_RX_LSB 5 |
| 418 #define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020 |
| 419 #define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX
_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB) |
| 420 #define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_R
X_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK) |
| 421 #define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4 |
| 422 #define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4 |
| 423 #define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010 |
| 424 #define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECR
YPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) |
| 425 #define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DEC
RYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) |
| 426 #define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3 |
| 427 #define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3 |
| 428 #define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008 |
| 429 #define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCR
YPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) |
| 430 #define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENC
RYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) |
| 431 #define MAC_PCU_DIAG_SW_NO_CTS_MSB 2 |
| 432 #define MAC_PCU_DIAG_SW_NO_CTS_LSB 2 |
| 433 #define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004 |
| 434 #define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_
MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB) |
| 435 #define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS
_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK) |
| 436 #define MAC_PCU_DIAG_SW_NO_ACK_MSB 1 |
| 437 #define MAC_PCU_DIAG_SW_NO_ACK_LSB 1 |
| 438 #define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002 |
| 439 #define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_
MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB) |
| 440 #define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK
_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK) |
| 441 #define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0 |
| 442 #define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0 |
| 443 #define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001 |
| 444 #define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALI
D_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) |
| 445 #define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVAL
ID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) |
| 446 |
| 447 #define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034 |
| 448 #define MAC_PCU_TST_ADDAC_OFFSET 0x00000034 |
| 449 #define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20 |
| 450 #define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20 |
| 451 #define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000 |
| 452 #define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_
ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB) |
| 453 #define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST
_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) |
| 454 #define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19 |
| 455 #define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19 |
| 456 #define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000 |
| 457 #define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_
CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) |
| 458 #define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST
_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) |
| 459 #define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18 |
| 460 #define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18 |
| 461 #define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000 |
| 462 #define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_
TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB) |
| 463 #define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT
_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) |
| 464 #define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17 |
| 465 #define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17 |
| 466 #define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000 |
| 467 #define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_
POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) |
| 468 #define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG
_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) |
| 469 #define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16 |
| 470 #define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16 |
| 471 #define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000 |
| 472 #define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_
SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) |
| 473 #define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG
_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) |
| 474 #define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14 |
| 475 #define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14 |
| 476 #define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000 |
| 477 #define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER
_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB) |
| 478 #define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPE
R_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) |
| 479 #define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13 |
| 480 #define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3 |
| 481 #define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8 |
| 482 #define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_
LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) |
| 483 #define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP
_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) |
| 484 #define MAC_PCU_TST_ADDAC_LOOP_MSB 2 |
| 485 #define MAC_PCU_TST_ADDAC_LOOP_LSB 2 |
| 486 #define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004 |
| 487 #define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_
MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB) |
| 488 #define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP
_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK) |
| 489 #define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1 |
| 490 #define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1 |
| 491 #define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002 |
| 492 #define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTM
ODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB) |
| 493 #define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST
MODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) |
| 494 #define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0 |
| 495 #define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0 |
| 496 #define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001 |
| 497 #define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_
TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB) |
| 498 #define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT
_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) |
| 499 |
| 500 #define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038 |
| 501 #define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038 |
| 502 #define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28 |
| 503 #define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28 |
| 504 #define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000 |
| 505 #define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA
_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) |
| 506 #define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENN
A_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) |
| 507 #define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24 |
| 508 #define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24 |
| 509 #define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000 |
| 510 #define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX
_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) |
| 511 #define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_T
X_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) |
| 512 #define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23 |
| 513 #define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0 |
| 514 #define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff |
| 515 #define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VAL
UE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB) |
| 516 #define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VA
LUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) |
| 517 |
| 518 #define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c |
| 519 #define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c |
| 520 #define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31 |
| 521 #define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16 |
| 522 #define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000 |
| 523 #define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0
_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) |
| 524 #define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_
0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) |
| 525 #define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15 |
| 526 #define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0 |
| 527 #define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff |
| 528 #define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0
_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB) |
| 529 #define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_
0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) |
| 530 |
| 531 #define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040 |
| 532 #define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040 |
| 533 #define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31 |
| 534 #define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16 |
| 535 #define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000 |
| 536 #define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1
_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) |
| 537 #define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_
1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) |
| 538 #define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15 |
| 539 #define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0 |
| 540 #define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff |
| 541 #define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1
_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) |
| 542 #define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_
1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) |
| 543 |
| 544 #define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044 |
| 545 #define MAC_PCU_GATED_CLKS_OFFSET 0x00000044 |
| 546 #define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3 |
| 547 #define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3 |
| 548 #define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008 |
| 549 #define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATE
D_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB) |
| 550 #define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GAT
ED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) |
| 551 #define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2 |
| 552 #define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2 |
| 553 #define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004 |
| 554 #define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATE
D_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB) |
| 555 #define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GAT
ED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) |
| 556 #define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1 |
| 557 #define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1 |
| 558 #define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002 |
| 559 #define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATE
D_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB) |
| 560 #define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GAT
ED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) |
| 561 |
| 562 #define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048 |
| 563 #define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048 |
| 564 #define MAC_PCU_OBS_BUS_2_VALUE_MSB 17 |
| 565 #define MAC_PCU_OBS_BUS_2_VALUE_LSB 0 |
| 566 #define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff |
| 567 #define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE
_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB) |
| 568 #define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALU
E_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK) |
| 569 |
| 570 #define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c |
| 571 #define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c |
| 572 #define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30 |
| 573 #define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25 |
| 574 #define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000 |
| 575 #define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_ST
ATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB) |
| 576 #define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_S
TATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) |
| 577 #define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24 |
| 578 #define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20 |
| 579 #define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000 |
| 580 #define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_ST
ATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB) |
| 581 #define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_S
TATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) |
| 582 #define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17 |
| 583 #define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12 |
| 584 #define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000 |
| 585 #define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_S
TATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) |
| 586 #define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_
STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) |
| 587 #define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11 |
| 588 #define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11 |
| 589 #define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800 |
| 590 #define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CL
EAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) |
| 591 #define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_C
LEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) |
| 592 #define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10 |
| 593 #define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10 |
| 594 #define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400 |
| 595 #define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FR
AME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) |
| 596 #define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_F
RAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) |
| 597 #define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9 |
| 598 #define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9 |
| 599 #define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200 |
| 600 #define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FR
AME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) |
| 601 #define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_F
RAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) |
| 602 #define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8 |
| 603 #define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8 |
| 604 #define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100 |
| 605 #define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HO
LD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) |
| 606 #define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_H
OLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) |
| 607 #define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7 |
| 608 #define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7 |
| 609 #define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080 |
| 610 #define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_
CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) |
| 611 #define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU
_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) |
| 612 #define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6 |
| 613 #define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6 |
| 614 #define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040 |
| 615 #define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QU
IET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) |
| 616 #define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_Q
UIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) |
| 617 #define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5 |
| 618 #define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5 |
| 619 #define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020 |
| 620 #define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HC
F_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB) |
| 621 #define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_H
CF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) |
| 622 #define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4 |
| 623 #define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4 |
| 624 #define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010 |
| 625 #define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTE
R_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) |
| 626 #define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILT
ER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) |
| 627 #define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3 |
| 628 #define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3 |
| 629 #define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008 |
| 630 #define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY
_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) |
| 631 #define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_M
Y_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) |
| 632 #define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2 |
| 633 #define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2 |
| 634 #define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004 |
| 635 #define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WE
P_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB) |
| 636 #define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_W
EP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) |
| 637 #define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1 |
| 638 #define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1 |
| 639 #define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002 |
| 640 #define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_R
X_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) |
| 641 #define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_
RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) |
| 642 #define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0 |
| 643 #define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0 |
| 644 #define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001 |
| 645 #define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_D
IRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) |
| 646 #define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_
DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) |
| 647 |
| 648 #define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050 |
| 649 #define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050 |
| 650 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10 |
| 651 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8 |
| 652 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700 |
| 653 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_M
IMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_M
ASK_LSB) |
| 654 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_
MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MA
SK_MASK) |
| 655 #define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6 |
| 656 #define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4 |
| 657 #define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070 |
| 658 #define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_
MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAI
N_MASK_LSB) |
| 659 #define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM
_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN
_MASK_MASK) |
| 660 #define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2 |
| 661 #define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2 |
| 662 #define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004 |
| 663 #define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_M
IMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_
SEL_LSB) |
| 664 #define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_
MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_S
EL_MASK) |
| 665 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1 |
| 666 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1 |
| 667 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002 |
| 668 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR
_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) |
| 669 #define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PW
R_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) |
| 670 #define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0 |
| 671 #define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0 |
| 672 #define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001 |
| 673 #define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_P
WR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) |
| 674 #define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_
PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) |
| 675 |
| 676 #define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054 |
| 677 #define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054 |
| 678 #define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31 |
| 679 #define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0 |
| 680 #define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff |
| 681 #define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF
_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) |
| 682 #define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TS
F_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) |
| 683 |
| 684 #define MAC_PCU_NAV_ADDRESS 0x00008058 |
| 685 #define MAC_PCU_NAV_OFFSET 0x00000058 |
| 686 #define MAC_PCU_NAV_VALUE_MSB 25 |
| 687 #define MAC_PCU_NAV_VALUE_LSB 0 |
| 688 #define MAC_PCU_NAV_VALUE_MASK 0x03ffffff |
| 689 #define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK)
>> MAC_PCU_NAV_VALUE_LSB) |
| 690 #define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB)
& MAC_PCU_NAV_VALUE_MASK) |
| 691 |
| 692 #define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c |
| 693 #define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c |
| 694 #define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15 |
| 695 #define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0 |
| 696 #define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff |
| 697 #define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT
_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) |
| 698 #define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CN
T_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) |
| 699 |
| 700 #define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060 |
| 701 #define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060 |
| 702 #define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15 |
| 703 #define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0 |
| 704 #define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff |
| 705 #define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VA
LUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) |
| 706 #define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_V
ALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) |
| 707 |
| 708 #define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064 |
| 709 #define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064 |
| 710 #define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15 |
| 711 #define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0 |
| 712 #define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff |
| 713 #define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VA
LUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) |
| 714 #define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_V
ALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) |
| 715 |
| 716 #define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068 |
| 717 #define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068 |
| 718 #define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15 |
| 719 #define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0 |
| 720 #define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff |
| 721 #define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VA
LUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) |
| 722 #define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_V
ALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) |
| 723 |
| 724 #define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c |
| 725 #define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c |
| 726 #define MAC_PCU_BEACON_CNT_VALUE_MSB 15 |
| 727 #define MAC_PCU_BEACON_CNT_VALUE_LSB 0 |
| 728 #define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff |
| 729 #define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALU
E_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB) |
| 730 #define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VAL
UE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK) |
| 731 |
| 732 #define MAC_PCU_XRMODE_ADDRESS 0x00008070 |
| 733 #define MAC_PCU_XRMODE_OFFSET 0x00000070 |
| 734 #define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31 |
| 735 #define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20 |
| 736 #define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000 |
| 737 #define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HO
LD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB) |
| 738 #define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_H
OLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) |
| 739 #define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7 |
| 740 #define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7 |
| 741 #define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080 |
| 742 #define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR
_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) |
| 743 #define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FO
R_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) |
| 744 #define MAC_PCU_XRMODE_POLL_TYPE_MSB 5 |
| 745 #define MAC_PCU_XRMODE_POLL_TYPE_LSB 0 |
| 746 #define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f |
| 747 #define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYP
E_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB) |
| 748 #define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TY
PE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK) |
| 749 |
| 750 #define MAC_PCU_XRDEL_ADDRESS 0x00008074 |
| 751 #define MAC_PCU_XRDEL_OFFSET 0x00000074 |
| 752 #define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31 |
| 753 #define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16 |
| 754 #define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000 |
| 755 #define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DAT
A_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) |
| 756 #define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DA
TA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) |
| 757 #define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15 |
| 758 #define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0 |
| 759 #define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff |
| 760 #define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELA
Y_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB) |
| 761 #define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DEL
AY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) |
| 762 |
| 763 #define MAC_PCU_XRTO_ADDRESS 0x00008078 |
| 764 #define MAC_PCU_XRTO_OFFSET 0x00000078 |
| 765 #define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31 |
| 766 #define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16 |
| 767 #define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000 |
| 768 #define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEO
UT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB) |
| 769 #define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIME
OUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) |
| 770 #define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15 |
| 771 #define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0 |
| 772 #define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff |
| 773 #define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIME
OUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) |
| 774 #define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIM
EOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) |
| 775 |
| 776 #define MAC_PCU_XRCRP_ADDRESS 0x0000807c |
| 777 #define MAC_PCU_XRCRP_OFFSET 0x0000007c |
| 778 #define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31 |
| 779 #define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16 |
| 780 #define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000 |
| 781 #define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP
_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB) |
| 782 #define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GA
P_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) |
| 783 #define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0 |
| 784 #define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0 |
| 785 #define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001 |
| 786 #define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIR
P_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB) |
| 787 #define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHI
RP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) |
| 788 |
| 789 #define MAC_PCU_XRSTMP_ADDRESS 0x00008080 |
| 790 #define MAC_PCU_XRSTMP_OFFSET 0x00000080 |
| 791 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23 |
| 792 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16 |
| 793 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000 |
| 794 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABO
RT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) |
| 795 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_AB
ORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) |
| 796 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15 |
| 797 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8 |
| 798 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00 |
| 799 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STO
MP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) |
| 800 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_ST
OMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) |
| 801 #define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5 |
| 802 #define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5 |
| 803 #define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020 |
| 804 #define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT
_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) |
| 805 #define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABOR
T_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) |
| 806 #define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4 |
| 807 #define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4 |
| 808 #define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010 |
| 809 #define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP
_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) |
| 810 #define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOM
P_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) |
| 811 #define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3 |
| 812 #define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3 |
| 813 #define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008 |
| 814 #define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP
_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) |
| 815 #define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOM
P_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) |
| 816 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2 |
| 817 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2 |
| 818 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004 |
| 819 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP
_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) |
| 820 #define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOM
P_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) |
| 821 #define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1 |
| 822 #define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1 |
| 823 #define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002 |
| 824 #define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT
_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) |
| 825 #define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABOR
T_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) |
| 826 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0 |
| 827 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0 |
| 828 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001 |
| 829 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT
_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) |
| 830 #define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABOR
T_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) |
| 831 |
| 832 #define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084 |
| 833 #define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084 |
| 834 #define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31 |
| 835 #define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0 |
| 836 #define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff |
| 837 #define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_
VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) |
| 838 #define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32
_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) |
| 839 |
| 840 #define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088 |
| 841 #define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088 |
| 842 #define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15 |
| 843 #define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0 |
| 844 #define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff |
| 845 #define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_
VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) |
| 846 #define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16
_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) |
| 847 |
| 848 #define MAC_PCU_TPC_ADDRESS 0x0000808c |
| 849 #define MAC_PCU_TPC_OFFSET 0x0000008c |
| 850 #define MAC_PCU_TPC_CHIRP_PWR_MSB 21 |
| 851 #define MAC_PCU_TPC_CHIRP_PWR_LSB 16 |
| 852 #define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000 |
| 853 #define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_M
ASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB) |
| 854 #define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_
LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK) |
| 855 #define MAC_PCU_TPC_CTS_PWR_MSB 13 |
| 856 #define MAC_PCU_TPC_CTS_PWR_LSB 8 |
| 857 #define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00 |
| 858 #define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MAS
K) >> MAC_PCU_TPC_CTS_PWR_LSB) |
| 859 #define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LS
B) & MAC_PCU_TPC_CTS_PWR_MASK) |
| 860 #define MAC_PCU_TPC_ACK_PWR_MSB 5 |
| 861 #define MAC_PCU_TPC_ACK_PWR_LSB 0 |
| 862 #define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f |
| 863 #define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MAS
K) >> MAC_PCU_TPC_ACK_PWR_LSB) |
| 864 #define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LS
B) & MAC_PCU_TPC_ACK_PWR_MASK) |
| 865 |
| 866 #define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090 |
| 867 #define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090 |
| 868 #define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31 |
| 869 #define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0 |
| 870 #define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff |
| 871 #define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VA
LUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB) |
| 872 #define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_V
ALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) |
| 873 |
| 874 #define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094 |
| 875 #define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094 |
| 876 #define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31 |
| 877 #define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0 |
| 878 #define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff |
| 879 #define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VA
LUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB) |
| 880 #define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_V
ALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) |
| 881 |
| 882 #define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098 |
| 883 #define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098 |
| 884 #define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31 |
| 885 #define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0 |
| 886 #define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff |
| 887 #define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VA
LUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) |
| 888 #define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_V
ALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) |
| 889 |
| 890 #define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c |
| 891 #define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c |
| 892 #define MAC_PCU_CYCLE_CNT_VALUE_MSB 31 |
| 893 #define MAC_PCU_CYCLE_CNT_VALUE_LSB 0 |
| 894 #define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff |
| 895 #define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE
_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB) |
| 896 #define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALU
E_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK) |
| 897 |
| 898 #define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0 |
| 899 #define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0 |
| 900 #define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17 |
| 901 #define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17 |
| 902 #define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000 |
| 903 #define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_
ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) |
| 904 #define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1
_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) |
| 905 |
| 906 #define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4 |
| 907 #define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4 |
| 908 #define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31 |
| 909 #define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16 |
| 910 #define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000 |
| 911 #define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DU
RATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB) |
| 912 #define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_D
URATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) |
| 913 |
| 914 #define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8 |
| 915 #define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8 |
| 916 #define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8 |
| 917 #define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7 |
| 918 #define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180 |
| 919 #define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE
_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) |
| 920 #define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYT
E_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) |
| 921 #define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6 |
| 922 #define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4 |
| 923 #define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070 |
| 924 #define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_
OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) |
| 925 #define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT
_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) |
| 926 #define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3 |
| 927 #define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0 |
| 928 #define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f |
| 929 #define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_
BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) |
| 930 #define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO
_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) |
| 931 |
| 932 #define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac |
| 933 #define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac |
| 934 #define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31 |
| 935 #define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0 |
| 936 #define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff |
| 937 #define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_
VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) |
| 938 #define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK
_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) |
| 939 |
| 940 #define MAC_PCU_XRLAT_ADDRESS 0x000080b0 |
| 941 #define MAC_PCU_XRLAT_OFFSET 0x000000b0 |
| 942 #define MAC_PCU_XRLAT_VALUE_MSB 11 |
| 943 #define MAC_PCU_XRLAT_VALUE_LSB 0 |
| 944 #define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff |
| 945 #define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MAS
K) >> MAC_PCU_XRLAT_VALUE_LSB) |
| 946 #define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LS
B) & MAC_PCU_XRLAT_VALUE_MASK) |
| 947 |
| 948 #define MAC_PCU_RXBUF_ADDRESS 0x000080b4 |
| 949 #define MAC_PCU_RXBUF_OFFSET 0x000000b4 |
| 950 #define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11 |
| 951 #define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11 |
| 952 #define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800 |
| 953 #define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_EN
ABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) |
| 954 #define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_E
NABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) |
| 955 #define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10 |
| 956 #define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0 |
| 957 #define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff |
| 958 #define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRI
ORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) |
| 959 #define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PR
IORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) |
| 960 |
| 961 #define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8 |
| 962 #define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8 |
| 963 #define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16 |
| 964 #define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16 |
| 965 #define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000 |
| 966 #define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) |
| 967 #define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) |
| 968 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15 |
| 969 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14 |
| 970 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000 |
| 971 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) |
| 972 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) |
| 973 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13 |
| 974 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12 |
| 975 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000 |
| 976 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) |
| 977 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) |
| 978 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11 |
| 979 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10 |
| 980 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00 |
| 981 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) |
| 982 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) |
| 983 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9 |
| 984 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8 |
| 985 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300 |
| 986 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) |
| 987 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) |
| 988 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7 |
| 989 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6 |
| 990 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0 |
| 991 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) |
| 992 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) |
| 993 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5 |
| 994 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4 |
| 995 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030 |
| 996 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) |
| 997 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) |
| 998 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3 |
| 999 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2 |
| 1000 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c |
| 1001 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) |
| 1002 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) |
| 1003 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1 |
| 1004 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0 |
| 1005 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003 |
| 1006 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL
_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) |
| 1007 #define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTRO
L_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) |
| 1008 |
| 1009 #define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc |
| 1010 #define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc |
| 1011 #define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31 |
| 1012 #define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28 |
| 1013 #define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000 |
| 1014 #define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) |
| 1015 #define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) |
| 1016 #define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27 |
| 1017 #define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24 |
| 1018 #define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000 |
| 1019 #define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) |
| 1020 #define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) |
| 1021 #define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23 |
| 1022 #define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20 |
| 1023 #define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000 |
| 1024 #define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) |
| 1025 #define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) |
| 1026 #define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19 |
| 1027 #define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16 |
| 1028 #define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000 |
| 1029 #define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) |
| 1030 #define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) |
| 1031 #define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15 |
| 1032 #define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12 |
| 1033 #define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000 |
| 1034 #define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) |
| 1035 #define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) |
| 1036 #define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11 |
| 1037 #define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8 |
| 1038 #define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00 |
| 1039 #define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) |
| 1040 #define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) |
| 1041 #define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7 |
| 1042 #define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4 |
| 1043 #define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0 |
| 1044 #define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) |
| 1045 #define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) |
| 1046 #define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3 |
| 1047 #define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0 |
| 1048 #define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f |
| 1049 #define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_
VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) |
| 1050 #define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT
_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) |
| 1051 |
| 1052 #define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0 |
| 1053 #define MAC_PCU_MISC_MODE_OFFSET 0x000000c0 |
| 1054 #define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31 |
| 1055 #define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30 |
| 1056 #define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000 |
| 1057 #define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG
_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) |
| 1058 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBU
G_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) |
| 1059 #define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29 |
| 1060 #define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29 |
| 1061 #define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000 |
| 1062 #define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MOD
E_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) |
| 1063 #define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MO
DE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) |
| 1064 #define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28 |
| 1065 #define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28 |
| 1066 #define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000 |
| 1067 #define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_
MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEA
RCH_LSB) |
| 1068 #define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC
_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEAR
CH_MASK) |
| 1069 #define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27 |
| 1070 #define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27 |
| 1071 #define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000 |
| 1072 #define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_E
VM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB) |
| 1073 #define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_
EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) |
| 1074 #define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26 |
| 1075 #define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26 |
| 1076 #define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000 |
| 1077 #define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR
_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) |
| 1078 #define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEA
R_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) |
| 1079 #define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25 |
| 1080 #define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25 |
| 1081 #define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000 |
| 1082 #define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR
_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) |
| 1083 #define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEA
R_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) |
| 1084 #define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24 |
| 1085 #define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24 |
| 1086 #define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000 |
| 1087 #define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR
_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) |
| 1088 #define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEA
R_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) |
| 1089 #define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23 |
| 1090 #define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23 |
| 1091 #define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000 |
| 1092 #define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX
_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) |
| 1093 #define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_R
X_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) |
| 1094 #define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22 |
| 1095 #define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22 |
| 1096 #define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000 |
| 1097 #define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_
HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) |
| 1098 #define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE
_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) |
| 1099 #define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21 |
| 1100 #define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21 |
| 1101 #define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000 |
| 1102 #define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_
PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) |
| 1103 #define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT
_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) |
| 1104 #define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20 |
| 1105 #define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20 |
| 1106 #define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000 |
| 1107 #define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT
_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) |
| 1108 #define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_B
T_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) |
| 1109 #define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18 |
| 1110 #define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18 |
| 1111 #define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000 |
| 1112 #define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE
_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) |
| 1113 #define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MOD
E_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) |
| 1114 #define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14 |
| 1115 #define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14 |
| 1116 #define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000 |
| 1117 #define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_
MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) |
| 1118 #define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE
_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) |
| 1119 #define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12 |
| 1120 #define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12 |
| 1121 #define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000 |
| 1122 #define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MOD
E_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) |
| 1123 #define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MO
DE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) |
| 1124 #define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11 |
| 1125 #define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11 |
| 1126 #define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800 |
| 1127 #define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_R
X_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) |
| 1128 #define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_
RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) |
| 1129 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10 |
| 1130 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10 |
| 1131 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400 |
| 1132 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG
_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) |
| 1133 #define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBU
G_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) |
| 1134 #define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9 |
| 1135 #define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9 |
| 1136 #define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200 |
| 1137 #define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_
DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) |
| 1138 #define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE
_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) |
| 1139 #define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4 |
| 1140 #define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4 |
| 1141 #define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010 |
| 1142 #define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_S
IFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) |
| 1143 #define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_
SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) |
| 1144 #define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3 |
| 1145 #define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3 |
| 1146 #define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008 |
| 1147 #define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_AD
D_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) |
| 1148 #define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_A
DD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) |
| 1149 #define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2 |
| 1150 #define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2 |
| 1151 #define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004 |
| 1152 #define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MO
DE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LS
B) |
| 1153 #define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_M
ODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MAS
K) |
| 1154 #define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1 |
| 1155 #define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1 |
| 1156 #define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002 |
| 1157 #define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG
_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) |
| 1158 #define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBU
G_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) |
| 1159 #define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0 |
| 1160 #define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0 |
| 1161 #define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001 |
| 1162 #define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSS
ID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) |
| 1163 #define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BS
SID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) |
| 1164 |
| 1165 #define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4 |
| 1166 #define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4 |
| 1167 #define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23 |
| 1168 #define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0 |
| 1169 #define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff |
| 1170 #define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT
_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) |
| 1171 #define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CN
T_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) |
| 1172 |
| 1173 #define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8 |
| 1174 #define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8 |
| 1175 #define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23 |
| 1176 #define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0 |
| 1177 #define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff |
| 1178 #define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_
VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) |
| 1179 #define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT
_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) |
| 1180 |
| 1181 #define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc |
| 1182 #define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc |
| 1183 #define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23 |
| 1184 #define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0 |
| 1185 #define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff |
| 1186 #define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_V
ALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) |
| 1187 #define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_
VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) |
| 1188 |
| 1189 #define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0 |
| 1190 #define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0 |
| 1191 #define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31 |
| 1192 #define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0 |
| 1193 #define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff |
| 1194 #define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_M
ASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) |
| 1195 #define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_
MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) |
| 1196 |
| 1197 #define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4 |
| 1198 #define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4 |
| 1199 #define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23 |
| 1200 #define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0 |
| 1201 #define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff |
| 1202 #define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_V
ALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) |
| 1203 #define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_
VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) |
| 1204 |
| 1205 #define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8 |
| 1206 #define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8 |
| 1207 #define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31 |
| 1208 #define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0 |
| 1209 #define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff |
| 1210 #define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_M
ASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) |
| 1211 #define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_
MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) |
| 1212 |
| 1213 #define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc |
| 1214 #define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc |
| 1215 #define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15 |
| 1216 #define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0 |
| 1217 #define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff |
| 1218 #define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_V
ALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB) |
| 1219 #define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_
VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) |
| 1220 |
| 1221 #define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0 |
| 1222 #define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0 |
| 1223 #define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31 |
| 1224 #define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0 |
| 1225 #define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff |
| 1226 #define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_
MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) |
| 1227 #define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS
_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) |
| 1228 |
| 1229 #define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4 |
| 1230 #define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4 |
| 1231 #define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23 |
| 1232 #define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0 |
| 1233 #define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff |
| 1234 #define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_V
ALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) |
| 1235 #define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_
VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) |
| 1236 |
| 1237 #define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8 |
| 1238 #define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8 |
| 1239 #define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31 |
| 1240 #define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0 |
| 1241 #define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff |
| 1242 #define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_M
ASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) |
| 1243 #define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_
MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) |
| 1244 |
| 1245 #define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec |
| 1246 #define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec |
| 1247 #define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31 |
| 1248 #define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24 |
| 1249 #define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000 |
| 1250 #define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) |
| 1251 #define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) |
| 1252 #define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23 |
| 1253 #define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18 |
| 1254 #define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000 |
| 1255 #define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MO
DE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) |
| 1256 #define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_M
ODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) |
| 1257 #define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17 |
| 1258 #define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17 |
| 1259 #define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000 |
| 1260 #define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOT
H_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) |
| 1261 #define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOO
TH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) |
| 1262 #define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16 |
| 1263 #define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13 |
| 1264 #define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000 |
| 1265 #define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_
QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) |
| 1266 #define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE
_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) |
| 1267 #define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12 |
| 1268 #define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12 |
| 1269 #define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000 |
| 1270 #define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_
QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) |
| 1271 #define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE
_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) |
| 1272 #define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11 |
| 1273 #define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10 |
| 1274 #define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00 |
| 1275 #define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_
MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB) |
| 1276 #define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE
_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) |
| 1277 #define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9 |
| 1278 #define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9 |
| 1279 #define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200 |
| 1280 #define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) |
| 1281 #define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) |
| 1282 #define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8 |
| 1283 #define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8 |
| 1284 #define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100 |
| 1285 #define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) |
| 1286 #define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) |
| 1287 #define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7 |
| 1288 #define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0 |
| 1289 #define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff |
| 1290 #define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE
_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) |
| 1291 #define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MOD
E_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) |
| 1292 |
| 1293 #define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0 |
| 1294 #define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0 |
| 1295 #define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31 |
| 1296 #define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16 |
| 1297 #define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000 |
| 1298 #define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEI
GHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) |
| 1299 #define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WE
IGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) |
| 1300 #define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15 |
| 1301 #define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0 |
| 1302 #define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff |
| 1303 #define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEI
GHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) |
| 1304 #define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WE
IGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) |
| 1305 |
| 1306 #define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4 |
| 1307 #define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4 |
| 1308 #define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31 |
| 1309 #define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31 |
| 1310 #define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000 |
| 1311 #define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BL
UETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT
_COLL_ENABLE_LSB) |
| 1312 #define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_B
LUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_
COLL_ENABLE_MASK) |
| 1313 #define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30 |
| 1314 #define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30 |
| 1315 #define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000 |
| 1316 #define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOT
H_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) |
| 1317 #define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOO
TH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) |
| 1318 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29 |
| 1319 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28 |
| 1320 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000 |
| 1321 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUE
TOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORIT
Y_CTRL_LSB) |
| 1322 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLU
ETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY
_CTRL_MASK) |
| 1323 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27 |
| 1324 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26 |
| 1325 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000 |
| 1326 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETO
OTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL
_LSB) |
| 1327 #define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUET
OOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_
MASK) |
| 1328 #define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25 |
| 1329 #define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25 |
| 1330 #define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000 |
| 1331 #define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOO
TH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LS
B) |
| 1332 #define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETO
OTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MAS
K) |
| 1333 #define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24 |
| 1334 #define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24 |
| 1335 #define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000 |
| 1336 #define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOT
H_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) |
| 1337 #define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOO
TH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) |
| 1338 #define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23 |
| 1339 #define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22 |
| 1340 #define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000 |
| 1341 #define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) |
| 1342 #define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) |
| 1343 #define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21 |
| 1344 #define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21 |
| 1345 #define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000 |
| 1346 #define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MO
DE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) |
| 1347 #define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_M
ODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) |
| 1348 #define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20 |
| 1349 #define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20 |
| 1350 #define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000 |
| 1351 #define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) |
| 1352 #define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) |
| 1353 #define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19 |
| 1354 #define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19 |
| 1355 #define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000 |
| 1356 #define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_B
LUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_
BT_AFTER_WAKEUP_LSB) |
| 1357 #define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_
BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_B
T_AFTER_WAKEUP_MASK) |
| 1358 #define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17 |
| 1359 #define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17 |
| 1360 #define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000 |
| 1361 #define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLU
ETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_
BT_ACCESS_LSB) |
| 1362 #define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BL
UETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_B
T_ACCESS_MASK) |
| 1363 #define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16 |
| 1364 #define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16 |
| 1365 #define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000 |
| 1366 #define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_M
ODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) |
| 1367 #define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_
MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) |
| 1368 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15 |
| 1369 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8 |
| 1370 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00 |
| 1371 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MO
DE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) |
| 1372 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_M
ODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) |
| 1373 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7 |
| 1374 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0 |
| 1375 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff |
| 1376 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH
_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) |
| 1377 #define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOT
H_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) |
| 1378 |
| 1379 #define MAC_PCU_TXSIFS_ADDRESS 0x000080f8 |
| 1380 #define MAC_PCU_TXSIFS_OFFSET 0x000000f8 |
| 1381 #define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14 |
| 1382 #define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12 |
| 1383 #define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000 |
| 1384 #define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIF
T_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB) |
| 1385 #define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHI
FT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) |
| 1386 #define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11 |
| 1387 #define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8 |
| 1388 #define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00 |
| 1389 #define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATEN
CY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB) |
| 1390 #define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATE
NCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) |
| 1391 #define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7 |
| 1392 #define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0 |
| 1393 #define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff |
| 1394 #define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIM
E_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB) |
| 1395 #define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TI
ME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) |
| 1396 |
| 1397 #define MAC_PCU_TXOP_X_ADDRESS 0x000080fc |
| 1398 #define MAC_PCU_TXOP_X_OFFSET 0x000000fc |
| 1399 #define MAC_PCU_TXOP_X_VALUE_MSB 7 |
| 1400 #define MAC_PCU_TXOP_X_VALUE_LSB 0 |
| 1401 #define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff |
| 1402 #define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MA
SK) >> MAC_PCU_TXOP_X_VALUE_LSB) |
| 1403 #define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_L
SB) & MAC_PCU_TXOP_X_VALUE_MASK) |
| 1404 |
| 1405 #define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100 |
| 1406 #define MAC_PCU_TXOP_0_3_OFFSET 0x00000100 |
| 1407 #define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31 |
| 1408 #define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24 |
| 1409 #define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000 |
| 1410 #define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_
3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB) |
| 1411 #define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE
_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) |
| 1412 #define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23 |
| 1413 #define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16 |
| 1414 #define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000 |
| 1415 #define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_
2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB) |
| 1416 #define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE
_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) |
| 1417 #define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15 |
| 1418 #define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8 |
| 1419 #define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00 |
| 1420 #define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_
1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB) |
| 1421 #define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE
_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) |
| 1422 #define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7 |
| 1423 #define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0 |
| 1424 #define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff |
| 1425 #define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_
0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB) |
| 1426 #define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE
_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) |
| 1427 |
| 1428 #define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104 |
| 1429 #define MAC_PCU_TXOP_4_7_OFFSET 0x00000104 |
| 1430 #define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31 |
| 1431 #define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24 |
| 1432 #define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000 |
| 1433 #define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_
7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB) |
| 1434 #define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE
_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) |
| 1435 #define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23 |
| 1436 #define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16 |
| 1437 #define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000 |
| 1438 #define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_
6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB) |
| 1439 #define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE
_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) |
| 1440 #define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15 |
| 1441 #define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8 |
| 1442 #define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00 |
| 1443 #define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_
5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB) |
| 1444 #define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE
_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) |
| 1445 #define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7 |
| 1446 #define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0 |
| 1447 #define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff |
| 1448 #define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_
4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB) |
| 1449 #define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE
_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) |
| 1450 |
| 1451 #define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108 |
| 1452 #define MAC_PCU_TXOP_8_11_OFFSET 0x00000108 |
| 1453 #define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31 |
| 1454 #define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24 |
| 1455 #define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000 |
| 1456 #define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE
_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB) |
| 1457 #define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALU
E_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) |
| 1458 #define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23 |
| 1459 #define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16 |
| 1460 #define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000 |
| 1461 #define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE
_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB) |
| 1462 #define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALU
E_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) |
| 1463 #define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15 |
| 1464 #define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8 |
| 1465 #define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00 |
| 1466 #define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE
_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB) |
| 1467 #define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALU
E_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) |
| 1468 #define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7 |
| 1469 #define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0 |
| 1470 #define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff |
| 1471 #define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE
_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB) |
| 1472 #define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALU
E_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) |
| 1473 |
| 1474 #define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c |
| 1475 #define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c |
| 1476 #define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31 |
| 1477 #define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24 |
| 1478 #define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000 |
| 1479 #define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALU
E_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB) |
| 1480 #define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VAL
UE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) |
| 1481 #define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23 |
| 1482 #define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16 |
| 1483 #define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000 |
| 1484 #define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALU
E_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB) |
| 1485 #define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VAL
UE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) |
| 1486 #define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15 |
| 1487 #define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8 |
| 1488 #define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00 |
| 1489 #define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALU
E_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB) |
| 1490 #define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VAL
UE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) |
| 1491 #define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7 |
| 1492 #define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0 |
| 1493 #define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff |
| 1494 #define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALU
E_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB) |
| 1495 #define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VAL
UE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) |
| 1496 |
| 1497 #define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110 |
| 1498 #define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110 |
| 1499 #define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31 |
| 1500 #define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18 |
| 1501 #define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000 |
| 1502 #define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) |
| 1503 #define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) |
| 1504 #define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17 |
| 1505 #define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8 |
| 1506 #define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00 |
| 1507 #define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) |
| 1508 #define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) |
| 1509 #define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7 |
| 1510 #define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4 |
| 1511 #define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0 |
| 1512 #define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) |
| 1513 #define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) |
| 1514 #define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3 |
| 1515 #define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3 |
| 1516 #define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008 |
| 1517 #define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) |
| 1518 #define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) |
| 1519 #define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2 |
| 1520 #define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2 |
| 1521 #define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004 |
| 1522 #define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB) |
| 1523 #define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) |
| 1524 #define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1 |
| 1525 #define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1 |
| 1526 #define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002 |
| 1527 #define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) |
| 1528 #define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) |
| 1529 #define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0 |
| 1530 #define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0 |
| 1531 #define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001 |
| 1532 #define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) |
| 1533 #define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) |
| 1534 |
| 1535 #define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114 |
| 1536 #define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114 |
| 1537 #define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31 |
| 1538 #define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0 |
| 1539 #define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff |
| 1540 #define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) |
| 1541 #define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) |
| 1542 |
| 1543 #define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118 |
| 1544 #define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118 |
| 1545 #define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15 |
| 1546 #define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0 |
| 1547 #define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff |
| 1548 #define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_
16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) |
| 1549 #define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER
_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) |
| 1550 |
| 1551 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c |
| 1552 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c |
| 1553 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23 |
| 1554 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16 |
| 1555 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000 |
| 1556 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_M
ASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) |
| 1557 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_
MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) |
| 1558 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15 |
| 1559 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8 |
| 1560 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00 |
| 1561 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_M
ASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) |
| 1562 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_
MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) |
| 1563 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7 |
| 1564 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0 |
| 1565 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff |
| 1566 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_M
ASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) |
| 1567 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_
MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) |
| 1568 |
| 1569 #define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120 |
| 1570 #define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120 |
| 1571 #define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7 |
| 1572 #define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7 |
| 1573 #define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080 |
| 1574 #define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA
_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) |
| 1575 #define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_B
A_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) |
| 1576 #define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6 |
| 1577 #define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6 |
| 1578 #define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040 |
| 1579 #define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH
_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LS
B) |
| 1580 #define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUT
H_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MAS
K) |
| 1581 #define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5 |
| 1582 #define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5 |
| 1583 #define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020 |
| 1584 #define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX
_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) |
| 1585 #define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_T
X_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) |
| 1586 #define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4 |
| 1587 #define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4 |
| 1588 #define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010 |
| 1589 #define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CL
K_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) |
| 1590 #define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_C
LK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) |
| 1591 #define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3 |
| 1592 #define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3 |
| 1593 #define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008 |
| 1594 #define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MO
DE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) |
| 1595 #define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_M
ODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) |
| 1596 #define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2 |
| 1597 #define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2 |
| 1598 #define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004 |
| 1599 #define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MO
DE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) |
| 1600 #define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_M
ODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) |
| 1601 #define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1 |
| 1602 #define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1 |
| 1603 #define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002 |
| 1604 #define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_
KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) |
| 1605 #define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE
_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) |
| 1606 #define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0 |
| 1607 #define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0 |
| 1608 #define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001 |
| 1609 #define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_M
ODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) |
| 1610 #define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_
MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) |
| 1611 |
| 1612 #define MAC_PCU_20_40_MODE_ADDRESS 0x00008124 |
| 1613 #define MAC_PCU_20_40_MODE_OFFSET 0x00000124 |
| 1614 #define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15 |
| 1615 #define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4 |
| 1616 #define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0 |
| 1617 #define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS
_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) |
| 1618 #define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIF
S_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) |
| 1619 #define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3 |
| 1620 #define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3 |
| 1621 #define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008 |
| 1622 #define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_P
CU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMP
ED_FORCES_RX_CLEAR_CTL_IDLE_LSB) |
| 1623 #define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_
PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPE
D_FORCES_RX_CLEAR_CTL_IDLE_MASK) |
| 1624 #define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2 |
| 1625 #define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2 |
| 1626 #define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004 |
| 1627 #define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE
_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) |
| 1628 #define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MOD
E_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) |
| 1629 #define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1 |
| 1630 #define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1 |
| 1631 #define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002 |
| 1632 #define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT
_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) |
| 1633 #define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EX
T_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) |
| 1634 #define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0 |
| 1635 #define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0 |
| 1636 #define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001 |
| 1637 #define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOI
NED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) |
| 1638 #define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JO
INED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) |
| 1639 |
| 1640 #define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128 |
| 1641 #define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128 |
| 1642 #define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31 |
| 1643 #define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0 |
| 1644 #define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff |
| 1645 #define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_C
NT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) |
| 1646 #define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_
CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) |
| 1647 |
| 1648 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c |
| 1649 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c |
| 1650 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2 |
| 1651 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0 |
| 1652 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007 |
| 1653 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTE
NNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) |
| 1654 #define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANT
ENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) |
| 1655 |
| 1656 #define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130 |
| 1657 #define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130 |
| 1658 #define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12 |
| 1659 #define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12 |
| 1660 #define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000 |
| 1661 #define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_
BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_
BA_BITMAP_QOS_NULL_LSB) |
| 1662 #define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU
_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_B
A_BITMAP_QOS_NULL_MASK) |
| 1663 #define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11 |
| 1664 #define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11 |
| 1665 #define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800 |
| 1666 #define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BA
R_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VA
LID_LSB) |
| 1667 #define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_B
AR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VAL
ID_MASK) |
| 1668 #define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10 |
| 1669 #define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10 |
| 1670 #define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400 |
| 1671 #define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONT
ROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) |
| 1672 #define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CON
TROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) |
| 1673 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9 |
| 1674 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9 |
| 1675 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200 |
| 1676 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CO
NTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) |
| 1677 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_C
ONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) |
| 1678 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8 |
| 1679 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8 |
| 1680 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100 |
| 1681 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CO
NTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) |
| 1682 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_C
ONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) |
| 1683 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7 |
| 1684 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4 |
| 1685 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0 |
| 1686 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_C
ONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) |
| 1687 #define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_
CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) |
| 1688 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3 |
| 1689 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0 |
| 1690 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f |
| 1691 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_C
ONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) |
| 1692 #define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_
CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) |
| 1693 |
| 1694 #define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134 |
| 1695 #define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134 |
| 1696 #define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12 |
| 1697 #define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8 |
| 1698 #define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00 |
| 1699 #define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_
SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) |
| 1700 #define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP
_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) |
| 1701 #define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7 |
| 1702 #define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0 |
| 1703 #define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff |
| 1704 #define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_
PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LS
B) |
| 1705 #define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY
_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MAS
K) |
| 1706 |
| 1707 #define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138 |
| 1708 #define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138 |
| 1709 #define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23 |
| 1710 #define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16 |
| 1711 #define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000 |
| 1712 #define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_
MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) |
| 1713 #define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR
_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) |
| 1714 #define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7 |
| 1715 #define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0 |
| 1716 #define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff |
| 1717 #define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_
MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) |
| 1718 #define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR
_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) |
| 1719 |
| 1720 #define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c |
| 1721 #define MAC_PCU_TX_TIMER_OFFSET 0x0000013c |
| 1722 #define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25 |
| 1723 #define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25 |
| 1724 #define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000 |
| 1725 #define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIE
T_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) |
| 1726 #define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUI
ET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) |
| 1727 #define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24 |
| 1728 #define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20 |
| 1729 #define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000 |
| 1730 #define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_
TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) |
| 1731 #define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET
_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) |
| 1732 #define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19 |
| 1733 #define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16 |
| 1734 #define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000 |
| 1735 #define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_T
IMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) |
| 1736 #define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_
TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) |
| 1737 #define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15 |
| 1738 #define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15 |
| 1739 #define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000 |
| 1740 #define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIM
ER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) |
| 1741 #define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TI
MER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) |
| 1742 #define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14 |
| 1743 #define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0 |
| 1744 #define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff |
| 1745 #define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIM
ER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB) |
| 1746 #define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TI
MER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) |
| 1747 |
| 1748 #define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140 |
| 1749 #define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140 |
| 1750 #define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16 |
| 1751 #define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16 |
| 1752 #define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000 |
| 1753 #define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL
_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) |
| 1754 #define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTR
L_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) |
| 1755 #define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11 |
| 1756 #define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0 |
| 1757 #define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff |
| 1758 #define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USAB
LE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) |
| 1759 #define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USA
BLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) |
| 1760 |
| 1761 #define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144 |
| 1762 #define MAC_PCU_MISC_MODE2_OFFSET 0x00000144 |
| 1763 #define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31 |
| 1764 #define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28 |
| 1765 #define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000 |
| 1766 #define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESE
RVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB) |
| 1767 #define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RES
ERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) |
| 1768 #define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27 |
| 1769 #define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27 |
| 1770 #define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000 |
| 1771 #define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_R
CV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) |
| 1772 #define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_
RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) |
| 1773 #define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26 |
| 1774 #define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26 |
| 1775 #define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000 |
| 1776 #define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_B
EACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) |
| 1777 #define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_
BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) |
| 1778 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25 |
| 1779 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25 |
| 1780 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000 |
| 1781 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_P
M_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) |
| 1782 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_
PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) |
| 1783 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24 |
| 1784 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24 |
| 1785 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000 |
| 1786 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM
_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) |
| 1787 #define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_P
M_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) |
| 1788 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23 |
| 1789 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23 |
| 1790 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000 |
| 1791 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2
_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) |
| 1792 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE
2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) |
| 1793 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22 |
| 1794 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22 |
| 1795 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000 |
| 1796 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2
_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) |
| 1797 #define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE
2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) |
| 1798 #define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21 |
| 1799 #define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21 |
| 1800 #define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000 |
| 1801 #define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLE
AR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) |
| 1802 #define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CL
EAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) |
| 1803 #define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20 |
| 1804 #define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20 |
| 1805 #define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000 |
| 1806 #define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_
28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB) |
| 1807 #define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG
_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) |
| 1808 #define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19 |
| 1809 #define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19 |
| 1810 #define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000 |
| 1811 #define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_D
UR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) |
| 1812 #define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_
DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) |
| 1813 #define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18 |
| 1814 #define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18 |
| 1815 #define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000 |
| 1816 #define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_
MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) |
| 1817 #define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC
_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) |
| 1818 #define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17 |
| 1819 #define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17 |
| 1820 #define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000 |
| 1821 #define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_
WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB) |
| 1822 #define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG
_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) |
| 1823 #define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16 |
| 1824 #define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16 |
| 1825 #define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000 |
| 1826 #define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PC
U_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_
LOAD_NAV_BEACON_DURATION_LSB) |
| 1827 #define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_P
CU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_L
OAD_NAV_BEACON_DURATION_MASK) |
| 1828 #define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15 |
| 1829 #define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8 |
| 1830 #define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00 |
| 1831 #define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT
_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) |
| 1832 #define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGM
T_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) |
| 1833 #define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7 |
| 1834 #define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7 |
| 1835 #define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080 |
| 1836 #define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_
IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) |
| 1837 #define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP
_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) |
| 1838 #define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6 |
| 1839 #define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6 |
| 1840 #define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040 |
| 1841 #define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_
MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENA
BLE_LSB) |
| 1842 #define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC
_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENAB
LE_MASK) |
| 1843 #define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5 |
| 1844 #define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5 |
| 1845 #define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020 |
| 1846 #define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESE
RVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB) |
| 1847 #define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RES
ERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) |
| 1848 #define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4 |
| 1849 #define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4 |
| 1850 #define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010 |
| 1851 #define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE
2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) |
| 1852 #define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MOD
E2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) |
| 1853 #define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3 |
| 1854 #define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3 |
| 1855 #define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008 |
| 1856 #define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESE
RVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB) |
| 1857 #define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RES
ERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) |
| 1858 #define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2 |
| 1859 #define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2 |
| 1860 #define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004 |
| 1861 #define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MIS
C_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON
_DATA_PKT_LSB) |
| 1862 #define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MI
SC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_
DATA_PKT_MASK) |
| 1863 #define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1 |
| 1864 #define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1 |
| 1865 #define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002 |
| 1866 #define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_
MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) |
| 1867 #define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2
_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) |
| 1868 #define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0 |
| 1869 #define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0 |
| 1870 #define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001 |
| 1871 #define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE
2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) |
| 1872 #define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MOD
E2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) |
| 1873 |
| 1874 #define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148 |
| 1875 #define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148 |
| 1876 #define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31 |
| 1877 #define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16 |
| 1878 #define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000 |
| 1879 #define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MA
SK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) |
| 1880 #define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_M
ASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) |
| 1881 |
| 1882 #define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c |
| 1883 #define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c |
| 1884 #define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31 |
| 1885 #define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0 |
| 1886 #define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff |
| 1887 #define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_ST
AMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) |
| 1888 #define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_S
TAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) |
| 1889 |
| 1890 #define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150 |
| 1891 #define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150 |
| 1892 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7 |
| 1893 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4 |
| 1894 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0 |
| 1895 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP
_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LS
B) |
| 1896 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CF
P_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MAS
K) |
| 1897 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3 |
| 1898 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0 |
| 1899 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f |
| 1900 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_D
UR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) |
| 1901 #define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_
DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) |
| 1902 |
| 1903 #define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154 |
| 1904 #define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154 |
| 1905 #define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15 |
| 1906 #define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0 |
| 1907 #define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff |
| 1908 #define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VAL
UE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB) |
| 1909 #define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VA
LUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) |
| 1910 |
| 1911 #define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158 |
| 1912 #define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158 |
| 1913 #define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31 |
| 1914 #define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16 |
| 1915 #define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000 |
| 1916 #define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETO
OTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD
_LSB) |
| 1917 #define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUET
OOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_
MASK) |
| 1918 |
| 1919 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c |
| 1920 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c |
| 1921 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31 |
| 1922 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0 |
| 1923 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff |
| 1924 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_T
SF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) |
| 1925 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_
TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) |
| 1926 |
| 1927 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160 |
| 1928 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160 |
| 1929 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31 |
| 1930 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0 |
| 1931 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff |
| 1932 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH
_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) |
| 1933 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOT
H_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) |
| 1934 |
| 1935 #define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164 |
| 1936 #define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164 |
| 1937 #define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31 |
| 1938 #define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28 |
| 1939 #define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000 |
| 1940 #define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_
BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRI
ORITY_EXTEND_THRES_LSB) |
| 1941 #define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU
_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIO
RITY_EXTEND_THRES_MASK) |
| 1942 #define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27 |
| 1943 #define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27 |
| 1944 #define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000 |
| 1945 #define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MOD
E3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) |
| 1946 #define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MO
DE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) |
| 1947 #define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26 |
| 1948 #define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25 |
| 1949 #define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000 |
| 1950 #define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3
_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) |
| 1951 #define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE
3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) |
| 1952 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24 |
| 1953 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24 |
| 1954 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000 |
| 1955 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLU
ETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGG
LE_WLA_EN_LSB) |
| 1956 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BL
UETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGL
E_WLA_EN_MASK) |
| 1957 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23 |
| 1958 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23 |
| 1959 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000 |
| 1960 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) |
| 1961 #define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) |
| 1962 #define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22 |
| 1963 #define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22 |
| 1964 #define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000 |
| 1965 #define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH
_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) |
| 1966 #define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOT
H_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) |
| 1967 #define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21 |
| 1968 #define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21 |
| 1969 #define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000 |
| 1970 #define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLU
ETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_
OFFSET_EN_LSB) |
| 1971 #define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BL
UETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_O
FFSET_EN_MASK) |
| 1972 #define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20 |
| 1973 #define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20 |
| 1974 #define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000 |
| 1975 #define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3
_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) |
| 1976 #define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE
3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) |
| 1977 #define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19 |
| 1978 #define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16 |
| 1979 #define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000 |
| 1980 #define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_B
LUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CO
NCURRENT_ACCESS_LSB) |
| 1981 #define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_
BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CON
CURRENT_ACCESS_MASK) |
| 1982 #define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15 |
| 1983 #define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8 |
| 1984 #define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00 |
| 1985 #define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE
3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) |
| 1986 #define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MOD
E3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) |
| 1987 #define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7 |
| 1988 #define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0 |
| 1989 #define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff |
| 1990 #define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_
MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) |
| 1991 #define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH
_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) |
| 1992 |
| 1993 #define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168 |
| 1994 #define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168 |
| 1995 #define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31 |
| 1996 #define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16 |
| 1997 #define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000 |
| 1998 #define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETO
OTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND
_LSB) |
| 1999 #define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUET
OOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_
MASK) |
| 2000 #define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15 |
| 2001 #define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0 |
| 2002 #define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff |
| 2003 #define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOT
H_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) |
| 2004 #define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOO
TH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) |
| 2005 |
| 2006 #define MAC_PCU_BT_BT_ADDRESS 0x00008200 |
| 2007 #define MAC_PCU_BT_BT_OFFSET 0x00000200 |
| 2008 #define MAC_PCU_BT_BT_WEIGHT_MSB 31 |
| 2009 #define MAC_PCU_BT_BT_WEIGHT_LSB 0 |
| 2010 #define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff |
| 2011 #define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MA
SK) >> MAC_PCU_BT_BT_WEIGHT_LSB) |
| 2012 #define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_L
SB) & MAC_PCU_BT_BT_WEIGHT_MASK) |
| 2013 |
| 2014 #define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300 |
| 2015 #define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300 |
| 2016 #define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15 |
| 2017 #define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12 |
| 2018 #define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000 |
| 2019 #define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXL
P_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) |
| 2020 #define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RX
LP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) |
| 2021 #define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11 |
| 2022 #define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8 |
| 2023 #define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00 |
| 2024 #define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXH
P_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) |
| 2025 #define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RX
HP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) |
| 2026 #define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7 |
| 2027 #define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4 |
| 2028 #define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0 |
| 2029 #define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXL
P_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) |
| 2030 #define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TX
LP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) |
| 2031 #define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3 |
| 2032 #define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0 |
| 2033 #define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f |
| 2034 #define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXH
P_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) |
| 2035 #define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TX
HP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) |
| 2036 |
| 2037 #define MAC_PCU_BT_WL_1_ADDRESS 0x00008304 |
| 2038 #define MAC_PCU_BT_WL_1_OFFSET 0x00000304 |
| 2039 #define MAC_PCU_BT_WL_1_WEIGHT_MSB 31 |
| 2040 #define MAC_PCU_BT_WL_1_WEIGHT_LSB 0 |
| 2041 #define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff |
| 2042 #define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_
MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB) |
| 2043 #define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT
_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK) |
| 2044 |
| 2045 #define MAC_PCU_BT_WL_2_ADDRESS 0x00008308 |
| 2046 #define MAC_PCU_BT_WL_2_OFFSET 0x00000308 |
| 2047 #define MAC_PCU_BT_WL_2_WEIGHT_MSB 31 |
| 2048 #define MAC_PCU_BT_WL_2_WEIGHT_LSB 0 |
| 2049 #define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff |
| 2050 #define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_
MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB) |
| 2051 #define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT
_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK) |
| 2052 |
| 2053 #define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c |
| 2054 #define MAC_PCU_BT_WL_3_OFFSET 0x0000030c |
| 2055 #define MAC_PCU_BT_WL_3_WEIGHT_MSB 31 |
| 2056 #define MAC_PCU_BT_WL_3_WEIGHT_LSB 0 |
| 2057 #define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff |
| 2058 #define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_
MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB) |
| 2059 #define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT
_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK) |
| 2060 |
| 2061 #define MAC_PCU_BT_WL_4_ADDRESS 0x00008310 |
| 2062 #define MAC_PCU_BT_WL_4_OFFSET 0x00000310 |
| 2063 #define MAC_PCU_BT_WL_4_WEIGHT_MSB 31 |
| 2064 #define MAC_PCU_BT_WL_4_WEIGHT_LSB 0 |
| 2065 #define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff |
| 2066 #define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_
MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB) |
| 2067 #define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT
_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK) |
| 2068 |
| 2069 #define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314 |
| 2070 #define MAC_PCU_COEX_EPTA_OFFSET 0x00000314 |
| 2071 #define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12 |
| 2072 #define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6 |
| 2073 #define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0 |
| 2074 #define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_ID
X_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB) |
| 2075 #define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_I
DX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) |
| 2076 #define MAC_PCU_COEX_EPTA_LINKID_MSB 5 |
| 2077 #define MAC_PCU_COEX_EPTA_LINKID_LSB 0 |
| 2078 #define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f |
| 2079 #define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKI
D_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB) |
| 2080 #define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINK
ID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK) |
| 2081 |
| 2082 #define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318 |
| 2083 #define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318 |
| 2084 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31 |
| 2085 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24 |
| 2086 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000 |
| 2087 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) |
| 2088 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) |
| 2089 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23 |
| 2090 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16 |
| 2091 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000 |
| 2092 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) |
| 2093 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) |
| 2094 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15 |
| 2095 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8 |
| 2096 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00 |
| 2097 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) |
| 2098 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) |
| 2099 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7 |
| 2100 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0 |
| 2101 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff |
| 2102 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) |
| 2103 #define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) |
| 2104 |
| 2105 #define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c |
| 2106 #define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c |
| 2107 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31 |
| 2108 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24 |
| 2109 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000 |
| 2110 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) |
| 2111 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) |
| 2112 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23 |
| 2113 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16 |
| 2114 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000 |
| 2115 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) |
| 2116 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) |
| 2117 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15 |
| 2118 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8 |
| 2119 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00 |
| 2120 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) |
| 2121 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) |
| 2122 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7 |
| 2123 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0 |
| 2124 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff |
| 2125 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) |
| 2126 #define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) |
| 2127 |
| 2128 #define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320 |
| 2129 #define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320 |
| 2130 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31 |
| 2131 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24 |
| 2132 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000 |
| 2133 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) |
| 2134 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) |
| 2135 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23 |
| 2136 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16 |
| 2137 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000 |
| 2138 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) |
| 2139 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) |
| 2140 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15 |
| 2141 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8 |
| 2142 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00 |
| 2143 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) |
| 2144 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) |
| 2145 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7 |
| 2146 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0 |
| 2147 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff |
| 2148 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) |
| 2149 #define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) |
| 2150 |
| 2151 #define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324 |
| 2152 #define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324 |
| 2153 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31 |
| 2154 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24 |
| 2155 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000 |
| 2156 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) |
| 2157 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) |
| 2158 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23 |
| 2159 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16 |
| 2160 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000 |
| 2161 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) |
| 2162 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) |
| 2163 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15 |
| 2164 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8 |
| 2165 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00 |
| 2166 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) |
| 2167 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) |
| 2168 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7 |
| 2169 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0 |
| 2170 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff |
| 2171 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN
4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) |
| 2172 #define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAI
N4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) |
| 2173 |
| 2174 #define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328 |
| 2175 #define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328 |
| 2176 #define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29 |
| 2177 #define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0 |
| 2178 #define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff |
| 2179 #define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0
_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) |
| 2180 #define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET
0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) |
| 2181 |
| 2182 #define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c |
| 2183 #define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c |
| 2184 #define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29 |
| 2185 #define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0 |
| 2186 #define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff |
| 2187 #define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1
_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) |
| 2188 #define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET
1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) |
| 2189 |
| 2190 #define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330 |
| 2191 #define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330 |
| 2192 #define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29 |
| 2193 #define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0 |
| 2194 #define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff |
| 2195 #define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2
_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) |
| 2196 #define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET
2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) |
| 2197 |
| 2198 #define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334 |
| 2199 #define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334 |
| 2200 #define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24 |
| 2201 #define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0 |
| 2202 #define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff |
| 2203 #define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3
_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) |
| 2204 #define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET
3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) |
| 2205 |
| 2206 #define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338 |
| 2207 #define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338 |
| 2208 #define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31 |
| 2209 #define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24 |
| 2210 #define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000 |
| 2211 #define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_
DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) |
| 2212 #define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0
_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) |
| 2213 #define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23 |
| 2214 #define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16 |
| 2215 #define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000 |
| 2216 #define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_
DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) |
| 2217 #define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0
_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) |
| 2218 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15 |
| 2219 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8 |
| 2220 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00 |
| 2221 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STA
TUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) |
| 2222 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_ST
ATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) |
| 2223 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7 |
| 2224 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0 |
| 2225 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff |
| 2226 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STA
TUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) |
| 2227 #define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_ST
ATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) |
| 2228 |
| 2229 #define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c |
| 2230 #define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c |
| 2231 #define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17 |
| 2232 #define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0 |
| 2233 #define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff |
| 2234 #define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_
VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB) |
| 2235 #define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1
_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) |
| 2236 |
| 2237 #define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340 |
| 2238 #define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340 |
| 2239 #define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26 |
| 2240 #define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0 |
| 2241 #define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff |
| 2242 #define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_
VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB) |
| 2243 #define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2
_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) |
| 2244 |
| 2245 #define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344 |
| 2246 #define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344 |
| 2247 #define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23 |
| 2248 #define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0 |
| 2249 #define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff |
| 2250 #define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_
VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB) |
| 2251 #define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3
_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) |
| 2252 |
| 2253 #define HT_HALF_GI_RATE1_ADDRESS 0x00008348 |
| 2254 #define HT_HALF_GI_RATE1_OFFSET 0x00000348 |
| 2255 #define HT_HALF_GI_RATE1_MCS3_MSB 31 |
| 2256 #define HT_HALF_GI_RATE1_MCS3_LSB 24 |
| 2257 #define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000 |
| 2258 #define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_M
ASK) >> HT_HALF_GI_RATE1_MCS3_LSB) |
| 2259 #define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_
LSB) & HT_HALF_GI_RATE1_MCS3_MASK) |
| 2260 #define HT_HALF_GI_RATE1_MCS2_MSB 23 |
| 2261 #define HT_HALF_GI_RATE1_MCS2_LSB 16 |
| 2262 #define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000 |
| 2263 #define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_M
ASK) >> HT_HALF_GI_RATE1_MCS2_LSB) |
| 2264 #define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_
LSB) & HT_HALF_GI_RATE1_MCS2_MASK) |
| 2265 #define HT_HALF_GI_RATE1_MCS1_MSB 15 |
| 2266 #define HT_HALF_GI_RATE1_MCS1_LSB 8 |
| 2267 #define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00 |
| 2268 #define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_M
ASK) >> HT_HALF_GI_RATE1_MCS1_LSB) |
| 2269 #define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_
LSB) & HT_HALF_GI_RATE1_MCS1_MASK) |
| 2270 #define HT_HALF_GI_RATE1_MCS0_MSB 7 |
| 2271 #define HT_HALF_GI_RATE1_MCS0_LSB 0 |
| 2272 #define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff |
| 2273 #define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_M
ASK) >> HT_HALF_GI_RATE1_MCS0_LSB) |
| 2274 #define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_
LSB) & HT_HALF_GI_RATE1_MCS0_MASK) |
| 2275 |
| 2276 #define HT_HALF_GI_RATE2_ADDRESS 0x0000834c |
| 2277 #define HT_HALF_GI_RATE2_OFFSET 0x0000034c |
| 2278 #define HT_HALF_GI_RATE2_MCS7_MSB 31 |
| 2279 #define HT_HALF_GI_RATE2_MCS7_LSB 24 |
| 2280 #define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000 |
| 2281 #define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_M
ASK) >> HT_HALF_GI_RATE2_MCS7_LSB) |
| 2282 #define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_
LSB) & HT_HALF_GI_RATE2_MCS7_MASK) |
| 2283 #define HT_HALF_GI_RATE2_MCS6_MSB 23 |
| 2284 #define HT_HALF_GI_RATE2_MCS6_LSB 16 |
| 2285 #define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000 |
| 2286 #define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_M
ASK) >> HT_HALF_GI_RATE2_MCS6_LSB) |
| 2287 #define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_
LSB) & HT_HALF_GI_RATE2_MCS6_MASK) |
| 2288 #define HT_HALF_GI_RATE2_MCS5_MSB 15 |
| 2289 #define HT_HALF_GI_RATE2_MCS5_LSB 8 |
| 2290 #define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00 |
| 2291 #define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_M
ASK) >> HT_HALF_GI_RATE2_MCS5_LSB) |
| 2292 #define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_
LSB) & HT_HALF_GI_RATE2_MCS5_MASK) |
| 2293 #define HT_HALF_GI_RATE2_MCS4_MSB 7 |
| 2294 #define HT_HALF_GI_RATE2_MCS4_LSB 0 |
| 2295 #define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff |
| 2296 #define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_M
ASK) >> HT_HALF_GI_RATE2_MCS4_LSB) |
| 2297 #define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_
LSB) & HT_HALF_GI_RATE2_MCS4_MASK) |
| 2298 |
| 2299 #define HT_FULL_GI_RATE1_ADDRESS 0x00008350 |
| 2300 #define HT_FULL_GI_RATE1_OFFSET 0x00000350 |
| 2301 #define HT_FULL_GI_RATE1_MCS3_MSB 31 |
| 2302 #define HT_FULL_GI_RATE1_MCS3_LSB 24 |
| 2303 #define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000 |
| 2304 #define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_M
ASK) >> HT_FULL_GI_RATE1_MCS3_LSB) |
| 2305 #define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_
LSB) & HT_FULL_GI_RATE1_MCS3_MASK) |
| 2306 #define HT_FULL_GI_RATE1_MCS2_MSB 23 |
| 2307 #define HT_FULL_GI_RATE1_MCS2_LSB 16 |
| 2308 #define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000 |
| 2309 #define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_M
ASK) >> HT_FULL_GI_RATE1_MCS2_LSB) |
| 2310 #define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_
LSB) & HT_FULL_GI_RATE1_MCS2_MASK) |
| 2311 #define HT_FULL_GI_RATE1_MCS1_MSB 15 |
| 2312 #define HT_FULL_GI_RATE1_MCS1_LSB 8 |
| 2313 #define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00 |
| 2314 #define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_M
ASK) >> HT_FULL_GI_RATE1_MCS1_LSB) |
| 2315 #define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_
LSB) & HT_FULL_GI_RATE1_MCS1_MASK) |
| 2316 #define HT_FULL_GI_RATE1_MCS0_MSB 7 |
| 2317 #define HT_FULL_GI_RATE1_MCS0_LSB 0 |
| 2318 #define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff |
| 2319 #define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_M
ASK) >> HT_FULL_GI_RATE1_MCS0_LSB) |
| 2320 #define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_
LSB) & HT_FULL_GI_RATE1_MCS0_MASK) |
| 2321 |
| 2322 #define HT_FULL_GI_RATE2_ADDRESS 0x00008354 |
| 2323 #define HT_FULL_GI_RATE2_OFFSET 0x00000354 |
| 2324 #define HT_FULL_GI_RATE2_MCS7_MSB 31 |
| 2325 #define HT_FULL_GI_RATE2_MCS7_LSB 24 |
| 2326 #define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000 |
| 2327 #define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_M
ASK) >> HT_FULL_GI_RATE2_MCS7_LSB) |
| 2328 #define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_
LSB) & HT_FULL_GI_RATE2_MCS7_MASK) |
| 2329 #define HT_FULL_GI_RATE2_MCS6_MSB 23 |
| 2330 #define HT_FULL_GI_RATE2_MCS6_LSB 16 |
| 2331 #define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000 |
| 2332 #define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_M
ASK) >> HT_FULL_GI_RATE2_MCS6_LSB) |
| 2333 #define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_
LSB) & HT_FULL_GI_RATE2_MCS6_MASK) |
| 2334 #define HT_FULL_GI_RATE2_MCS5_MSB 15 |
| 2335 #define HT_FULL_GI_RATE2_MCS5_LSB 8 |
| 2336 #define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00 |
| 2337 #define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_M
ASK) >> HT_FULL_GI_RATE2_MCS5_LSB) |
| 2338 #define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_
LSB) & HT_FULL_GI_RATE2_MCS5_MASK) |
| 2339 #define HT_FULL_GI_RATE2_MCS4_MSB 7 |
| 2340 #define HT_FULL_GI_RATE2_MCS4_LSB 0 |
| 2341 #define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff |
| 2342 #define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_M
ASK) >> HT_FULL_GI_RATE2_MCS4_LSB) |
| 2343 #define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_
LSB) & HT_FULL_GI_RATE2_MCS4_MASK) |
| 2344 |
| 2345 #define LEGACY_RATE1_ADDRESS 0x00008358 |
| 2346 #define LEGACY_RATE1_OFFSET 0x00000358 |
| 2347 #define LEGACY_RATE1_RATE12_MSB 29 |
| 2348 #define LEGACY_RATE1_RATE12_LSB 24 |
| 2349 #define LEGACY_RATE1_RATE12_MASK 0x3f000000 |
| 2350 #define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MAS
K) >> LEGACY_RATE1_RATE12_LSB) |
| 2351 #define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LS
B) & LEGACY_RATE1_RATE12_MASK) |
| 2352 #define LEGACY_RATE1_RATE11_MSB 23 |
| 2353 #define LEGACY_RATE1_RATE11_LSB 18 |
| 2354 #define LEGACY_RATE1_RATE11_MASK 0x00fc0000 |
| 2355 #define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MAS
K) >> LEGACY_RATE1_RATE11_LSB) |
| 2356 #define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LS
B) & LEGACY_RATE1_RATE11_MASK) |
| 2357 #define LEGACY_RATE1_RATE10_MSB 17 |
| 2358 #define LEGACY_RATE1_RATE10_LSB 12 |
| 2359 #define LEGACY_RATE1_RATE10_MASK 0x0003f000 |
| 2360 #define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MAS
K) >> LEGACY_RATE1_RATE10_LSB) |
| 2361 #define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LS
B) & LEGACY_RATE1_RATE10_MASK) |
| 2362 #define LEGACY_RATE1_RATE9_MSB 11 |
| 2363 #define LEGACY_RATE1_RATE9_LSB 6 |
| 2364 #define LEGACY_RATE1_RATE9_MASK 0x00000fc0 |
| 2365 #define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK
) >> LEGACY_RATE1_RATE9_LSB) |
| 2366 #define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB
) & LEGACY_RATE1_RATE9_MASK) |
| 2367 #define LEGACY_RATE1_RATE8_MSB 5 |
| 2368 #define LEGACY_RATE1_RATE8_LSB 0 |
| 2369 #define LEGACY_RATE1_RATE8_MASK 0x0000003f |
| 2370 #define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK
) >> LEGACY_RATE1_RATE8_LSB) |
| 2371 #define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB
) & LEGACY_RATE1_RATE8_MASK) |
| 2372 |
| 2373 #define LEGACY_RATE2_ADDRESS 0x0000835c |
| 2374 #define LEGACY_RATE2_OFFSET 0x0000035c |
| 2375 #define LEGACY_RATE2_RATE25_MSB 29 |
| 2376 #define LEGACY_RATE2_RATE25_LSB 24 |
| 2377 #define LEGACY_RATE2_RATE25_MASK 0x3f000000 |
| 2378 #define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MAS
K) >> LEGACY_RATE2_RATE25_LSB) |
| 2379 #define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LS
B) & LEGACY_RATE2_RATE25_MASK) |
| 2380 #define LEGACY_RATE2_RATE24_MSB 23 |
| 2381 #define LEGACY_RATE2_RATE24_LSB 18 |
| 2382 #define LEGACY_RATE2_RATE24_MASK 0x00fc0000 |
| 2383 #define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MAS
K) >> LEGACY_RATE2_RATE24_LSB) |
| 2384 #define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LS
B) & LEGACY_RATE2_RATE24_MASK) |
| 2385 #define LEGACY_RATE2_RATE15_MSB 17 |
| 2386 #define LEGACY_RATE2_RATE15_LSB 12 |
| 2387 #define LEGACY_RATE2_RATE15_MASK 0x0003f000 |
| 2388 #define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MAS
K) >> LEGACY_RATE2_RATE15_LSB) |
| 2389 #define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LS
B) & LEGACY_RATE2_RATE15_MASK) |
| 2390 #define LEGACY_RATE2_RATE14_MSB 11 |
| 2391 #define LEGACY_RATE2_RATE14_LSB 6 |
| 2392 #define LEGACY_RATE2_RATE14_MASK 0x00000fc0 |
| 2393 #define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MAS
K) >> LEGACY_RATE2_RATE14_LSB) |
| 2394 #define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LS
B) & LEGACY_RATE2_RATE14_MASK) |
| 2395 #define LEGACY_RATE2_RATE13_MSB 5 |
| 2396 #define LEGACY_RATE2_RATE13_LSB 0 |
| 2397 #define LEGACY_RATE2_RATE13_MASK 0x0000003f |
| 2398 #define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MAS
K) >> LEGACY_RATE2_RATE13_LSB) |
| 2399 #define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LS
B) & LEGACY_RATE2_RATE13_MASK) |
| 2400 |
| 2401 #define LEGACY_RATE3_ADDRESS 0x00008360 |
| 2402 #define LEGACY_RATE3_OFFSET 0x00000360 |
| 2403 #define LEGACY_RATE3_RATE30_MSB 29 |
| 2404 #define LEGACY_RATE3_RATE30_LSB 24 |
| 2405 #define LEGACY_RATE3_RATE30_MASK 0x3f000000 |
| 2406 #define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MAS
K) >> LEGACY_RATE3_RATE30_LSB) |
| 2407 #define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LS
B) & LEGACY_RATE3_RATE30_MASK) |
| 2408 #define LEGACY_RATE3_RATE29_MSB 23 |
| 2409 #define LEGACY_RATE3_RATE29_LSB 18 |
| 2410 #define LEGACY_RATE3_RATE29_MASK 0x00fc0000 |
| 2411 #define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MAS
K) >> LEGACY_RATE3_RATE29_LSB) |
| 2412 #define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LS
B) & LEGACY_RATE3_RATE29_MASK) |
| 2413 #define LEGACY_RATE3_RATE28_MSB 17 |
| 2414 #define LEGACY_RATE3_RATE28_LSB 12 |
| 2415 #define LEGACY_RATE3_RATE28_MASK 0x0003f000 |
| 2416 #define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MAS
K) >> LEGACY_RATE3_RATE28_LSB) |
| 2417 #define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LS
B) & LEGACY_RATE3_RATE28_MASK) |
| 2418 #define LEGACY_RATE3_RATE27_MSB 11 |
| 2419 #define LEGACY_RATE3_RATE27_LSB 6 |
| 2420 #define LEGACY_RATE3_RATE27_MASK 0x00000fc0 |
| 2421 #define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MAS
K) >> LEGACY_RATE3_RATE27_LSB) |
| 2422 #define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LS
B) & LEGACY_RATE3_RATE27_MASK) |
| 2423 #define LEGACY_RATE3_RATE26_MSB 5 |
| 2424 #define LEGACY_RATE3_RATE26_LSB 0 |
| 2425 #define LEGACY_RATE3_RATE26_MASK 0x0000003f |
| 2426 #define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MAS
K) >> LEGACY_RATE3_RATE26_LSB) |
| 2427 #define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LS
B) & LEGACY_RATE3_RATE26_MASK) |
| 2428 |
| 2429 #define RX_INT_FILTER_ADDRESS 0x00008364 |
| 2430 #define RX_INT_FILTER_OFFSET 0x00000364 |
| 2431 #define RX_INT_FILTER_BEACON_MSB 17 |
| 2432 #define RX_INT_FILTER_BEACON_LSB 17 |
| 2433 #define RX_INT_FILTER_BEACON_MASK 0x00020000 |
| 2434 #define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MA
SK) >> RX_INT_FILTER_BEACON_LSB) |
| 2435 #define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_L
SB) & RX_INT_FILTER_BEACON_MASK) |
| 2436 #define RX_INT_FILTER_AMPDU_MSB 16 |
| 2437 #define RX_INT_FILTER_AMPDU_LSB 16 |
| 2438 #define RX_INT_FILTER_AMPDU_MASK 0x00010000 |
| 2439 #define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MAS
K) >> RX_INT_FILTER_AMPDU_LSB) |
| 2440 #define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LS
B) & RX_INT_FILTER_AMPDU_MASK) |
| 2441 #define RX_INT_FILTER_EOSP_MSB 15 |
| 2442 #define RX_INT_FILTER_EOSP_LSB 15 |
| 2443 #define RX_INT_FILTER_EOSP_MASK 0x00008000 |
| 2444 #define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK
) >> RX_INT_FILTER_EOSP_LSB) |
| 2445 #define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB
) & RX_INT_FILTER_EOSP_MASK) |
| 2446 #define RX_INT_FILTER_LENGTH_LOW_MSB 14 |
| 2447 #define RX_INT_FILTER_LENGTH_LOW_LSB 14 |
| 2448 #define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000 |
| 2449 #define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LO
W_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB) |
| 2450 #define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_L
OW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK) |
| 2451 #define RX_INT_FILTER_LENGTH_HIGH_MSB 13 |
| 2452 #define RX_INT_FILTER_LENGTH_HIGH_LSB 13 |
| 2453 #define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000 |
| 2454 #define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HI
GH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB) |
| 2455 #define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_H
IGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK) |
| 2456 #define RX_INT_FILTER_RSSI_MSB 12 |
| 2457 #define RX_INT_FILTER_RSSI_LSB 12 |
| 2458 #define RX_INT_FILTER_RSSI_MASK 0x00001000 |
| 2459 #define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK
) >> RX_INT_FILTER_RSSI_LSB) |
| 2460 #define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB
) & RX_INT_FILTER_RSSI_MASK) |
| 2461 #define RX_INT_FILTER_RATE_LOW_MSB 11 |
| 2462 #define RX_INT_FILTER_RATE_LOW_LSB 11 |
| 2463 #define RX_INT_FILTER_RATE_LOW_MASK 0x00000800 |
| 2464 #define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_
MASK) >> RX_INT_FILTER_RATE_LOW_LSB) |
| 2465 #define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW
_LSB) & RX_INT_FILTER_RATE_LOW_MASK) |
| 2466 #define RX_INT_FILTER_RATE_HIGH_MSB 10 |
| 2467 #define RX_INT_FILTER_RATE_HIGH_LSB 10 |
| 2468 #define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400 |
| 2469 #define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH
_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB) |
| 2470 #define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIG
H_LSB) & RX_INT_FILTER_RATE_HIGH_MASK) |
| 2471 #define RX_INT_FILTER_MORE_FRAG_MSB 9 |
| 2472 #define RX_INT_FILTER_MORE_FRAG_LSB 9 |
| 2473 #define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200 |
| 2474 #define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG
_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB) |
| 2475 #define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRA
G_LSB) & RX_INT_FILTER_MORE_FRAG_MASK) |
| 2476 #define RX_INT_FILTER_MORE_DATA_MSB 8 |
| 2477 #define RX_INT_FILTER_MORE_DATA_LSB 8 |
| 2478 #define RX_INT_FILTER_MORE_DATA_MASK 0x00000100 |
| 2479 #define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA
_MASK) >> RX_INT_FILTER_MORE_DATA_LSB) |
| 2480 #define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DAT
A_LSB) & RX_INT_FILTER_MORE_DATA_MASK) |
| 2481 #define RX_INT_FILTER_RETRY_MSB 7 |
| 2482 #define RX_INT_FILTER_RETRY_LSB 7 |
| 2483 #define RX_INT_FILTER_RETRY_MASK 0x00000080 |
| 2484 #define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MAS
K) >> RX_INT_FILTER_RETRY_LSB) |
| 2485 #define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LS
B) & RX_INT_FILTER_RETRY_MASK) |
| 2486 #define RX_INT_FILTER_CTS_MSB 6 |
| 2487 #define RX_INT_FILTER_CTS_LSB 6 |
| 2488 #define RX_INT_FILTER_CTS_MASK 0x00000040 |
| 2489 #define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK)
>> RX_INT_FILTER_CTS_LSB) |
| 2490 #define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB)
& RX_INT_FILTER_CTS_MASK) |
| 2491 #define RX_INT_FILTER_ACK_MSB 5 |
| 2492 #define RX_INT_FILTER_ACK_LSB 5 |
| 2493 #define RX_INT_FILTER_ACK_MASK 0x00000020 |
| 2494 #define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK)
>> RX_INT_FILTER_ACK_LSB) |
| 2495 #define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB)
& RX_INT_FILTER_ACK_MASK) |
| 2496 #define RX_INT_FILTER_RTS_MSB 4 |
| 2497 #define RX_INT_FILTER_RTS_LSB 4 |
| 2498 #define RX_INT_FILTER_RTS_MASK 0x00000010 |
| 2499 #define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK)
>> RX_INT_FILTER_RTS_LSB) |
| 2500 #define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB)
& RX_INT_FILTER_RTS_MASK) |
| 2501 #define RX_INT_FILTER_MCAST_MSB 3 |
| 2502 #define RX_INT_FILTER_MCAST_LSB 3 |
| 2503 #define RX_INT_FILTER_MCAST_MASK 0x00000008 |
| 2504 #define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MAS
K) >> RX_INT_FILTER_MCAST_LSB) |
| 2505 #define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LS
B) & RX_INT_FILTER_MCAST_MASK) |
| 2506 #define RX_INT_FILTER_BCAST_MSB 2 |
| 2507 #define RX_INT_FILTER_BCAST_LSB 2 |
| 2508 #define RX_INT_FILTER_BCAST_MASK 0x00000004 |
| 2509 #define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MAS
K) >> RX_INT_FILTER_BCAST_LSB) |
| 2510 #define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LS
B) & RX_INT_FILTER_BCAST_MASK) |
| 2511 #define RX_INT_FILTER_DIRECTED_MSB 1 |
| 2512 #define RX_INT_FILTER_DIRECTED_LSB 1 |
| 2513 #define RX_INT_FILTER_DIRECTED_MASK 0x00000002 |
| 2514 #define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_
MASK) >> RX_INT_FILTER_DIRECTED_LSB) |
| 2515 #define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED
_LSB) & RX_INT_FILTER_DIRECTED_MASK) |
| 2516 #define RX_INT_FILTER_ENABLE_MSB 0 |
| 2517 #define RX_INT_FILTER_ENABLE_LSB 0 |
| 2518 #define RX_INT_FILTER_ENABLE_MASK 0x00000001 |
| 2519 #define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MA
SK) >> RX_INT_FILTER_ENABLE_LSB) |
| 2520 #define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_L
SB) & RX_INT_FILTER_ENABLE_MASK) |
| 2521 |
| 2522 #define RX_INT_OVERFLOW_ADDRESS 0x00008368 |
| 2523 #define RX_INT_OVERFLOW_OFFSET 0x00000368 |
| 2524 #define RX_INT_OVERFLOW_STATUS_MSB 0 |
| 2525 #define RX_INT_OVERFLOW_STATUS_LSB 0 |
| 2526 #define RX_INT_OVERFLOW_STATUS_MASK 0x00000001 |
| 2527 #define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_
MASK) >> RX_INT_OVERFLOW_STATUS_LSB) |
| 2528 #define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS
_LSB) & RX_INT_OVERFLOW_STATUS_MASK) |
| 2529 |
| 2530 #define RX_FILTER_THRESH_ADDRESS 0x0000836c |
| 2531 #define RX_FILTER_THRESH_OFFSET 0x0000036c |
| 2532 #define RX_FILTER_THRESH_RSSI_LOW_MSB 23 |
| 2533 #define RX_FILTER_THRESH_RSSI_LOW_LSB 16 |
| 2534 #define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000 |
| 2535 #define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_L
OW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB) |
| 2536 #define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_
LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK) |
| 2537 #define RX_FILTER_THRESH_RATE_LOW_MSB 15 |
| 2538 #define RX_FILTER_THRESH_RATE_LOW_LSB 8 |
| 2539 #define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00 |
| 2540 #define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_L
OW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB) |
| 2541 #define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_
LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK) |
| 2542 #define RX_FILTER_THRESH_RATE_HIGH_MSB 7 |
| 2543 #define RX_FILTER_THRESH_RATE_HIGH_LSB 0 |
| 2544 #define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff |
| 2545 #define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_H
IGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB) |
| 2546 #define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_
HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK) |
| 2547 |
| 2548 #define RX_FILTER_THRESH1_ADDRESS 0x00008370 |
| 2549 #define RX_FILTER_THRESH1_OFFSET 0x00000370 |
| 2550 #define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23 |
| 2551 #define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12 |
| 2552 #define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000 |
| 2553 #define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGT
H_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB) |
| 2554 #define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENG
TH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) |
| 2555 #define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11 |
| 2556 #define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0 |
| 2557 #define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff |
| 2558 #define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGT
H_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB) |
| 2559 #define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENG
TH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) |
| 2560 |
| 2561 #define RX_PRIORITY_THRESH0_ADDRESS 0x00008374 |
| 2562 #define RX_PRIORITY_THRESH0_OFFSET 0x00000374 |
| 2563 #define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31 |
| 2564 #define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24 |
| 2565 #define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000 |
| 2566 #define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSS
I_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB) |
| 2567 #define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RS
SI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) |
| 2568 #define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23 |
| 2569 #define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16 |
| 2570 #define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000 |
| 2571 #define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSS
I_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) |
| 2572 #define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RS
SI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) |
| 2573 #define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15 |
| 2574 #define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8 |
| 2575 #define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00 |
| 2576 #define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RAT
E_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB) |
| 2577 #define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RA
TE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) |
| 2578 #define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7 |
| 2579 #define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0 |
| 2580 #define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff |
| 2581 #define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RAT
E_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB) |
| 2582 #define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RA
TE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) |
| 2583 |
| 2584 #define RX_PRIORITY_THRESH1_ADDRESS 0x00008378 |
| 2585 #define RX_PRIORITY_THRESH1_OFFSET 0x00000378 |
| 2586 #define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31 |
| 2587 #define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24 |
| 2588 #define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000 |
| 2589 #define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_X
CAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) |
| 2590 #define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_
XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) |
| 2591 #define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23 |
| 2592 #define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12 |
| 2593 #define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000 |
| 2594 #define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LEN
GTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) |
| 2595 #define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LE
NGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) |
| 2596 #define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11 |
| 2597 #define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0 |
| 2598 #define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff |
| 2599 #define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LEN
GTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) |
| 2600 #define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LE
NGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) |
| 2601 |
| 2602 #define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c |
| 2603 #define RX_PRIORITY_THRESH2_OFFSET 0x0000037c |
| 2604 #define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31 |
| 2605 #define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24 |
| 2606 #define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000 |
| 2607 #define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NU
LL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) |
| 2608 #define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_N
ULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) |
| 2609 #define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23 |
| 2610 #define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16 |
| 2611 #define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000 |
| 2612 #define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_
BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) |
| 2613 #define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2
_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) |
| 2614 #define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15 |
| 2615 #define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8 |
| 2616 #define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00 |
| 2617 #define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MG
MT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) |
| 2618 #define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_M
GMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) |
| 2619 #define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7 |
| 2620 #define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0 |
| 2621 #define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff |
| 2622 #define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_P
RESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) |
| 2623 #define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_
PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) |
| 2624 |
| 2625 #define RX_PRIORITY_THRESH3_ADDRESS 0x00008380 |
| 2626 #define RX_PRIORITY_THRESH3_OFFSET 0x00000380 |
| 2627 #define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15 |
| 2628 #define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8 |
| 2629 #define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00 |
| 2630 #define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3
_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) |
| 2631 #define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH
3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) |
| 2632 #define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7 |
| 2633 #define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0 |
| 2634 #define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff |
| 2635 #define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PR
EQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) |
| 2636 #define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_P
REQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) |
| 2637 |
| 2638 #define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384 |
| 2639 #define RX_PRIORITY_OFFSET0_OFFSET 0x00000384 |
| 2640 #define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29 |
| 2641 #define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24 |
| 2642 #define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000 |
| 2643 #define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_X
CAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) |
| 2644 #define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_
XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) |
| 2645 #define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23 |
| 2646 #define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18 |
| 2647 #define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000 |
| 2648 #define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSS
I_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) |
| 2649 #define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RS
SI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) |
| 2650 #define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17 |
| 2651 #define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12 |
| 2652 #define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000 |
| 2653 #define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSS
I_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) |
| 2654 #define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RS
SI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) |
| 2655 #define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11 |
| 2656 #define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6 |
| 2657 #define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0 |
| 2658 #define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY
_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) |
| 2659 #define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PH
Y_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) |
| 2660 #define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5 |
| 2661 #define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0 |
| 2662 #define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f |
| 2663 #define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY
_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) |
| 2664 #define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PH
Y_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) |
| 2665 |
| 2666 #define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388 |
| 2667 #define RX_PRIORITY_OFFSET1_OFFSET 0x00000388 |
| 2668 #define RX_PRIORITY_OFFSET1_RTS_MSB 29 |
| 2669 #define RX_PRIORITY_OFFSET1_RTS_LSB 24 |
| 2670 #define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000 |
| 2671 #define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS
_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB) |
| 2672 #define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RT
S_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK) |
| 2673 #define RX_PRIORITY_OFFSET1_RETX_MSB 23 |
| 2674 #define RX_PRIORITY_OFFSET1_RETX_LSB 18 |
| 2675 #define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000 |
| 2676 #define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RET
X_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB) |
| 2677 #define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RE
TX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK) |
| 2678 #define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17 |
| 2679 #define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12 |
| 2680 #define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000 |
| 2681 #define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_P
RESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) |
| 2682 #define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_
PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) |
| 2683 #define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11 |
| 2684 #define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6 |
| 2685 #define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0 |
| 2686 #define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LEN
GTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) |
| 2687 #define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LE
NGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) |
| 2688 #define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5 |
| 2689 #define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0 |
| 2690 #define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f |
| 2691 #define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LEN
GTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) |
| 2692 #define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LE
NGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) |
| 2693 |
| 2694 #define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c |
| 2695 #define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c |
| 2696 #define RX_PRIORITY_OFFSET2_BEACON_MSB 29 |
| 2697 #define RX_PRIORITY_OFFSET2_BEACON_LSB 24 |
| 2698 #define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000 |
| 2699 #define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEA
CON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB) |
| 2700 #define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BE
ACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK) |
| 2701 #define RX_PRIORITY_OFFSET2_MGMT_MSB 23 |
| 2702 #define RX_PRIORITY_OFFSET2_MGMT_LSB 18 |
| 2703 #define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000 |
| 2704 #define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGM
T_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB) |
| 2705 #define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MG
MT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK) |
| 2706 #define RX_PRIORITY_OFFSET2_ATIM_MSB 17 |
| 2707 #define RX_PRIORITY_OFFSET2_ATIM_LSB 12 |
| 2708 #define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000 |
| 2709 #define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATI
M_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB) |
| 2710 #define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_AT
IM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK) |
| 2711 #define RX_PRIORITY_OFFSET2_PRESP_MSB 11 |
| 2712 #define RX_PRIORITY_OFFSET2_PRESP_LSB 6 |
| 2713 #define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0 |
| 2714 #define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRE
SP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB) |
| 2715 #define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PR
ESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK) |
| 2716 #define RX_PRIORITY_OFFSET2_XCAST_MSB 5 |
| 2717 #define RX_PRIORITY_OFFSET2_XCAST_LSB 0 |
| 2718 #define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f |
| 2719 #define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCA
ST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB) |
| 2720 #define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XC
AST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK) |
| 2721 |
| 2722 #define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390 |
| 2723 #define RX_PRIORITY_OFFSET3_OFFSET 0x00000390 |
| 2724 #define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29 |
| 2725 #define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24 |
| 2726 #define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000 |
| 2727 #define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_
POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB) |
| 2728 #define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS
_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) |
| 2729 #define RX_PRIORITY_OFFSET3_AMSDU_MSB 23 |
| 2730 #define RX_PRIORITY_OFFSET3_AMSDU_LSB 18 |
| 2731 #define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000 |
| 2732 #define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMS
DU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB) |
| 2733 #define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AM
SDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK) |
| 2734 #define RX_PRIORITY_OFFSET3_AMPDU_MSB 17 |
| 2735 #define RX_PRIORITY_OFFSET3_AMPDU_LSB 12 |
| 2736 #define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000 |
| 2737 #define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMP
DU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB) |
| 2738 #define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AM
PDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK) |
| 2739 #define RX_PRIORITY_OFFSET3_EOSP_MSB 11 |
| 2740 #define RX_PRIORITY_OFFSET3_EOSP_LSB 6 |
| 2741 #define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0 |
| 2742 #define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOS
P_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB) |
| 2743 #define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EO
SP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK) |
| 2744 #define RX_PRIORITY_OFFSET3_MORE_MSB 5 |
| 2745 #define RX_PRIORITY_OFFSET3_MORE_LSB 0 |
| 2746 #define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f |
| 2747 #define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MOR
E_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB) |
| 2748 #define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MO
RE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK) |
| 2749 |
| 2750 #define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394 |
| 2751 #define RX_PRIORITY_OFFSET4_OFFSET 0x00000394 |
| 2752 #define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29 |
| 2753 #define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24 |
| 2754 #define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000 |
| 2755 #define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_
BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) |
| 2756 #define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4
_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) |
| 2757 #define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23 |
| 2758 #define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18 |
| 2759 #define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000 |
| 2760 #define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MG
MT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) |
| 2761 #define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_M
GMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) |
| 2762 #define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17 |
| 2763 #define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12 |
| 2764 #define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000 |
| 2765 #define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEA
CON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) |
| 2766 #define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BE
ACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) |
| 2767 #define RX_PRIORITY_OFFSET4_NULL_MSB 11 |
| 2768 #define RX_PRIORITY_OFFSET4_NULL_LSB 6 |
| 2769 #define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0 |
| 2770 #define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NUL
L_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB) |
| 2771 #define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NU
LL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK) |
| 2772 #define RX_PRIORITY_OFFSET4_PREQ_MSB 5 |
| 2773 #define RX_PRIORITY_OFFSET4_PREQ_LSB 0 |
| 2774 #define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f |
| 2775 #define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PRE
Q_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB) |
| 2776 #define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PR
EQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK) |
| 2777 |
| 2778 #define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398 |
| 2779 #define RX_PRIORITY_OFFSET5_OFFSET 0x00000398 |
| 2780 #define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17 |
| 2781 #define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12 |
| 2782 #define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000 |
| 2783 #define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5
_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) |
| 2784 #define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET
5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) |
| 2785 #define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11 |
| 2786 #define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6 |
| 2787 #define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0 |
| 2788 #define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PR
EQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) |
| 2789 #define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_P
REQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) |
| 2790 #define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5 |
| 2791 #define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0 |
| 2792 #define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f |
| 2793 #define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NU
LL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) |
| 2794 #define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_N
ULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) |
| 2795 |
| 2796 #define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c |
| 2797 #define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c |
| 2798 #define MAC_PCU_BSSID2_L32_ADDR_MSB 31 |
| 2799 #define MAC_PCU_BSSID2_L32_ADDR_LSB 0 |
| 2800 #define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff |
| 2801 #define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR
_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB) |
| 2802 #define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADD
R_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK) |
| 2803 |
| 2804 #define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0 |
| 2805 #define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0 |
| 2806 #define MAC_PCU_BSSID2_U16_ENABLE_MSB 16 |
| 2807 #define MAC_PCU_BSSID2_U16_ENABLE_LSB 16 |
| 2808 #define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000 |
| 2809 #define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENAB
LE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB) |
| 2810 #define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENA
BLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK) |
| 2811 #define MAC_PCU_BSSID2_U16_ADDR_MSB 15 |
| 2812 #define MAC_PCU_BSSID2_U16_ADDR_LSB 0 |
| 2813 #define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff |
| 2814 #define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR
_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB) |
| 2815 #define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADD
R_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK) |
| 2816 |
| 2817 #define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4 |
| 2818 #define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4 |
| 2819 #define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31 |
| 2820 #define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0 |
| 2821 #define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff |
| 2822 #define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32
_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) |
| 2823 #define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L3
2_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) |
| 2824 |
| 2825 #define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8 |
| 2826 #define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8 |
| 2827 #define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31 |
| 2828 #define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0 |
| 2829 #define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff |
| 2830 #define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32
_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) |
| 2831 #define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U3
2_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) |
| 2832 |
| 2833 #define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac |
| 2834 #define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac |
| 2835 #define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31 |
| 2836 #define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0 |
| 2837 #define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff |
| 2838 #define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32
_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) |
| 2839 #define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L3
2_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) |
| 2840 |
| 2841 #define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0 |
| 2842 #define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0 |
| 2843 #define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31 |
| 2844 #define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0 |
| 2845 #define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff |
| 2846 #define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32
_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) |
| 2847 #define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U3
2_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) |
| 2848 |
| 2849 #define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400 |
| 2850 #define MAC_PCU_TXBUF_BA_OFFSET 0x00000400 |
| 2851 #define MAC_PCU_TXBUF_BA_DATA_MSB 31 |
| 2852 #define MAC_PCU_TXBUF_BA_DATA_LSB 0 |
| 2853 #define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff |
| 2854 #define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_M
ASK) >> MAC_PCU_TXBUF_BA_DATA_LSB) |
| 2855 #define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_
LSB) & MAC_PCU_TXBUF_BA_DATA_MASK) |
| 2856 |
| 2857 #define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800 |
| 2858 #define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800 |
| 2859 #define MAC_PCU_KEY_CACHE_1_DATA_MSB 31 |
| 2860 #define MAC_PCU_KEY_CACHE_1_DATA_LSB 0 |
| 2861 #define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff |
| 2862 #define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DAT
A_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB) |
| 2863 #define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DA
TA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK) |
| 2864 |
| 2865 #define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800 |
| 2866 #define MAC_PCU_BASEBAND_0_OFFSET 0x00001800 |
| 2867 #define MAC_PCU_BASEBAND_0_DATA_MSB 31 |
| 2868 #define MAC_PCU_BASEBAND_0_DATA_LSB 0 |
| 2869 #define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff |
| 2870 #define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA
_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB) |
| 2871 #define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DAT
A_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK) |
| 2872 |
| 2873 #define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000 |
| 2874 #define MAC_PCU_BASEBAND_1_OFFSET 0x00002000 |
| 2875 #define MAC_PCU_BASEBAND_1_DATA_MSB 31 |
| 2876 #define MAC_PCU_BASEBAND_1_DATA_LSB 0 |
| 2877 #define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff |
| 2878 #define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA
_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB) |
| 2879 #define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DAT
A_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK) |
| 2880 |
| 2881 #define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000 |
| 2882 #define MAC_PCU_BASEBAND_2_OFFSET 0x00004000 |
| 2883 #define MAC_PCU_BASEBAND_2_DATA_MSB 31 |
| 2884 #define MAC_PCU_BASEBAND_2_DATA_LSB 0 |
| 2885 #define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff |
| 2886 #define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA
_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB) |
| 2887 #define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DAT
A_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK) |
| 2888 |
| 2889 #define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000 |
| 2890 #define MAC_PCU_BASEBAND_3_OFFSET 0x00005000 |
| 2891 #define MAC_PCU_BASEBAND_3_DATA_MSB 31 |
| 2892 #define MAC_PCU_BASEBAND_3_DATA_LSB 0 |
| 2893 #define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff |
| 2894 #define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA
_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB) |
| 2895 #define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DAT
A_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK) |
| 2896 |
| 2897 #define MAC_PCU_BUF_ADDRESS 0x0000e000 |
| 2898 #define MAC_PCU_BUF_OFFSET 0x00006000 |
| 2899 #define MAC_PCU_BUF_DATA_MSB 31 |
| 2900 #define MAC_PCU_BUF_DATA_LSB 0 |
| 2901 #define MAC_PCU_BUF_DATA_MASK 0xffffffff |
| 2902 #define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK)
>> MAC_PCU_BUF_DATA_LSB) |
| 2903 #define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB)
& MAC_PCU_BUF_DATA_MASK) |
| 2904 |
| 2905 |
| 2906 #ifndef __ASSEMBLER__ |
| 2907 |
| 2908 typedef struct mac_pcu_reg_s { |
| 2909 volatile unsigned int mac_pcu_sta_addr_l32; |
| 2910 volatile unsigned int mac_pcu_sta_addr_u16; |
| 2911 volatile unsigned int mac_pcu_bssid_l32; |
| 2912 volatile unsigned int mac_pcu_bssid_u16; |
| 2913 volatile unsigned int mac_pcu_bcn_rssi_ave; |
| 2914 volatile unsigned int mac_pcu_ack_cts_timeout; |
| 2915 volatile unsigned int mac_pcu_bcn_rssi_ctl; |
| 2916 volatile unsigned int mac_pcu_usec_latency; |
| 2917 volatile unsigned int pcu_max_cfp_dur; |
| 2918 volatile unsigned int mac_pcu_rx_filter; |
| 2919 volatile unsigned int mac_pcu_mcast_filter_l32; |
| 2920 volatile unsigned int mac_pcu_mcast_filter_u32; |
| 2921 volatile unsigned int mac_pcu_diag_sw; |
| 2922 volatile unsigned int mac_pcu_tst_addac; |
| 2923 volatile unsigned int mac_pcu_def_antenna; |
| 2924 volatile unsigned int mac_pcu_aes_mute_mask_0; |
| 2925 volatile unsigned int mac_pcu_aes_mute_mask_1; |
| 2926 volatile unsigned int mac_pcu_gated_clks; |
| 2927 volatile unsigned int mac_pcu_obs_bus_2; |
| 2928 volatile unsigned int mac_pcu_obs_bus_1; |
| 2929 volatile unsigned int mac_pcu_dym_mimo_pwr_save; |
| 2930 volatile unsigned int mac_pcu_last_beacon_tsf; |
| 2931 volatile unsigned int mac_pcu_nav; |
| 2932 volatile unsigned int mac_pcu_rts_success_cnt; |
| 2933 volatile unsigned int mac_pcu_rts_fail_cnt; |
| 2934 volatile unsigned int mac_pcu_ack_fail_cnt; |
| 2935 volatile unsigned int mac_pcu_fcs_fail_cnt; |
| 2936 volatile unsigned int mac_pcu_beacon_cnt; |
| 2937 volatile unsigned int mac_pcu_xrmode; |
| 2938 volatile unsigned int mac_pcu_xrdel; |
| 2939 volatile unsigned int mac_pcu_xrto; |
| 2940 volatile unsigned int mac_pcu_xrcrp; |
| 2941 volatile unsigned int mac_pcu_xrstmp; |
| 2942 volatile unsigned int mac_pcu_addr1_mask_l32; |
| 2943 volatile unsigned int mac_pcu_addr1_mask_u16; |
| 2944 volatile unsigned int mac_pcu_tpc; |
| 2945 volatile unsigned int mac_pcu_tx_frame_cnt; |
| 2946 volatile unsigned int mac_pcu_rx_frame_cnt; |
| 2947 volatile unsigned int mac_pcu_rx_clear_cnt; |
| 2948 volatile unsigned int mac_pcu_cycle_cnt; |
| 2949 volatile unsigned int mac_pcu_quiet_time_1; |
| 2950 volatile unsigned int mac_pcu_quiet_time_2; |
| 2951 volatile unsigned int mac_pcu_qos_no_ack; |
| 2952 volatile unsigned int mac_pcu_phy_error_mask; |
| 2953 volatile unsigned int mac_pcu_xrlat; |
| 2954 volatile unsigned int mac_pcu_rxbuf; |
| 2955 volatile unsigned int mac_pcu_mic_qos_control; |
| 2956 volatile unsigned int mac_pcu_mic_qos_select; |
| 2957 volatile unsigned int mac_pcu_misc_mode; |
| 2958 volatile unsigned int mac_pcu_filter_ofdm_cnt; |
| 2959 volatile unsigned int mac_pcu_filter_cck_cnt; |
| 2960 volatile unsigned int mac_pcu_phy_err_cnt_1; |
| 2961 volatile unsigned int mac_pcu_phy_err_cnt_1_mask; |
| 2962 volatile unsigned int mac_pcu_phy_err_cnt_2; |
| 2963 volatile unsigned int mac_pcu_phy_err_cnt_2_mask; |
| 2964 volatile unsigned int mac_pcu_tsf_threshold; |
| 2965 volatile unsigned int mac_pcu_phy_error_eifs_mask; |
| 2966 volatile unsigned int mac_pcu_phy_err_cnt_3; |
| 2967 volatile unsigned int mac_pcu_phy_err_cnt_3_mask; |
| 2968 volatile unsigned int mac_pcu_bluetooth_mode; |
| 2969 volatile unsigned int mac_pcu_bluetooth_weights; |
| 2970 volatile unsigned int mac_pcu_bluetooth_mode2; |
| 2971 volatile unsigned int mac_pcu_txsifs; |
| 2972 volatile unsigned int mac_pcu_txop_x; |
| 2973 volatile unsigned int mac_pcu_txop_0_3; |
| 2974 volatile unsigned int mac_pcu_txop_4_7; |
| 2975 volatile unsigned int mac_pcu_txop_8_11; |
| 2976 volatile unsigned int mac_pcu_txop_12_15; |
| 2977 volatile unsigned int mac_pcu_logic_analyzer; |
| 2978 volatile unsigned int mac_pcu_logic_analyzer_32l; |
| 2979 volatile unsigned int mac_pcu_logic_analyzer_16u; |
| 2980 volatile unsigned int mac_pcu_phy_err_cnt_mask_cont; |
| 2981 volatile unsigned int mac_pcu_azimuth_mode; |
| 2982 volatile unsigned int mac_pcu_20_40_mode; |
| 2983 volatile unsigned int mac_pcu_rx_clear_diff_cnt; |
| 2984 volatile unsigned int mac_pcu_self_gen_antenna_mask; |
| 2985 volatile unsigned int mac_pcu_ba_bar_control; |
| 2986 volatile unsigned int mac_pcu_legacy_plcp_spoof; |
| 2987 volatile unsigned int mac_pcu_phy_error_mask_cont; |
| 2988 volatile unsigned int mac_pcu_tx_timer; |
| 2989 volatile unsigned int mac_pcu_txbuf_ctrl; |
| 2990 volatile unsigned int mac_pcu_misc_mode2; |
| 2991 volatile unsigned int mac_pcu_alt_aes_mute_mask; |
| 2992 volatile unsigned int mac_pcu_azimuth_time_stamp; |
| 2993 volatile unsigned int mac_pcu_max_cfp_dur; |
| 2994 volatile unsigned int mac_pcu_hcf_timeout; |
| 2995 volatile unsigned int mac_pcu_bluetooth_weights2; |
| 2996 volatile unsigned int mac_pcu_bluetooth_tsf_bt_active; |
| 2997 volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority; |
| 2998 volatile unsigned int mac_pcu_bluetooth_mode3; |
| 2999 volatile unsigned int mac_pcu_bluetooth_mode4; |
| 3000 unsigned char pad0[148]; /* pad to 0x200 */ |
| 3001 volatile unsigned int mac_pcu_bt_bt[64]; |
| 3002 volatile unsigned int mac_pcu_bt_bt_async; |
| 3003 volatile unsigned int mac_pcu_bt_wl_1; |
| 3004 volatile unsigned int mac_pcu_bt_wl_2; |
| 3005 volatile unsigned int mac_pcu_bt_wl_3; |
| 3006 volatile unsigned int mac_pcu_bt_wl_4; |
| 3007 volatile unsigned int mac_pcu_coex_epta; |
| 3008 volatile unsigned int mac_pcu_coex_lnamaxgain1; |
| 3009 volatile unsigned int mac_pcu_coex_lnamaxgain2; |
| 3010 volatile unsigned int mac_pcu_coex_lnamaxgain3; |
| 3011 volatile unsigned int mac_pcu_coex_lnamaxgain4; |
| 3012 volatile unsigned int mac_pcu_basic_rate_set0; |
| 3013 volatile unsigned int mac_pcu_basic_rate_set1; |
| 3014 volatile unsigned int mac_pcu_basic_rate_set2; |
| 3015 volatile unsigned int mac_pcu_basic_rate_set3; |
| 3016 volatile unsigned int mac_pcu_rx_int_status0; |
| 3017 volatile unsigned int mac_pcu_rx_int_status1; |
| 3018 volatile unsigned int mac_pcu_rx_int_status2; |
| 3019 volatile unsigned int mac_pcu_rx_int_status3; |
| 3020 volatile unsigned int ht_half_gi_rate1; |
| 3021 volatile unsigned int ht_half_gi_rate2; |
| 3022 volatile unsigned int ht_full_gi_rate1; |
| 3023 volatile unsigned int ht_full_gi_rate2; |
| 3024 volatile unsigned int legacy_rate1; |
| 3025 volatile unsigned int legacy_rate2; |
| 3026 volatile unsigned int legacy_rate3; |
| 3027 volatile unsigned int rx_int_filter; |
| 3028 volatile unsigned int rx_int_overflow; |
| 3029 volatile unsigned int rx_filter_thresh; |
| 3030 volatile unsigned int rx_filter_thresh1; |
| 3031 volatile unsigned int rx_priority_thresh0; |
| 3032 volatile unsigned int rx_priority_thresh1; |
| 3033 volatile unsigned int rx_priority_thresh2; |
| 3034 volatile unsigned int rx_priority_thresh3; |
| 3035 volatile unsigned int rx_priority_offset0; |
| 3036 volatile unsigned int rx_priority_offset1; |
| 3037 volatile unsigned int rx_priority_offset2; |
| 3038 volatile unsigned int rx_priority_offset3; |
| 3039 volatile unsigned int rx_priority_offset4; |
| 3040 volatile unsigned int rx_priority_offset5; |
| 3041 volatile unsigned int mac_pcu_bssid2_l32; |
| 3042 volatile unsigned int mac_pcu_bssid2_u16; |
| 3043 volatile unsigned int mac_pcu_tsf1_status_l32; |
| 3044 volatile unsigned int mac_pcu_tsf1_status_u32; |
| 3045 volatile unsigned int mac_pcu_tsf2_status_l32; |
| 3046 volatile unsigned int mac_pcu_tsf2_status_u32; |
| 3047 unsigned char pad1[76]; /* pad to 0x400 */ |
| 3048 volatile unsigned int mac_pcu_txbuf_ba[64]; |
| 3049 unsigned char pad2[768]; /* pad to 0x800 */ |
| 3050 volatile unsigned int mac_pcu_key_cache_1[256]; |
| 3051 unsigned char pad3[3072]; /* pad to 0x1800 */ |
| 3052 volatile unsigned int mac_pcu_baseband_0[512]; |
| 3053 volatile unsigned int mac_pcu_baseband_1[2048]; |
| 3054 volatile unsigned int mac_pcu_baseband_2[1024]; |
| 3055 volatile unsigned int mac_pcu_baseband_3[1024]; |
| 3056 volatile unsigned int mac_pcu_buf[512]; |
| 3057 } mac_pcu_reg_t; |
| 3058 |
| 3059 #endif /* __ASSEMBLER__ */ |
| 3060 |
| 3061 #endif /* _MAC_PCU_H_ */ |
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