| OLD | NEW |
|---|
| (Empty) | |
| 1 // |
| 2 // Copyright (c) 2002-2009 Atheros Communications Inc. |
| 3 // All rights reserved. |
| 4 // $ATH_LICENSE_TMAC_DMAGET_C$ |
| 5 // |
| 6 |
| 7 /*****************************************************************************/ |
| 8 /* AR6003 WLAN MAC DMA register definitions */ |
| 9 /*****************************************************************************/ |
| 10 |
| 11 #ifndef _AR6000_DMAREG_H_ |
| 12 #define _AR6000_DMAREG_H_ |
| 13 |
| 14 /* |
| 15 * Definitions for the Atheros AR6003 chipset. |
| 16 */ |
| 17 |
| 18 /* DMA Control and Interrupt Registers */ |
| 19 #define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control regis
ter */ |
| 20 #define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */ |
| 21 #define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable *
/ |
| 22 #define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software
interrupt */ |
| 23 |
| 24 #define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue
descriptor pointer */ |
| 25 |
| 26 #define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration
and status register */ |
| 27 #define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descr
iptor words */ |
| 28 #define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data
buffer words */ |
| 29 #define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descr
iptor words */ |
| 30 #define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data
buffer words */ |
| 31 #define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register
access data words */ |
| 32 #define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indicati
on (0-AP, 1-Adhoc) */ |
| 33 #define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */ |
| 34 #define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disa
ble */ |
| 35 |
| 36 #define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate thre
shold register */ |
| 37 #define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF |
| 38 |
| 39 #define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt en
able register */ |
| 40 #define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt
enable */ |
| 41 #define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt
disable */ |
| 42 |
| 43 #define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrup
t Mitigation Threshold */ |
| 44 #define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet thres
hold mask */ |
| 45 #define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet thre
shold mask */ |
| 46 |
| 47 #define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt
Mitigation Threshold */ |
| 48 #define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet thres
hold mask */ |
| 49 #define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet thre
shold mask */ |
| 50 |
| 51 #define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size
config register */ |
| 52 #define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame tr
igger level */ |
| 53 #define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame t
rigger level */ |
| 54 #define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX F
IFO before air */ |
| 55 #define MAC_DMA_FTRIG_64B 0x00000010 /* default */ |
| 56 #define MAC_DMA_FTRIG_128B 0x00000020 |
| 57 #define MAC_DMA_FTRIG_192B 0x00000030 |
| 58 #define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */ |
| 59 #define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800 |
| 60 |
| 61 #define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size
config register */ |
| 62 #define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of ze
ro-length frame */ |
| 63 #define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes
(TXCFG + RXCFG) */ |
| 64 #define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes
*/ |
| 65 #define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 byte
s */ |
| 66 #define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 byte
s */ |
| 67 #define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 byte
s */ |
| 68 #define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 byt
es */ |
| 69 #define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 byt
es */ |
| 70 #define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 byt
es */ |
| 71 |
| 72 #define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control
register */ |
| 73 #define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow
warning */ |
| 74 #define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB count
ers */ |
| 75 #define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counte
rs */ |
| 76 #define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter stro
be, increment all */ |
| 77 |
| 78 #define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout pre
scale count */ |
| 79 #define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout
prescale */ |
| 80 |
| 81 #define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame re
ceived timeout */ |
| 82 #define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no fram
e received timeout */ |
| 83 |
| 84 #define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame tr
asmitted timeout */ |
| 85 #define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no fram
e transmitted timeout */ |
| 86 #define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating
the set of QCUs */ |
| 87 /* for which frame comple
tions will cause */ |
| 88 /* a reset of the no fram
e xmit'd timeout */ |
| 89 |
| 90 #define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive fra
me gap timeout */ |
| 91 #define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive
frame gap timeout */ |
| 92 |
| 93 #define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive fra
me count limit */ |
| 94 #define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive
frame count limit */ |
| 95 |
| 96 #define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneo
us control/status register */ |
| 97 #define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA obs
ervation bus mux select */ |
| 98 #define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA ob
servation bus mux select */ |
| 99 #define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC ob
servation bus mux select */ |
| 100 #define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC o
bservation bus mux select */ |
| 101 #define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC obs
ervation bus mux select (lsb) */ |
| 102 #define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC ob
servation bus mux select (lsb) */ |
| 103 #define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC obs
ervation bus mux select (msb) */ |
| 104 #define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC ob
servation bus mux select (msb) */ |
| 105 |
| 106 |
| 107 #define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary in
terrupt status register */ |
| 108 /* |
| 109 * Interrupt Status Registers |
| 110 * |
| 111 * Only the bits in the ISR_P register and the IMR_P registers |
| 112 * control whether the MAC's INTA# output is asserted. The bits in |
| 113 * the secondary interrupt status/mask registers control what bits |
| 114 * are set in the primary interrupt status register; however the |
| 115 * IMR_S* registers DO NOT determine whether INTA# is asserted. |
| 116 * That is INTA# is asserted only when the logical AND of ISR_P |
| 117 * and IMR_P is non-zero. The secondary interrupt mask/status |
| 118 * registers affect what bits are set in ISR_P but they do not |
| 119 * directly affect whether INTA# is asserted. |
| 120 */ |
| 121 #define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one fram
e received sans errors */ |
| 122 #define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt
request */ |
| 123 #define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error int
errupt */ |
| 124 #define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received
within timeout clock */ |
| 125 #define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descript
or empty interrupt */ |
| 126 #define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO over
run interrupt */ |
| 127 #define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay int
errupt */ |
| 128 #define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrup
t request */ |
| 129 #define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error in
terrupt */ |
| 130 #define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmit
ted interrupt */ |
| 131 #define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descript
or empty interrupt */ |
| 132 #define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO und
errun interrupt */ |
| 133 #define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - s
ee MIBC */ |
| 134 #define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrup
t */ |
| 135 #define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error
interrupt */ |
| 136 #define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss in
terrupt */ |
| 137 #define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high
threshold interrupt */ |
| 138 #define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold
interrupt */ |
| 139 #define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed int
errupt */ |
| 140 #define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit
interrupt rate */ |
| 141 #define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready
interrupt */ |
| 142 #define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus
error has occurred */ |
| 143 #define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABE
ND, DTIMSYNC, BCNTO */ |
| 144 #define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive i
nterrupt rate */ |
| 145 #define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow
interrupt */ |
| 146 #define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun
interrupt */ |
| 147 #define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling tr
igger interrupt */ |
| 148 #define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt
*/ |
| 149 #define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt
*/ |
| 150 #define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completi
on mitigation interrupt */ |
| 151 #define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completio
n mitigation interrupt */ |
| 152 |
| 153 #define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary in
terrupt status register 0 */ |
| 154 #define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QC
U 0-9) */ |
| 155 #define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0 |
| 156 #define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (
QCU 0-9) */ |
| 157 #define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16 |
| 158 |
| 159 #define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary in
terrupt status register 1 */ |
| 160 #define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (Q
CU 0-9) */ |
| 161 #define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0 |
| 162 #define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (Q
CU 0-9) */ |
| 163 #define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16 |
| 164 |
| 165 #define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary
interrupt status register 2 */ |
| 166 #define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN
(QCU 0-9) */ |
| 167 #define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-
9) */ |
| 168 #define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800 |
| 169 #define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000 |
| 170 #define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000 |
| 171 #define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 |
| 172 #define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 |
| 173 #define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000 |
| 174 #define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000 |
| 175 #define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000 |
| 176 #define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 |
| 177 #define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000 |
| 178 #define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 |
| 179 #define MAC_DMA_ISR_S2_CST_MASK 0x00400000 |
| 180 #define MAC_DMA_ISR_S2_GTT_MASK 0x00800000 |
| 181 #define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */ |
| 182 #define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */ |
| 183 #define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ |
| 184 #define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ |
| 185 #define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */ |
| 186 #define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */ |
| 187 #define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ |
| 188 |
| 189 #define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary in
terrupt status register 3 */ |
| 190 #define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF
(QCU 0-9) */ |
| 191 #define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN
(QCU 0-9) */ |
| 192 |
| 193 #define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary in
terrupt status register 4 */ |
| 194 #define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (Q
CU 0-9) */ |
| 195 |
| 196 #define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary in
terrupt status register 5 */ |
| 197 #define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 |
| 198 #define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 |
| 199 #define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 |
| 200 #define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 |
| 201 #define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 |
| 202 #define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 |
| 203 #define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 |
| 204 #define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 |
| 205 #define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 |
| 206 #define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 |
| 207 #define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) |
| 208 #define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000 |
| 209 #define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 |
| 210 #define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 |
| 211 #define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 |
| 212 #define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 |
| 213 #define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 |
| 214 #define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000 |
| 215 #define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 |
| 216 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 |
| 217 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 |
| 218 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) |
| 219 |
| 220 #define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary inte
rrupt mask register */ |
| 221 /* |
| 222 * Interrupt Mask Registers |
| 223 * |
| 224 * Only the bits in the IMR control whether the MAC's INTA# |
| 225 * output will be asserted. The bits in the secondary interrupt |
| 226 * mask registers control what bits get set in the primary |
| 227 * interrupt status register; however the IMR_S* registers |
| 228 * DO NOT determine whether INTA# is asserted. |
| 229 */ |
| 230 #define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one fram
e received sans errors */ |
| 231 #define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt
request */ |
| 232 #define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error int
errupt */ |
| 233 #define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received
within timeout clock */ |
| 234 #define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descript
or empty interrupt */ |
| 235 #define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO over
run interrupt */ |
| 236 #define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay int
errupt */ |
| 237 #define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrup
t request */ |
| 238 #define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error in
terrupt */ |
| 239 #define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmit
ted interrupt */ |
| 240 #define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descript
or empty interrupt */ |
| 241 #define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO und
errun interrupt */ |
| 242 #define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - s
ee MIBC */ |
| 243 #define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrup
t */ |
| 244 #define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error
interrupt */ |
| 245 #define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss in
terrupt */ |
| 246 #define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi th
reshold interrupt */ |
| 247 #define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo th
reshold interrupt */ |
| 248 #define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed int
errupt */ |
| 249 #define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit
interrupt rate */ |
| 250 #define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */ |
| 251 #define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus
error has occurred */ |
| 252 #define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */ |
| 253 #define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive i
nterrupt rate */ |
| 254 #define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow
interrupt */ |
| 255 #define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun
interrupt */ |
| 256 #define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling tr
igger interrupt */ |
| 257 #define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt
*/ |
| 258 #define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/ |
| 259 #define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completi
on mitigation interrupt */ |
| 260 #define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completio
n mitigation interrupt */ |
| 261 |
| 262 #define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary in
terrupt mask register 0 */ |
| 263 #define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */ |
| 264 #define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0 |
| 265 #define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9)
*/ |
| 266 #define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16 |
| 267 |
| 268 #define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary in
terrupt mask register 1 */ |
| 269 #define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) *
/ |
| 270 #define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0 |
| 271 #define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) *
/ |
| 272 #define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16 |
| 273 |
| 274 #define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary
interrupt mask register 2 */ |
| 275 #define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN
(QCU 0-9) */ |
| 276 #define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0 |
| 277 #define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800 |
| 278 #define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000 |
| 279 #define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000 |
| 280 #define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 |
| 281 #define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 |
| 282 #define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000 |
| 283 #define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000 |
| 284 #define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000 |
| 285 #define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 |
| 286 #define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000 |
| 287 #define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 |
| 288 #define MAC_DMA_IMR_S2_CST_MASK 0x00400000 |
| 289 #define MAC_DMA_IMR_S2_GTT_MASK 0x00800000 |
| 290 #define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */ |
| 291 #define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */ |
| 292 #define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ |
| 293 #define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ |
| 294 #define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */ |
| 295 #define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */ |
| 296 #define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ |
| 297 |
| 298 #define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary in
terrupt mask register 3 */ |
| 299 #define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF
(QCU 0-9) */ |
| 300 #define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN
(QCU 0-9) */ |
| 301 #define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16 |
| 302 |
| 303 #define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary in
terrupt mask register 4 */ |
| 304 #define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (Q
CU 0-9) */ |
| 305 |
| 306 #define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary in
terrupt mask register 5 */ |
| 307 #define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 |
| 308 #define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 |
| 309 #define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 |
| 310 #define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 |
| 311 #define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 |
| 312 #define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 |
| 313 #define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 |
| 314 #define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 |
| 315 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 |
| 316 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 |
| 317 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i)) |
| 318 #define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000 |
| 319 #define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 |
| 320 #define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 |
| 321 #define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 |
| 322 #define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 |
| 323 #define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 |
| 324 #define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000 |
| 325 #define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 |
| 326 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 |
| 327 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 |
| 328 #define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) |
| 329 |
| 330 #define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-cle
ar access */ |
| 331 |
| 332 /* Shadow copies with read-and-clear access */ |
| 333 #define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow co
py */ |
| 334 #define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow co
py */ |
| 335 #define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow co
py */ |
| 336 #define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow co
py */ |
| 337 #define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow co
py */ |
| 338 #define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow co
py */ |
| 339 |
| 340 #define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Que
ue descriptor pointer */ |
| 341 #define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Que
ue descriptor pointer */ |
| 342 #define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Que
ue descriptor pointer */ |
| 343 #define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Que
ue descriptor pointer */ |
| 344 #define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Que
ue descriptor pointer */ |
| 345 #define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Que
ue descriptor pointer */ |
| 346 #define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Que
ue descriptor pointer */ |
| 347 #define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Que
ue descriptor pointer */ |
| 348 #define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Que
ue descriptor pointer */ |
| 349 #define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Que
ue descriptor pointer */ |
| 350 #define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i
)<<2)) |
| 351 |
| 352 #define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Que
ue enable */ |
| 353 #define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Que
ue disable */ |
| 354 /* QCU registers */ |
| 355 |
| 356 #define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configur
ation */ |
| 357 #define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configur
ation */ |
| 358 #define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configur
ation */ |
| 359 #define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configur
ation */ |
| 360 #define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configur
ation */ |
| 361 #define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configur
ation */ |
| 362 #define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configur
ation */ |
| 363 #define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configur
ation */ |
| 364 #define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configur
ation */ |
| 365 #define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configur
ation */ |
| 366 #define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_
i)<<2)) |
| 367 |
| 368 #define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR int
erval (us) */ |
| 369 #define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval
*/ |
| 370 #define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR ove
rflow threshold */ |
| 371 #define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow
thresh */ |
| 372 |
| 373 |
| 374 #define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime c
onfiguration */ |
| 375 #define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime c
onfiguration */ |
| 376 #define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime c
onfiguration */ |
| 377 #define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime c
onfiguration */ |
| 378 #define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime c
onfiguration */ |
| 379 #define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime c
onfiguration */ |
| 380 #define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime c
onfiguration */ |
| 381 #define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime c
onfiguration */ |
| 382 #define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime c
onfiguration */ |
| 383 #define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime c
onfiguration */ |
| 384 #define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS
+ ((_i)<<2)) |
| 385 |
| 386 #define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us
) */ |
| 387 #define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Inte
rval (us) */ |
| 388 #define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */ |
| 389 |
| 390 #define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm
set control */ |
| 391 #define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm
clear control */ |
| 392 |
| 393 #define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneo
us QCU settings */ |
| 394 #define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneo
us QCU settings */ |
| 395 #define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneo
us QCU settings */ |
| 396 #define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneo
us QCU settings */ |
| 397 #define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneo
us QCU settings */ |
| 398 #define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneo
us QCU settings */ |
| 399 #define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneo
us QCU settings */ |
| 400 #define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneo
us QCU settings */ |
| 401 #define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneo
us QCU settings */ |
| 402 #define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneo
us QCU settings */ |
| 403 #define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_
i)<<2)) |
| 404 |
| 405 #define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling
Policy mask */ |
| 406 #define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */ |
| 407 #define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */ |
| 408 #define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated
*/ |
| 409 #define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ |
| 410 #define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ |
| 411 #define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable *
/ |
| 412 #define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expi
red counter incr |
| 413 (empty q) */ |
| 414 #define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expi
red counter incr |
| 415 (empty beacon q) */ |
| 416 #define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indic
ation */ |
| 417 #define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired coun
ter limit enable */ |
| 418 #define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE clear
ed on ReadyTime expired or VEOL */ |
| 419 #define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expire
d counter */ |
| 420 #define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early
termination request control */ |
| 421 |
| 422 #define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneou
s QCU status */ |
| 423 #define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneou
s QCU status */ |
| 424 #define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneou
s QCU status */ |
| 425 #define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneou
s QCU status */ |
| 426 #define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneou
s QCU status */ |
| 427 #define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneou
s QCU status */ |
| 428 #define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneou
s QCU status */ |
| 429 #define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneou
s QCU status */ |
| 430 #define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneou
s QCU status */ |
| 431 #define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneou
s QCU status */ |
| 432 #define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)
<<2)) |
| 433 |
| 434 #define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending
Frame Count */ |
| 435 #define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expi
red counter */ |
| 436 |
| 437 #define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShu
tdown status */ |
| 438 |
| 439 /* DCU registers */ |
| 440 |
| 441 #define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */ |
| 442 #define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */ |
| 443 #define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */ |
| 444 #define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */ |
| 445 #define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */ |
| 446 #define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */ |
| 447 #define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */ |
| 448 #define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */ |
| 449 #define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */ |
| 450 #define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */ |
| 451 #define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + (
(_i)<<2)) |
| 452 |
| 453 #define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask
(QCU 0-9) */ |
| 454 |
| 455 #define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS
settings */ |
| 456 |
| 457 |
| 458 #define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific
IFS settings */ |
| 459 #define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific
IFS settings */ |
| 460 #define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific
IFS settings */ |
| 461 #define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific
IFS settings */ |
| 462 #define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific
IFS settings */ |
| 463 #define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific
IFS settings */ |
| 464 #define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific
IFS settings */ |
| 465 #define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific
IFS settings */ |
| 466 #define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific
IFS settings */ |
| 467 #define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific
IFS settings */ |
| 468 #define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + (
(_i)<<2)) |
| 469 #define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN *
/ |
| 470 #define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0 |
| 471 #define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX *
/ |
| 472 #define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10 |
| 473 #define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */ |
| 474 #define MAC_DMA_D_LCL_IFS_AIFS_LSB 20 |
| 475 /* |
| 476 * Note: even though this field is 8 bits wide the |
| 477 * maximum supported AIFS value is 0xFc. Setting the AIFS value |
| 478 * to 0xFd 0xFe, or 0xFf will not work correctly and will cause |
| 479 * the DCU to hang. |
| 480 */ |
| 481 #define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot i
nterval */ |
| 482 |
| 483 #define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits
*/ |
| 484 #define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits
*/ |
| 485 #define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits
*/ |
| 486 #define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits
*/ |
| 487 #define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits
*/ |
| 488 #define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits
*/ |
| 489 #define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits
*/ |
| 490 #define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits
*/ |
| 491 #define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits
*/ |
| 492 #define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits
*/ |
| 493 #define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS
+ ((_i)<<2)) |
| 494 |
| 495 #define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure
limit */ |
| 496 #define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0 |
| 497 #define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failu
re limit */ |
| 498 #define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8 |
| 499 #define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short ret
ry limit */ |
| 500 #define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14 |
| 501 |
| 502 #define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS
setting */ |
| 503 |
| 504 #define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime
settings */ |
| 505 #define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime
settings */ |
| 506 #define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime
settings */ |
| 507 #define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime
settings */ |
| 508 #define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime
settings */ |
| 509 #define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime
settings */ |
| 510 #define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime
settings */ |
| 511 #define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime
settings */ |
| 512 #define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime
settings */ |
| 513 #define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime
settings */ |
| 514 #define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + (
(_i)<<2)) |
| 515 |
| 516 #define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime durat
ion (us) */ |
| 517 #define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime dura
tion */ |
| 518 #define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enabl
e */ |
| 519 |
| 520 #define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc.
IFS settings */ |
| 521 #define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice sele
ct */ |
| 522 #define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indi
cation */ |
| 523 #define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter de
lay */ |
| 524 #define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000 |
| 525 |
| 526 #define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneou
s DCU-specific settings */ |
| 527 #define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneou
s DCU-specific settings */ |
| 528 #define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneou
s DCU-specific settings */ |
| 529 #define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneou
s DCU-specific settings */ |
| 530 #define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneou
s DCU-specific settings */ |
| 531 #define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneou
s DCU-specific settings */ |
| 532 #define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneou
s DCU-specific settings */ |
| 533 #define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneou
s DCU-specific settings */ |
| 534 #define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneou
s DCU-specific settings */ |
| 535 #define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneou
s DCU-specific settings */ |
| 536 #define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i
)<<2)) |
| 537 |
| 538 #define MAC_DMA_D0_EOL_ADDRESS 0x00001180 |
| 539 #define MAC_DMA_D1_EOL_ADDRESS 0x00001184 |
| 540 #define MAC_DMA_D2_EOL_ADDRESS 0x00001188 |
| 541 #define MAC_DMA_D3_EOL_ADDRESS 0x0000118C |
| 542 #define MAC_DMA_D4_EOL_ADDRESS 0x00001190 |
| 543 #define MAC_DMA_D5_EOL_ADDRESS 0x00001194 |
| 544 #define MAC_DMA_D6_EOL_ADDRESS 0x00001198 |
| 545 #define MAC_DMA_D7_EOL_ADDRESS 0x0000119C |
| 546 #define MAC_DMA_D8_EOL_ADDRESS 0x00001200 |
| 547 #define MAC_DMA_D9_EOL_ADDRESS 0x00001204 |
| 548 #define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<
<2)) |
| 549 |
| 550 #define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold
*/ |
| 551 #define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0 |
| 552 #define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmissi
on series |
| 553 station RTS/data failu
re |
| 554 count reset policy */ |
| 555 #define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmissi
on series |
| 556 CW reset policy */ |
| 557 #define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvat
ion Policy */ |
| 558 |
| 559 #define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a
frag burst */ |
| 560 #define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable *
/ |
| 561 #define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persisten
ce factor |
| 562 setting */ |
| 563 #define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual
collision |
| 564 handling policy */ |
| 565 #define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14 |
| 566 #define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ |
| 567 #define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ |
| 568 #define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indic
ation */ |
| 569 #define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbite
r lockout control */ |
| 570 #define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17 |
| 571 #define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/ |
| 572 #define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/ |
| 573 #define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ |
| 574 #define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockou
t ignore control */ |
| 575 #define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number in
crement disable */ |
| 576 #define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff
disable */ |
| 577 #define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. hand
ling policy */ |
| 578 #define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling
policy */ |
| 579 |
| 580 #define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequenc
e number */ |
| 581 |
| 582 |
| 583 |
| 584 #define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame pr
efetch settings */ |
| 585 #define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit
pause control/status */ |
| 586 |
| 587 #endif /* _AR6000_DMMAEG_H_ */ |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 646055:
Atheros AR600x driver + build glue (Closed)
