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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _EFUSE_REG_REG_H_ |
| 21 #define _EFUSE_REG_REG_H_ |
| 22 |
| 23 #define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 |
| 24 #define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 |
| 25 #define EFUSE_WR_ENABLE_REG_V_MSB 0 |
| 26 #define EFUSE_WR_ENABLE_REG_V_LSB 0 |
| 27 #define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 |
| 28 #define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_M
ASK) >> EFUSE_WR_ENABLE_REG_V_LSB) |
| 29 #define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_
LSB) & EFUSE_WR_ENABLE_REG_V_MASK) |
| 30 |
| 31 #define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 |
| 32 #define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 |
| 33 #define EFUSE_INT_ENABLE_REG_V_MSB 0 |
| 34 #define EFUSE_INT_ENABLE_REG_V_LSB 0 |
| 35 #define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 |
| 36 #define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_
MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) |
| 37 #define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V
_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) |
| 38 |
| 39 #define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 |
| 40 #define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 |
| 41 #define EFUSE_INT_STATUS_REG_V_MSB 0 |
| 42 #define EFUSE_INT_STATUS_REG_V_LSB 0 |
| 43 #define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 |
| 44 #define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_
MASK) >> EFUSE_INT_STATUS_REG_V_LSB) |
| 45 #define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V
_LSB) & EFUSE_INT_STATUS_REG_V_MASK) |
| 46 |
| 47 #define BITMASK_WR_REG_ADDRESS 0x0000000c |
| 48 #define BITMASK_WR_REG_OFFSET 0x0000000c |
| 49 #define BITMASK_WR_REG_V_MSB 31 |
| 50 #define BITMASK_WR_REG_V_LSB 0 |
| 51 #define BITMASK_WR_REG_V_MASK 0xffffffff |
| 52 #define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK)
>> BITMASK_WR_REG_V_LSB) |
| 53 #define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB)
& BITMASK_WR_REG_V_MASK) |
| 54 |
| 55 #define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 |
| 56 #define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 |
| 57 #define VDDQ_SETTLE_TIME_REG_V_MSB 31 |
| 58 #define VDDQ_SETTLE_TIME_REG_V_LSB 0 |
| 59 #define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff |
| 60 #define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_
MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) |
| 61 #define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V
_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) |
| 62 |
| 63 #define RD_STROBE_PW_REG_ADDRESS 0x00000014 |
| 64 #define RD_STROBE_PW_REG_OFFSET 0x00000014 |
| 65 #define RD_STROBE_PW_REG_V_MSB 31 |
| 66 #define RD_STROBE_PW_REG_V_LSB 0 |
| 67 #define RD_STROBE_PW_REG_V_MASK 0xffffffff |
| 68 #define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK
) >> RD_STROBE_PW_REG_V_LSB) |
| 69 #define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB
) & RD_STROBE_PW_REG_V_MASK) |
| 70 |
| 71 #define PG_STROBE_PW_REG_ADDRESS 0x00000018 |
| 72 #define PG_STROBE_PW_REG_OFFSET 0x00000018 |
| 73 #define PG_STROBE_PW_REG_V_MSB 31 |
| 74 #define PG_STROBE_PW_REG_V_LSB 0 |
| 75 #define PG_STROBE_PW_REG_V_MASK 0xffffffff |
| 76 #define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK
) >> PG_STROBE_PW_REG_V_LSB) |
| 77 #define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB
) & PG_STROBE_PW_REG_V_MASK) |
| 78 |
| 79 #define EFUSE_INTF_ADDRESS 0x00000800 |
| 80 #define EFUSE_INTF_OFFSET 0x00000800 |
| 81 #define EFUSE_INTF_R_MSB 31 |
| 82 #define EFUSE_INTF_R_LSB 0 |
| 83 #define EFUSE_INTF_R_MASK 0xffffffff |
| 84 #define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> E
FUSE_INTF_R_LSB) |
| 85 #define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EF
USE_INTF_R_MASK) |
| 86 |
| 87 |
| 88 #ifndef __ASSEMBLER__ |
| 89 |
| 90 typedef struct efuse_reg_reg_s { |
| 91 volatile unsigned int efuse_wr_enable_reg; |
| 92 volatile unsigned int efuse_int_enable_reg; |
| 93 volatile unsigned int efuse_int_status_reg; |
| 94 volatile unsigned int bitmask_wr_reg; |
| 95 volatile unsigned int vddq_settle_time_reg; |
| 96 volatile unsigned int rd_strobe_pw_reg; |
| 97 volatile unsigned int pg_strobe_pw_reg; |
| 98 unsigned char pad0[2020]; /* pad to 0x800 */ |
| 99 volatile unsigned int efuse_intf[512]; |
| 100 } efuse_reg_reg_t; |
| 101 |
| 102 #endif /* __ASSEMBLER__ */ |
| 103 |
| 104 #endif /* _EFUSE_REG_H_ */ |
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