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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _UART_REG_REG_H_ |
| 21 #define _UART_REG_REG_H_ |
| 22 |
| 23 #define RBR_ADDRESS 0x00000000 |
| 24 #define RBR_OFFSET 0x00000000 |
| 25 #define RBR_RBR_MSB 7 |
| 26 #define RBR_RBR_LSB 0 |
| 27 #define RBR_RBR_MASK 0x000000ff |
| 28 #define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RB
R_LSB) |
| 29 #define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR
_MASK) |
| 30 |
| 31 #define THR_ADDRESS 0x00000000 |
| 32 #define THR_OFFSET 0x00000000 |
| 33 #define THR_THR_MSB 7 |
| 34 #define THR_THR_LSB 0 |
| 35 #define THR_THR_MASK 0x000000ff |
| 36 #define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_TH
R_LSB) |
| 37 #define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR
_MASK) |
| 38 |
| 39 #define DLL_ADDRESS 0x00000000 |
| 40 #define DLL_OFFSET 0x00000000 |
| 41 #define DLL_DLL_MSB 7 |
| 42 #define DLL_DLL_LSB 0 |
| 43 #define DLL_DLL_MASK 0x000000ff |
| 44 #define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DL
L_LSB) |
| 45 #define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL
_MASK) |
| 46 |
| 47 #define DLH_ADDRESS 0x00000004 |
| 48 #define DLH_OFFSET 0x00000004 |
| 49 #define DLH_DLH_MSB 7 |
| 50 #define DLH_DLH_LSB 0 |
| 51 #define DLH_DLH_MASK 0x000000ff |
| 52 #define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DL
H_LSB) |
| 53 #define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH
_MASK) |
| 54 |
| 55 #define IER_ADDRESS 0x00000004 |
| 56 #define IER_OFFSET 0x00000004 |
| 57 #define IER_EDDSI_MSB 3 |
| 58 #define IER_EDDSI_LSB 3 |
| 59 #define IER_EDDSI_MASK 0x00000008 |
| 60 #define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_
EDDSI_LSB) |
| 61 #define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_E
DDSI_MASK) |
| 62 #define IER_ELSI_MSB 2 |
| 63 #define IER_ELSI_LSB 2 |
| 64 #define IER_ELSI_MASK 0x00000004 |
| 65 #define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_E
LSI_LSB) |
| 66 #define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_EL
SI_MASK) |
| 67 #define IER_ETBEI_MSB 1 |
| 68 #define IER_ETBEI_LSB 1 |
| 69 #define IER_ETBEI_MASK 0x00000002 |
| 70 #define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_
ETBEI_LSB) |
| 71 #define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_E
TBEI_MASK) |
| 72 #define IER_ERBFI_MSB 0 |
| 73 #define IER_ERBFI_LSB 0 |
| 74 #define IER_ERBFI_MASK 0x00000001 |
| 75 #define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_
ERBFI_LSB) |
| 76 #define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_E
RBFI_MASK) |
| 77 |
| 78 #define IIR_ADDRESS 0x00000008 |
| 79 #define IIR_OFFSET 0x00000008 |
| 80 #define IIR_FIFO_STATUS_MSB 7 |
| 81 #define IIR_FIFO_STATUS_LSB 6 |
| 82 #define IIR_FIFO_STATUS_MASK 0x000000c0 |
| 83 #define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >
> IIR_FIFO_STATUS_LSB) |
| 84 #define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) &
IIR_FIFO_STATUS_MASK) |
| 85 #define IIR_IID_MSB 3 |
| 86 #define IIR_IID_LSB 0 |
| 87 #define IIR_IID_MASK 0x0000000f |
| 88 #define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_II
D_LSB) |
| 89 #define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID
_MASK) |
| 90 |
| 91 #define FCR_ADDRESS 0x00000008 |
| 92 #define FCR_OFFSET 0x00000008 |
| 93 #define FCR_RCVR_TRIG_MSB 7 |
| 94 #define FCR_RCVR_TRIG_LSB 6 |
| 95 #define FCR_RCVR_TRIG_MASK 0x000000c0 |
| 96 #define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >>
FCR_RCVR_TRIG_LSB) |
| 97 #define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & F
CR_RCVR_TRIG_MASK) |
| 98 #define FCR_DMA_MODE_MSB 3 |
| 99 #define FCR_DMA_MODE_LSB 3 |
| 100 #define FCR_DMA_MODE_MASK 0x00000008 |
| 101 #define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> F
CR_DMA_MODE_LSB) |
| 102 #define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FC
R_DMA_MODE_MASK) |
| 103 #define FCR_XMIT_FIFO_RST_MSB 2 |
| 104 #define FCR_XMIT_FIFO_RST_LSB 2 |
| 105 #define FCR_XMIT_FIFO_RST_MASK 0x00000004 |
| 106 #define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK)
>> FCR_XMIT_FIFO_RST_LSB) |
| 107 #define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB)
& FCR_XMIT_FIFO_RST_MASK) |
| 108 #define FCR_RCVR_FIFO_RST_MSB 1 |
| 109 #define FCR_RCVR_FIFO_RST_LSB 1 |
| 110 #define FCR_RCVR_FIFO_RST_MASK 0x00000002 |
| 111 #define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK)
>> FCR_RCVR_FIFO_RST_LSB) |
| 112 #define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB)
& FCR_RCVR_FIFO_RST_MASK) |
| 113 #define FCR_FIFO_EN_MSB 0 |
| 114 #define FCR_FIFO_EN_LSB 0 |
| 115 #define FCR_FIFO_EN_MASK 0x00000001 |
| 116 #define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FC
R_FIFO_EN_LSB) |
| 117 #define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR
_FIFO_EN_MASK) |
| 118 |
| 119 #define LCR_ADDRESS 0x0000000c |
| 120 #define LCR_OFFSET 0x0000000c |
| 121 #define LCR_DLAB_MSB 7 |
| 122 #define LCR_DLAB_LSB 7 |
| 123 #define LCR_DLAB_MASK 0x00000080 |
| 124 #define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_D
LAB_LSB) |
| 125 #define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DL
AB_MASK) |
| 126 #define LCR_BREAK_MSB 6 |
| 127 #define LCR_BREAK_LSB 6 |
| 128 #define LCR_BREAK_MASK 0x00000040 |
| 129 #define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_
BREAK_LSB) |
| 130 #define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_B
REAK_MASK) |
| 131 #define LCR_EPS_MSB 4 |
| 132 #define LCR_EPS_LSB 4 |
| 133 #define LCR_EPS_MASK 0x00000010 |
| 134 #define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EP
S_LSB) |
| 135 #define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS
_MASK) |
| 136 #define LCR_PEN_MSB 3 |
| 137 #define LCR_PEN_LSB 3 |
| 138 #define LCR_PEN_MASK 0x00000008 |
| 139 #define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PE
N_LSB) |
| 140 #define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN
_MASK) |
| 141 #define LCR_STOP_MSB 2 |
| 142 #define LCR_STOP_LSB 2 |
| 143 #define LCR_STOP_MASK 0x00000004 |
| 144 #define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_S
TOP_LSB) |
| 145 #define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_ST
OP_MASK) |
| 146 #define LCR_CLS_MSB 1 |
| 147 #define LCR_CLS_LSB 0 |
| 148 #define LCR_CLS_MASK 0x00000003 |
| 149 #define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CL
S_LSB) |
| 150 #define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS
_MASK) |
| 151 |
| 152 #define MCR_ADDRESS 0x00000010 |
| 153 #define MCR_OFFSET 0x00000010 |
| 154 #define MCR_LOOPBACK_MSB 5 |
| 155 #define MCR_LOOPBACK_LSB 5 |
| 156 #define MCR_LOOPBACK_MASK 0x00000020 |
| 157 #define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> M
CR_LOOPBACK_LSB) |
| 158 #define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MC
R_LOOPBACK_MASK) |
| 159 #define MCR_OUT2_MSB 3 |
| 160 #define MCR_OUT2_LSB 3 |
| 161 #define MCR_OUT2_MASK 0x00000008 |
| 162 #define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_O
UT2_LSB) |
| 163 #define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OU
T2_MASK) |
| 164 #define MCR_OUT1_MSB 2 |
| 165 #define MCR_OUT1_LSB 2 |
| 166 #define MCR_OUT1_MASK 0x00000004 |
| 167 #define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_O
UT1_LSB) |
| 168 #define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OU
T1_MASK) |
| 169 #define MCR_RTS_MSB 1 |
| 170 #define MCR_RTS_LSB 1 |
| 171 #define MCR_RTS_MASK 0x00000002 |
| 172 #define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RT
S_LSB) |
| 173 #define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS
_MASK) |
| 174 #define MCR_DTR_MSB 0 |
| 175 #define MCR_DTR_LSB 0 |
| 176 #define MCR_DTR_MASK 0x00000001 |
| 177 #define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DT
R_LSB) |
| 178 #define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR
_MASK) |
| 179 |
| 180 #define LSR_ADDRESS 0x00000014 |
| 181 #define LSR_OFFSET 0x00000014 |
| 182 #define LSR_FERR_MSB 7 |
| 183 #define LSR_FERR_LSB 7 |
| 184 #define LSR_FERR_MASK 0x00000080 |
| 185 #define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_F
ERR_LSB) |
| 186 #define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FE
RR_MASK) |
| 187 #define LSR_TEMT_MSB 6 |
| 188 #define LSR_TEMT_LSB 6 |
| 189 #define LSR_TEMT_MASK 0x00000040 |
| 190 #define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_T
EMT_LSB) |
| 191 #define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TE
MT_MASK) |
| 192 #define LSR_THRE_MSB 5 |
| 193 #define LSR_THRE_LSB 5 |
| 194 #define LSR_THRE_MASK 0x00000020 |
| 195 #define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_T
HRE_LSB) |
| 196 #define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_TH
RE_MASK) |
| 197 #define LSR_BI_MSB 4 |
| 198 #define LSR_BI_LSB 4 |
| 199 #define LSR_BI_MASK 0x00000010 |
| 200 #define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_
LSB) |
| 201 #define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_M
ASK) |
| 202 #define LSR_FE_MSB 3 |
| 203 #define LSR_FE_LSB 3 |
| 204 #define LSR_FE_MASK 0x00000008 |
| 205 #define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_
LSB) |
| 206 #define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_M
ASK) |
| 207 #define LSR_PE_MSB 2 |
| 208 #define LSR_PE_LSB 2 |
| 209 #define LSR_PE_MASK 0x00000004 |
| 210 #define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_
LSB) |
| 211 #define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_M
ASK) |
| 212 #define LSR_OE_MSB 1 |
| 213 #define LSR_OE_LSB 1 |
| 214 #define LSR_OE_MASK 0x00000002 |
| 215 #define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_
LSB) |
| 216 #define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_M
ASK) |
| 217 #define LSR_DR_MSB 0 |
| 218 #define LSR_DR_LSB 0 |
| 219 #define LSR_DR_MASK 0x00000001 |
| 220 #define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_
LSB) |
| 221 #define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_M
ASK) |
| 222 |
| 223 #define MSR_ADDRESS 0x00000018 |
| 224 #define MSR_OFFSET 0x00000018 |
| 225 #define MSR_DCD_MSB 7 |
| 226 #define MSR_DCD_LSB 7 |
| 227 #define MSR_DCD_MASK 0x00000080 |
| 228 #define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DC
D_LSB) |
| 229 #define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD
_MASK) |
| 230 #define MSR_RI_MSB 6 |
| 231 #define MSR_RI_LSB 6 |
| 232 #define MSR_RI_MASK 0x00000040 |
| 233 #define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_
LSB) |
| 234 #define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_M
ASK) |
| 235 #define MSR_DSR_MSB 5 |
| 236 #define MSR_DSR_LSB 5 |
| 237 #define MSR_DSR_MASK 0x00000020 |
| 238 #define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DS
R_LSB) |
| 239 #define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR
_MASK) |
| 240 #define MSR_CTS_MSB 4 |
| 241 #define MSR_CTS_LSB 4 |
| 242 #define MSR_CTS_MASK 0x00000010 |
| 243 #define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CT
S_LSB) |
| 244 #define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS
_MASK) |
| 245 #define MSR_DDCD_MSB 3 |
| 246 #define MSR_DDCD_LSB 3 |
| 247 #define MSR_DDCD_MASK 0x00000008 |
| 248 #define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_D
DCD_LSB) |
| 249 #define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DD
CD_MASK) |
| 250 #define MSR_TERI_MSB 2 |
| 251 #define MSR_TERI_LSB 2 |
| 252 #define MSR_TERI_MASK 0x00000004 |
| 253 #define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_T
ERI_LSB) |
| 254 #define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TE
RI_MASK) |
| 255 #define MSR_DDSR_MSB 1 |
| 256 #define MSR_DDSR_LSB 1 |
| 257 #define MSR_DDSR_MASK 0x00000002 |
| 258 #define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_D
DSR_LSB) |
| 259 #define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DD
SR_MASK) |
| 260 #define MSR_DCTS_MSB 0 |
| 261 #define MSR_DCTS_LSB 0 |
| 262 #define MSR_DCTS_MASK 0x00000001 |
| 263 #define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_D
CTS_LSB) |
| 264 #define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DC
TS_MASK) |
| 265 |
| 266 #define SCR_ADDRESS 0x0000001c |
| 267 #define SCR_OFFSET 0x0000001c |
| 268 #define SCR_SCR_MSB 7 |
| 269 #define SCR_SCR_LSB 0 |
| 270 #define SCR_SCR_MASK 0x000000ff |
| 271 #define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SC
R_LSB) |
| 272 #define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR
_MASK) |
| 273 |
| 274 #define SRBR_ADDRESS 0x00000020 |
| 275 #define SRBR_OFFSET 0x00000020 |
| 276 #define SRBR_SRBR_MSB 7 |
| 277 #define SRBR_SRBR_LSB 0 |
| 278 #define SRBR_SRBR_MASK 0x000000ff |
| 279 #define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR
_SRBR_LSB) |
| 280 #define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_
SRBR_MASK) |
| 281 |
| 282 #define SIIR_ADDRESS 0x00000028 |
| 283 #define SIIR_OFFSET 0x00000028 |
| 284 #define SIIR_SIIR_MSB 7 |
| 285 #define SIIR_SIIR_LSB 0 |
| 286 #define SIIR_SIIR_MASK 0x000000ff |
| 287 #define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR
_SIIR_LSB) |
| 288 #define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_
SIIR_MASK) |
| 289 |
| 290 #define MWR_ADDRESS 0x0000002c |
| 291 #define MWR_OFFSET 0x0000002c |
| 292 #define MWR_MWR_MSB 31 |
| 293 #define MWR_MWR_LSB 0 |
| 294 #define MWR_MWR_MASK 0xffffffff |
| 295 #define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MW
R_LSB) |
| 296 #define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR
_MASK) |
| 297 |
| 298 #define SLSR_ADDRESS 0x00000034 |
| 299 #define SLSR_OFFSET 0x00000034 |
| 300 #define SLSR_SLSR_MSB 7 |
| 301 #define SLSR_SLSR_LSB 0 |
| 302 #define SLSR_SLSR_MASK 0x000000ff |
| 303 #define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR
_SLSR_LSB) |
| 304 #define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_
SLSR_MASK) |
| 305 |
| 306 #define SMSR_ADDRESS 0x00000038 |
| 307 #define SMSR_OFFSET 0x00000038 |
| 308 #define SMSR_SMSR_MSB 7 |
| 309 #define SMSR_SMSR_LSB 0 |
| 310 #define SMSR_SMSR_MASK 0x000000ff |
| 311 #define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR
_SMSR_LSB) |
| 312 #define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_
SMSR_MASK) |
| 313 |
| 314 #define MRR_ADDRESS 0x0000003c |
| 315 #define MRR_OFFSET 0x0000003c |
| 316 #define MRR_MRR_MSB 31 |
| 317 #define MRR_MRR_LSB 0 |
| 318 #define MRR_MRR_MASK 0xffffffff |
| 319 #define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MR
R_LSB) |
| 320 #define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR
_MASK) |
| 321 |
| 322 |
| 323 #ifndef __ASSEMBLER__ |
| 324 |
| 325 typedef struct uart_reg_reg_s { |
| 326 volatile unsigned int rbr; |
| 327 volatile unsigned int dlh; |
| 328 volatile unsigned int iir; |
| 329 volatile unsigned int lcr; |
| 330 volatile unsigned int mcr; |
| 331 volatile unsigned int lsr; |
| 332 volatile unsigned int msr; |
| 333 volatile unsigned int scr; |
| 334 volatile unsigned int srbr; |
| 335 unsigned char pad0[4]; /* pad to 0x28 */ |
| 336 volatile unsigned int siir; |
| 337 volatile unsigned int mwr; |
| 338 unsigned char pad1[4]; /* pad to 0x34 */ |
| 339 volatile unsigned int slsr; |
| 340 volatile unsigned int smsr; |
| 341 volatile unsigned int mrr; |
| 342 } uart_reg_reg_t; |
| 343 |
| 344 #endif /* __ASSEMBLER__ */ |
| 345 |
| 346 #endif /* _UART_REG_H_ */ |
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