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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _GPIO_REG_REG_H_ |
| 21 #define _GPIO_REG_REG_H_ |
| 22 |
| 23 #define GPIO_OUT_ADDRESS 0x00000000 |
| 24 #define GPIO_OUT_OFFSET 0x00000000 |
| 25 #define GPIO_OUT_DATA_MSB 17 |
| 26 #define GPIO_OUT_DATA_LSB 0 |
| 27 #define GPIO_OUT_DATA_MASK 0x0003ffff |
| 28 #define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >>
GPIO_OUT_DATA_LSB) |
| 29 #define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & G
PIO_OUT_DATA_MASK) |
| 30 |
| 31 #define GPIO_OUT_W1TS_ADDRESS 0x00000004 |
| 32 #define GPIO_OUT_W1TS_OFFSET 0x00000004 |
| 33 #define GPIO_OUT_W1TS_DATA_MSB 17 |
| 34 #define GPIO_OUT_W1TS_DATA_LSB 0 |
| 35 #define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff |
| 36 #define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK
) >> GPIO_OUT_W1TS_DATA_LSB) |
| 37 #define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB
) & GPIO_OUT_W1TS_DATA_MASK) |
| 38 |
| 39 #define GPIO_OUT_W1TC_ADDRESS 0x00000008 |
| 40 #define GPIO_OUT_W1TC_OFFSET 0x00000008 |
| 41 #define GPIO_OUT_W1TC_DATA_MSB 17 |
| 42 #define GPIO_OUT_W1TC_DATA_LSB 0 |
| 43 #define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff |
| 44 #define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK
) >> GPIO_OUT_W1TC_DATA_LSB) |
| 45 #define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB
) & GPIO_OUT_W1TC_DATA_MASK) |
| 46 |
| 47 #define GPIO_ENABLE_ADDRESS 0x0000000c |
| 48 #define GPIO_ENABLE_OFFSET 0x0000000c |
| 49 #define GPIO_ENABLE_DATA_MSB 17 |
| 50 #define GPIO_ENABLE_DATA_LSB 0 |
| 51 #define GPIO_ENABLE_DATA_MASK 0x0003ffff |
| 52 #define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK)
>> GPIO_ENABLE_DATA_LSB) |
| 53 #define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB)
& GPIO_ENABLE_DATA_MASK) |
| 54 |
| 55 #define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 |
| 56 #define GPIO_ENABLE_W1TS_OFFSET 0x00000010 |
| 57 #define GPIO_ENABLE_W1TS_DATA_MSB 17 |
| 58 #define GPIO_ENABLE_W1TS_DATA_LSB 0 |
| 59 #define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff |
| 60 #define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_M
ASK) >> GPIO_ENABLE_W1TS_DATA_LSB) |
| 61 #define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_
LSB) & GPIO_ENABLE_W1TS_DATA_MASK) |
| 62 |
| 63 #define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 |
| 64 #define GPIO_ENABLE_W1TC_OFFSET 0x00000014 |
| 65 #define GPIO_ENABLE_W1TC_DATA_MSB 17 |
| 66 #define GPIO_ENABLE_W1TC_DATA_LSB 0 |
| 67 #define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff |
| 68 #define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_M
ASK) >> GPIO_ENABLE_W1TC_DATA_LSB) |
| 69 #define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_
LSB) & GPIO_ENABLE_W1TC_DATA_MASK) |
| 70 |
| 71 #define GPIO_IN_ADDRESS 0x00000018 |
| 72 #define GPIO_IN_OFFSET 0x00000018 |
| 73 #define GPIO_IN_DATA_MSB 17 |
| 74 #define GPIO_IN_DATA_LSB 0 |
| 75 #define GPIO_IN_DATA_MASK 0x0003ffff |
| 76 #define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> G
PIO_IN_DATA_LSB) |
| 77 #define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GP
IO_IN_DATA_MASK) |
| 78 |
| 79 #define GPIO_STATUS_ADDRESS 0x0000001c |
| 80 #define GPIO_STATUS_OFFSET 0x0000001c |
| 81 #define GPIO_STATUS_INTERRUPT_MSB 17 |
| 82 #define GPIO_STATUS_INTERRUPT_LSB 0 |
| 83 #define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff |
| 84 #define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_M
ASK) >> GPIO_STATUS_INTERRUPT_LSB) |
| 85 #define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_
LSB) & GPIO_STATUS_INTERRUPT_MASK) |
| 86 |
| 87 #define GPIO_STATUS_W1TS_ADDRESS 0x00000020 |
| 88 #define GPIO_STATUS_W1TS_OFFSET 0x00000020 |
| 89 #define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 |
| 90 #define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 |
| 91 #define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff |
| 92 #define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERR
UPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) |
| 93 #define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTER
RUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) |
| 94 |
| 95 #define GPIO_STATUS_W1TC_ADDRESS 0x00000024 |
| 96 #define GPIO_STATUS_W1TC_OFFSET 0x00000024 |
| 97 #define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 |
| 98 #define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 |
| 99 #define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff |
| 100 #define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERR
UPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) |
| 101 #define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTER
RUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) |
| 102 |
| 103 #define GPIO_PIN0_ADDRESS 0x00000028 |
| 104 #define GPIO_PIN0_OFFSET 0x00000028 |
| 105 #define GPIO_PIN0_CONFIG_MSB 12 |
| 106 #define GPIO_PIN0_CONFIG_LSB 11 |
| 107 #define GPIO_PIN0_CONFIG_MASK 0x00001800 |
| 108 #define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK)
>> GPIO_PIN0_CONFIG_LSB) |
| 109 #define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB)
& GPIO_PIN0_CONFIG_MASK) |
| 110 #define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 |
| 111 #define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 |
| 112 #define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 |
| 113 #define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE
_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) |
| 114 #define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABL
E_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) |
| 115 #define GPIO_PIN0_INT_TYPE_MSB 9 |
| 116 #define GPIO_PIN0_INT_TYPE_LSB 7 |
| 117 #define GPIO_PIN0_INT_TYPE_MASK 0x00000380 |
| 118 #define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK
) >> GPIO_PIN0_INT_TYPE_LSB) |
| 119 #define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB
) & GPIO_PIN0_INT_TYPE_MASK) |
| 120 #define GPIO_PIN0_PAD_DRIVER_MSB 2 |
| 121 #define GPIO_PIN0_PAD_DRIVER_LSB 2 |
| 122 #define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 |
| 123 #define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MA
SK) >> GPIO_PIN0_PAD_DRIVER_LSB) |
| 124 #define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_L
SB) & GPIO_PIN0_PAD_DRIVER_MASK) |
| 125 #define GPIO_PIN0_SOURCE_MSB 0 |
| 126 #define GPIO_PIN0_SOURCE_LSB 0 |
| 127 #define GPIO_PIN0_SOURCE_MASK 0x00000001 |
| 128 #define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK)
>> GPIO_PIN0_SOURCE_LSB) |
| 129 #define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB)
& GPIO_PIN0_SOURCE_MASK) |
| 130 |
| 131 #define GPIO_PIN1_ADDRESS 0x0000002c |
| 132 #define GPIO_PIN1_OFFSET 0x0000002c |
| 133 #define GPIO_PIN1_CONFIG_MSB 12 |
| 134 #define GPIO_PIN1_CONFIG_LSB 11 |
| 135 #define GPIO_PIN1_CONFIG_MASK 0x00001800 |
| 136 #define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK)
>> GPIO_PIN1_CONFIG_LSB) |
| 137 #define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB)
& GPIO_PIN1_CONFIG_MASK) |
| 138 #define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 |
| 139 #define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 |
| 140 #define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 |
| 141 #define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE
_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) |
| 142 #define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABL
E_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) |
| 143 #define GPIO_PIN1_INT_TYPE_MSB 9 |
| 144 #define GPIO_PIN1_INT_TYPE_LSB 7 |
| 145 #define GPIO_PIN1_INT_TYPE_MASK 0x00000380 |
| 146 #define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK
) >> GPIO_PIN1_INT_TYPE_LSB) |
| 147 #define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB
) & GPIO_PIN1_INT_TYPE_MASK) |
| 148 #define GPIO_PIN1_PAD_DRIVER_MSB 2 |
| 149 #define GPIO_PIN1_PAD_DRIVER_LSB 2 |
| 150 #define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 |
| 151 #define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MA
SK) >> GPIO_PIN1_PAD_DRIVER_LSB) |
| 152 #define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_L
SB) & GPIO_PIN1_PAD_DRIVER_MASK) |
| 153 #define GPIO_PIN1_SOURCE_MSB 0 |
| 154 #define GPIO_PIN1_SOURCE_LSB 0 |
| 155 #define GPIO_PIN1_SOURCE_MASK 0x00000001 |
| 156 #define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK)
>> GPIO_PIN1_SOURCE_LSB) |
| 157 #define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB)
& GPIO_PIN1_SOURCE_MASK) |
| 158 |
| 159 #define GPIO_PIN2_ADDRESS 0x00000030 |
| 160 #define GPIO_PIN2_OFFSET 0x00000030 |
| 161 #define GPIO_PIN2_CONFIG_MSB 12 |
| 162 #define GPIO_PIN2_CONFIG_LSB 11 |
| 163 #define GPIO_PIN2_CONFIG_MASK 0x00001800 |
| 164 #define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK)
>> GPIO_PIN2_CONFIG_LSB) |
| 165 #define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB)
& GPIO_PIN2_CONFIG_MASK) |
| 166 #define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 |
| 167 #define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 |
| 168 #define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 |
| 169 #define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE
_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) |
| 170 #define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABL
E_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) |
| 171 #define GPIO_PIN2_INT_TYPE_MSB 9 |
| 172 #define GPIO_PIN2_INT_TYPE_LSB 7 |
| 173 #define GPIO_PIN2_INT_TYPE_MASK 0x00000380 |
| 174 #define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK
) >> GPIO_PIN2_INT_TYPE_LSB) |
| 175 #define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB
) & GPIO_PIN2_INT_TYPE_MASK) |
| 176 #define GPIO_PIN2_PAD_DRIVER_MSB 2 |
| 177 #define GPIO_PIN2_PAD_DRIVER_LSB 2 |
| 178 #define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 |
| 179 #define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MA
SK) >> GPIO_PIN2_PAD_DRIVER_LSB) |
| 180 #define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_L
SB) & GPIO_PIN2_PAD_DRIVER_MASK) |
| 181 #define GPIO_PIN2_SOURCE_MSB 0 |
| 182 #define GPIO_PIN2_SOURCE_LSB 0 |
| 183 #define GPIO_PIN2_SOURCE_MASK 0x00000001 |
| 184 #define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK)
>> GPIO_PIN2_SOURCE_LSB) |
| 185 #define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB)
& GPIO_PIN2_SOURCE_MASK) |
| 186 |
| 187 #define GPIO_PIN3_ADDRESS 0x00000034 |
| 188 #define GPIO_PIN3_OFFSET 0x00000034 |
| 189 #define GPIO_PIN3_CONFIG_MSB 12 |
| 190 #define GPIO_PIN3_CONFIG_LSB 11 |
| 191 #define GPIO_PIN3_CONFIG_MASK 0x00001800 |
| 192 #define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK)
>> GPIO_PIN3_CONFIG_LSB) |
| 193 #define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB)
& GPIO_PIN3_CONFIG_MASK) |
| 194 #define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 |
| 195 #define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 |
| 196 #define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 |
| 197 #define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE
_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) |
| 198 #define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABL
E_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) |
| 199 #define GPIO_PIN3_INT_TYPE_MSB 9 |
| 200 #define GPIO_PIN3_INT_TYPE_LSB 7 |
| 201 #define GPIO_PIN3_INT_TYPE_MASK 0x00000380 |
| 202 #define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK
) >> GPIO_PIN3_INT_TYPE_LSB) |
| 203 #define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB
) & GPIO_PIN3_INT_TYPE_MASK) |
| 204 #define GPIO_PIN3_PAD_DRIVER_MSB 2 |
| 205 #define GPIO_PIN3_PAD_DRIVER_LSB 2 |
| 206 #define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 |
| 207 #define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MA
SK) >> GPIO_PIN3_PAD_DRIVER_LSB) |
| 208 #define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_L
SB) & GPIO_PIN3_PAD_DRIVER_MASK) |
| 209 #define GPIO_PIN3_SOURCE_MSB 0 |
| 210 #define GPIO_PIN3_SOURCE_LSB 0 |
| 211 #define GPIO_PIN3_SOURCE_MASK 0x00000001 |
| 212 #define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK)
>> GPIO_PIN3_SOURCE_LSB) |
| 213 #define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB)
& GPIO_PIN3_SOURCE_MASK) |
| 214 |
| 215 #define GPIO_PIN4_ADDRESS 0x00000038 |
| 216 #define GPIO_PIN4_OFFSET 0x00000038 |
| 217 #define GPIO_PIN4_CONFIG_MSB 12 |
| 218 #define GPIO_PIN4_CONFIG_LSB 11 |
| 219 #define GPIO_PIN4_CONFIG_MASK 0x00001800 |
| 220 #define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK)
>> GPIO_PIN4_CONFIG_LSB) |
| 221 #define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB)
& GPIO_PIN4_CONFIG_MASK) |
| 222 #define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 |
| 223 #define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 |
| 224 #define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 |
| 225 #define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE
_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) |
| 226 #define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABL
E_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) |
| 227 #define GPIO_PIN4_INT_TYPE_MSB 9 |
| 228 #define GPIO_PIN4_INT_TYPE_LSB 7 |
| 229 #define GPIO_PIN4_INT_TYPE_MASK 0x00000380 |
| 230 #define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK
) >> GPIO_PIN4_INT_TYPE_LSB) |
| 231 #define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB
) & GPIO_PIN4_INT_TYPE_MASK) |
| 232 #define GPIO_PIN4_PAD_DRIVER_MSB 2 |
| 233 #define GPIO_PIN4_PAD_DRIVER_LSB 2 |
| 234 #define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 |
| 235 #define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MA
SK) >> GPIO_PIN4_PAD_DRIVER_LSB) |
| 236 #define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_L
SB) & GPIO_PIN4_PAD_DRIVER_MASK) |
| 237 #define GPIO_PIN4_SOURCE_MSB 0 |
| 238 #define GPIO_PIN4_SOURCE_LSB 0 |
| 239 #define GPIO_PIN4_SOURCE_MASK 0x00000001 |
| 240 #define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK)
>> GPIO_PIN4_SOURCE_LSB) |
| 241 #define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB)
& GPIO_PIN4_SOURCE_MASK) |
| 242 |
| 243 #define GPIO_PIN5_ADDRESS 0x0000003c |
| 244 #define GPIO_PIN5_OFFSET 0x0000003c |
| 245 #define GPIO_PIN5_CONFIG_MSB 12 |
| 246 #define GPIO_PIN5_CONFIG_LSB 11 |
| 247 #define GPIO_PIN5_CONFIG_MASK 0x00001800 |
| 248 #define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK)
>> GPIO_PIN5_CONFIG_LSB) |
| 249 #define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB)
& GPIO_PIN5_CONFIG_MASK) |
| 250 #define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 |
| 251 #define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 |
| 252 #define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 |
| 253 #define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE
_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) |
| 254 #define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABL
E_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) |
| 255 #define GPIO_PIN5_INT_TYPE_MSB 9 |
| 256 #define GPIO_PIN5_INT_TYPE_LSB 7 |
| 257 #define GPIO_PIN5_INT_TYPE_MASK 0x00000380 |
| 258 #define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK
) >> GPIO_PIN5_INT_TYPE_LSB) |
| 259 #define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB
) & GPIO_PIN5_INT_TYPE_MASK) |
| 260 #define GPIO_PIN5_PAD_DRIVER_MSB 2 |
| 261 #define GPIO_PIN5_PAD_DRIVER_LSB 2 |
| 262 #define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 |
| 263 #define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MA
SK) >> GPIO_PIN5_PAD_DRIVER_LSB) |
| 264 #define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_L
SB) & GPIO_PIN5_PAD_DRIVER_MASK) |
| 265 #define GPIO_PIN5_SOURCE_MSB 0 |
| 266 #define GPIO_PIN5_SOURCE_LSB 0 |
| 267 #define GPIO_PIN5_SOURCE_MASK 0x00000001 |
| 268 #define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK)
>> GPIO_PIN5_SOURCE_LSB) |
| 269 #define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB)
& GPIO_PIN5_SOURCE_MASK) |
| 270 |
| 271 #define GPIO_PIN6_ADDRESS 0x00000040 |
| 272 #define GPIO_PIN6_OFFSET 0x00000040 |
| 273 #define GPIO_PIN6_CONFIG_MSB 12 |
| 274 #define GPIO_PIN6_CONFIG_LSB 11 |
| 275 #define GPIO_PIN6_CONFIG_MASK 0x00001800 |
| 276 #define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK)
>> GPIO_PIN6_CONFIG_LSB) |
| 277 #define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB)
& GPIO_PIN6_CONFIG_MASK) |
| 278 #define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 |
| 279 #define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 |
| 280 #define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 |
| 281 #define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE
_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) |
| 282 #define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABL
E_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) |
| 283 #define GPIO_PIN6_INT_TYPE_MSB 9 |
| 284 #define GPIO_PIN6_INT_TYPE_LSB 7 |
| 285 #define GPIO_PIN6_INT_TYPE_MASK 0x00000380 |
| 286 #define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK
) >> GPIO_PIN6_INT_TYPE_LSB) |
| 287 #define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB
) & GPIO_PIN6_INT_TYPE_MASK) |
| 288 #define GPIO_PIN6_PAD_DRIVER_MSB 2 |
| 289 #define GPIO_PIN6_PAD_DRIVER_LSB 2 |
| 290 #define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 |
| 291 #define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MA
SK) >> GPIO_PIN6_PAD_DRIVER_LSB) |
| 292 #define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_L
SB) & GPIO_PIN6_PAD_DRIVER_MASK) |
| 293 #define GPIO_PIN6_SOURCE_MSB 0 |
| 294 #define GPIO_PIN6_SOURCE_LSB 0 |
| 295 #define GPIO_PIN6_SOURCE_MASK 0x00000001 |
| 296 #define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK)
>> GPIO_PIN6_SOURCE_LSB) |
| 297 #define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB)
& GPIO_PIN6_SOURCE_MASK) |
| 298 |
| 299 #define GPIO_PIN7_ADDRESS 0x00000044 |
| 300 #define GPIO_PIN7_OFFSET 0x00000044 |
| 301 #define GPIO_PIN7_CONFIG_MSB 12 |
| 302 #define GPIO_PIN7_CONFIG_LSB 11 |
| 303 #define GPIO_PIN7_CONFIG_MASK 0x00001800 |
| 304 #define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK)
>> GPIO_PIN7_CONFIG_LSB) |
| 305 #define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB)
& GPIO_PIN7_CONFIG_MASK) |
| 306 #define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 |
| 307 #define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 |
| 308 #define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 |
| 309 #define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE
_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) |
| 310 #define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABL
E_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) |
| 311 #define GPIO_PIN7_INT_TYPE_MSB 9 |
| 312 #define GPIO_PIN7_INT_TYPE_LSB 7 |
| 313 #define GPIO_PIN7_INT_TYPE_MASK 0x00000380 |
| 314 #define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK
) >> GPIO_PIN7_INT_TYPE_LSB) |
| 315 #define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB
) & GPIO_PIN7_INT_TYPE_MASK) |
| 316 #define GPIO_PIN7_PAD_DRIVER_MSB 2 |
| 317 #define GPIO_PIN7_PAD_DRIVER_LSB 2 |
| 318 #define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 |
| 319 #define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MA
SK) >> GPIO_PIN7_PAD_DRIVER_LSB) |
| 320 #define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_L
SB) & GPIO_PIN7_PAD_DRIVER_MASK) |
| 321 #define GPIO_PIN7_SOURCE_MSB 0 |
| 322 #define GPIO_PIN7_SOURCE_LSB 0 |
| 323 #define GPIO_PIN7_SOURCE_MASK 0x00000001 |
| 324 #define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK)
>> GPIO_PIN7_SOURCE_LSB) |
| 325 #define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB)
& GPIO_PIN7_SOURCE_MASK) |
| 326 |
| 327 #define GPIO_PIN8_ADDRESS 0x00000048 |
| 328 #define GPIO_PIN8_OFFSET 0x00000048 |
| 329 #define GPIO_PIN8_CONFIG_MSB 12 |
| 330 #define GPIO_PIN8_CONFIG_LSB 11 |
| 331 #define GPIO_PIN8_CONFIG_MASK 0x00001800 |
| 332 #define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK)
>> GPIO_PIN8_CONFIG_LSB) |
| 333 #define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB)
& GPIO_PIN8_CONFIG_MASK) |
| 334 #define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 |
| 335 #define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 |
| 336 #define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 |
| 337 #define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE
_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) |
| 338 #define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABL
E_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) |
| 339 #define GPIO_PIN8_INT_TYPE_MSB 9 |
| 340 #define GPIO_PIN8_INT_TYPE_LSB 7 |
| 341 #define GPIO_PIN8_INT_TYPE_MASK 0x00000380 |
| 342 #define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK
) >> GPIO_PIN8_INT_TYPE_LSB) |
| 343 #define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB
) & GPIO_PIN8_INT_TYPE_MASK) |
| 344 #define GPIO_PIN8_PAD_DRIVER_MSB 2 |
| 345 #define GPIO_PIN8_PAD_DRIVER_LSB 2 |
| 346 #define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 |
| 347 #define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MA
SK) >> GPIO_PIN8_PAD_DRIVER_LSB) |
| 348 #define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_L
SB) & GPIO_PIN8_PAD_DRIVER_MASK) |
| 349 #define GPIO_PIN8_SOURCE_MSB 0 |
| 350 #define GPIO_PIN8_SOURCE_LSB 0 |
| 351 #define GPIO_PIN8_SOURCE_MASK 0x00000001 |
| 352 #define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK)
>> GPIO_PIN8_SOURCE_LSB) |
| 353 #define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB)
& GPIO_PIN8_SOURCE_MASK) |
| 354 |
| 355 #define GPIO_PIN9_ADDRESS 0x0000004c |
| 356 #define GPIO_PIN9_OFFSET 0x0000004c |
| 357 #define GPIO_PIN9_CONFIG_MSB 12 |
| 358 #define GPIO_PIN9_CONFIG_LSB 11 |
| 359 #define GPIO_PIN9_CONFIG_MASK 0x00001800 |
| 360 #define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK)
>> GPIO_PIN9_CONFIG_LSB) |
| 361 #define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB)
& GPIO_PIN9_CONFIG_MASK) |
| 362 #define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 |
| 363 #define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 |
| 364 #define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 |
| 365 #define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE
_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) |
| 366 #define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABL
E_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) |
| 367 #define GPIO_PIN9_INT_TYPE_MSB 9 |
| 368 #define GPIO_PIN9_INT_TYPE_LSB 7 |
| 369 #define GPIO_PIN9_INT_TYPE_MASK 0x00000380 |
| 370 #define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK
) >> GPIO_PIN9_INT_TYPE_LSB) |
| 371 #define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB
) & GPIO_PIN9_INT_TYPE_MASK) |
| 372 #define GPIO_PIN9_PAD_DRIVER_MSB 2 |
| 373 #define GPIO_PIN9_PAD_DRIVER_LSB 2 |
| 374 #define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 |
| 375 #define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MA
SK) >> GPIO_PIN9_PAD_DRIVER_LSB) |
| 376 #define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_L
SB) & GPIO_PIN9_PAD_DRIVER_MASK) |
| 377 #define GPIO_PIN9_SOURCE_MSB 0 |
| 378 #define GPIO_PIN9_SOURCE_LSB 0 |
| 379 #define GPIO_PIN9_SOURCE_MASK 0x00000001 |
| 380 #define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK)
>> GPIO_PIN9_SOURCE_LSB) |
| 381 #define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB)
& GPIO_PIN9_SOURCE_MASK) |
| 382 |
| 383 #define GPIO_PIN10_ADDRESS 0x00000050 |
| 384 #define GPIO_PIN10_OFFSET 0x00000050 |
| 385 #define GPIO_PIN10_CONFIG_MSB 12 |
| 386 #define GPIO_PIN10_CONFIG_LSB 11 |
| 387 #define GPIO_PIN10_CONFIG_MASK 0x00001800 |
| 388 #define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK)
>> GPIO_PIN10_CONFIG_LSB) |
| 389 #define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB)
& GPIO_PIN10_CONFIG_MASK) |
| 390 #define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 |
| 391 #define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 |
| 392 #define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 |
| 393 #define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABL
E_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) |
| 394 #define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENAB
LE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) |
| 395 #define GPIO_PIN10_INT_TYPE_MSB 9 |
| 396 #define GPIO_PIN10_INT_TYPE_LSB 7 |
| 397 #define GPIO_PIN10_INT_TYPE_MASK 0x00000380 |
| 398 #define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MAS
K) >> GPIO_PIN10_INT_TYPE_LSB) |
| 399 #define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LS
B) & GPIO_PIN10_INT_TYPE_MASK) |
| 400 #define GPIO_PIN10_PAD_DRIVER_MSB 2 |
| 401 #define GPIO_PIN10_PAD_DRIVER_LSB 2 |
| 402 #define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 |
| 403 #define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_M
ASK) >> GPIO_PIN10_PAD_DRIVER_LSB) |
| 404 #define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_
LSB) & GPIO_PIN10_PAD_DRIVER_MASK) |
| 405 #define GPIO_PIN10_SOURCE_MSB 0 |
| 406 #define GPIO_PIN10_SOURCE_LSB 0 |
| 407 #define GPIO_PIN10_SOURCE_MASK 0x00000001 |
| 408 #define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK)
>> GPIO_PIN10_SOURCE_LSB) |
| 409 #define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB)
& GPIO_PIN10_SOURCE_MASK) |
| 410 |
| 411 #define GPIO_PIN11_ADDRESS 0x00000054 |
| 412 #define GPIO_PIN11_OFFSET 0x00000054 |
| 413 #define GPIO_PIN11_CONFIG_MSB 12 |
| 414 #define GPIO_PIN11_CONFIG_LSB 11 |
| 415 #define GPIO_PIN11_CONFIG_MASK 0x00001800 |
| 416 #define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK)
>> GPIO_PIN11_CONFIG_LSB) |
| 417 #define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB)
& GPIO_PIN11_CONFIG_MASK) |
| 418 #define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 |
| 419 #define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 |
| 420 #define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 |
| 421 #define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABL
E_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) |
| 422 #define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENAB
LE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) |
| 423 #define GPIO_PIN11_INT_TYPE_MSB 9 |
| 424 #define GPIO_PIN11_INT_TYPE_LSB 7 |
| 425 #define GPIO_PIN11_INT_TYPE_MASK 0x00000380 |
| 426 #define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MAS
K) >> GPIO_PIN11_INT_TYPE_LSB) |
| 427 #define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LS
B) & GPIO_PIN11_INT_TYPE_MASK) |
| 428 #define GPIO_PIN11_PAD_DRIVER_MSB 2 |
| 429 #define GPIO_PIN11_PAD_DRIVER_LSB 2 |
| 430 #define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 |
| 431 #define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_M
ASK) >> GPIO_PIN11_PAD_DRIVER_LSB) |
| 432 #define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_
LSB) & GPIO_PIN11_PAD_DRIVER_MASK) |
| 433 #define GPIO_PIN11_SOURCE_MSB 0 |
| 434 #define GPIO_PIN11_SOURCE_LSB 0 |
| 435 #define GPIO_PIN11_SOURCE_MASK 0x00000001 |
| 436 #define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK)
>> GPIO_PIN11_SOURCE_LSB) |
| 437 #define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB)
& GPIO_PIN11_SOURCE_MASK) |
| 438 |
| 439 #define GPIO_PIN12_ADDRESS 0x00000058 |
| 440 #define GPIO_PIN12_OFFSET 0x00000058 |
| 441 #define GPIO_PIN12_CONFIG_MSB 12 |
| 442 #define GPIO_PIN12_CONFIG_LSB 11 |
| 443 #define GPIO_PIN12_CONFIG_MASK 0x00001800 |
| 444 #define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK)
>> GPIO_PIN12_CONFIG_LSB) |
| 445 #define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB)
& GPIO_PIN12_CONFIG_MASK) |
| 446 #define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 |
| 447 #define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 |
| 448 #define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 |
| 449 #define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABL
E_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) |
| 450 #define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENAB
LE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) |
| 451 #define GPIO_PIN12_INT_TYPE_MSB 9 |
| 452 #define GPIO_PIN12_INT_TYPE_LSB 7 |
| 453 #define GPIO_PIN12_INT_TYPE_MASK 0x00000380 |
| 454 #define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MAS
K) >> GPIO_PIN12_INT_TYPE_LSB) |
| 455 #define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LS
B) & GPIO_PIN12_INT_TYPE_MASK) |
| 456 #define GPIO_PIN12_PAD_DRIVER_MSB 2 |
| 457 #define GPIO_PIN12_PAD_DRIVER_LSB 2 |
| 458 #define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 |
| 459 #define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_M
ASK) >> GPIO_PIN12_PAD_DRIVER_LSB) |
| 460 #define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_
LSB) & GPIO_PIN12_PAD_DRIVER_MASK) |
| 461 #define GPIO_PIN12_SOURCE_MSB 0 |
| 462 #define GPIO_PIN12_SOURCE_LSB 0 |
| 463 #define GPIO_PIN12_SOURCE_MASK 0x00000001 |
| 464 #define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK)
>> GPIO_PIN12_SOURCE_LSB) |
| 465 #define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB)
& GPIO_PIN12_SOURCE_MASK) |
| 466 |
| 467 #define GPIO_PIN13_ADDRESS 0x0000005c |
| 468 #define GPIO_PIN13_OFFSET 0x0000005c |
| 469 #define GPIO_PIN13_CONFIG_MSB 12 |
| 470 #define GPIO_PIN13_CONFIG_LSB 11 |
| 471 #define GPIO_PIN13_CONFIG_MASK 0x00001800 |
| 472 #define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK)
>> GPIO_PIN13_CONFIG_LSB) |
| 473 #define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB)
& GPIO_PIN13_CONFIG_MASK) |
| 474 #define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 |
| 475 #define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 |
| 476 #define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 |
| 477 #define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABL
E_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) |
| 478 #define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENAB
LE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) |
| 479 #define GPIO_PIN13_INT_TYPE_MSB 9 |
| 480 #define GPIO_PIN13_INT_TYPE_LSB 7 |
| 481 #define GPIO_PIN13_INT_TYPE_MASK 0x00000380 |
| 482 #define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MAS
K) >> GPIO_PIN13_INT_TYPE_LSB) |
| 483 #define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LS
B) & GPIO_PIN13_INT_TYPE_MASK) |
| 484 #define GPIO_PIN13_PAD_DRIVER_MSB 2 |
| 485 #define GPIO_PIN13_PAD_DRIVER_LSB 2 |
| 486 #define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 |
| 487 #define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_M
ASK) >> GPIO_PIN13_PAD_DRIVER_LSB) |
| 488 #define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_
LSB) & GPIO_PIN13_PAD_DRIVER_MASK) |
| 489 #define GPIO_PIN13_SOURCE_MSB 0 |
| 490 #define GPIO_PIN13_SOURCE_LSB 0 |
| 491 #define GPIO_PIN13_SOURCE_MASK 0x00000001 |
| 492 #define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK)
>> GPIO_PIN13_SOURCE_LSB) |
| 493 #define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB)
& GPIO_PIN13_SOURCE_MASK) |
| 494 |
| 495 #define GPIO_PIN14_ADDRESS 0x00000060 |
| 496 #define GPIO_PIN14_OFFSET 0x00000060 |
| 497 #define GPIO_PIN14_CONFIG_MSB 12 |
| 498 #define GPIO_PIN14_CONFIG_LSB 11 |
| 499 #define GPIO_PIN14_CONFIG_MASK 0x00001800 |
| 500 #define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK)
>> GPIO_PIN14_CONFIG_LSB) |
| 501 #define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB)
& GPIO_PIN14_CONFIG_MASK) |
| 502 #define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 |
| 503 #define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 |
| 504 #define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 |
| 505 #define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABL
E_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) |
| 506 #define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENAB
LE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) |
| 507 #define GPIO_PIN14_INT_TYPE_MSB 9 |
| 508 #define GPIO_PIN14_INT_TYPE_LSB 7 |
| 509 #define GPIO_PIN14_INT_TYPE_MASK 0x00000380 |
| 510 #define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MAS
K) >> GPIO_PIN14_INT_TYPE_LSB) |
| 511 #define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LS
B) & GPIO_PIN14_INT_TYPE_MASK) |
| 512 #define GPIO_PIN14_PAD_DRIVER_MSB 2 |
| 513 #define GPIO_PIN14_PAD_DRIVER_LSB 2 |
| 514 #define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 |
| 515 #define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_M
ASK) >> GPIO_PIN14_PAD_DRIVER_LSB) |
| 516 #define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_
LSB) & GPIO_PIN14_PAD_DRIVER_MASK) |
| 517 #define GPIO_PIN14_SOURCE_MSB 0 |
| 518 #define GPIO_PIN14_SOURCE_LSB 0 |
| 519 #define GPIO_PIN14_SOURCE_MASK 0x00000001 |
| 520 #define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK)
>> GPIO_PIN14_SOURCE_LSB) |
| 521 #define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB)
& GPIO_PIN14_SOURCE_MASK) |
| 522 |
| 523 #define GPIO_PIN15_ADDRESS 0x00000064 |
| 524 #define GPIO_PIN15_OFFSET 0x00000064 |
| 525 #define GPIO_PIN15_CONFIG_MSB 12 |
| 526 #define GPIO_PIN15_CONFIG_LSB 11 |
| 527 #define GPIO_PIN15_CONFIG_MASK 0x00001800 |
| 528 #define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK)
>> GPIO_PIN15_CONFIG_LSB) |
| 529 #define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB)
& GPIO_PIN15_CONFIG_MASK) |
| 530 #define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 |
| 531 #define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 |
| 532 #define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 |
| 533 #define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABL
E_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) |
| 534 #define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENAB
LE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) |
| 535 #define GPIO_PIN15_INT_TYPE_MSB 9 |
| 536 #define GPIO_PIN15_INT_TYPE_LSB 7 |
| 537 #define GPIO_PIN15_INT_TYPE_MASK 0x00000380 |
| 538 #define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MAS
K) >> GPIO_PIN15_INT_TYPE_LSB) |
| 539 #define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LS
B) & GPIO_PIN15_INT_TYPE_MASK) |
| 540 #define GPIO_PIN15_PAD_DRIVER_MSB 2 |
| 541 #define GPIO_PIN15_PAD_DRIVER_LSB 2 |
| 542 #define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 |
| 543 #define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_M
ASK) >> GPIO_PIN15_PAD_DRIVER_LSB) |
| 544 #define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_
LSB) & GPIO_PIN15_PAD_DRIVER_MASK) |
| 545 #define GPIO_PIN15_SOURCE_MSB 0 |
| 546 #define GPIO_PIN15_SOURCE_LSB 0 |
| 547 #define GPIO_PIN15_SOURCE_MASK 0x00000001 |
| 548 #define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK)
>> GPIO_PIN15_SOURCE_LSB) |
| 549 #define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB)
& GPIO_PIN15_SOURCE_MASK) |
| 550 |
| 551 #define GPIO_PIN16_ADDRESS 0x00000068 |
| 552 #define GPIO_PIN16_OFFSET 0x00000068 |
| 553 #define GPIO_PIN16_CONFIG_MSB 12 |
| 554 #define GPIO_PIN16_CONFIG_LSB 11 |
| 555 #define GPIO_PIN16_CONFIG_MASK 0x00001800 |
| 556 #define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK)
>> GPIO_PIN16_CONFIG_LSB) |
| 557 #define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB)
& GPIO_PIN16_CONFIG_MASK) |
| 558 #define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 |
| 559 #define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 |
| 560 #define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 |
| 561 #define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABL
E_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) |
| 562 #define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENAB
LE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) |
| 563 #define GPIO_PIN16_INT_TYPE_MSB 9 |
| 564 #define GPIO_PIN16_INT_TYPE_LSB 7 |
| 565 #define GPIO_PIN16_INT_TYPE_MASK 0x00000380 |
| 566 #define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MAS
K) >> GPIO_PIN16_INT_TYPE_LSB) |
| 567 #define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LS
B) & GPIO_PIN16_INT_TYPE_MASK) |
| 568 #define GPIO_PIN16_PAD_DRIVER_MSB 2 |
| 569 #define GPIO_PIN16_PAD_DRIVER_LSB 2 |
| 570 #define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 |
| 571 #define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_M
ASK) >> GPIO_PIN16_PAD_DRIVER_LSB) |
| 572 #define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_
LSB) & GPIO_PIN16_PAD_DRIVER_MASK) |
| 573 #define GPIO_PIN16_SOURCE_MSB 0 |
| 574 #define GPIO_PIN16_SOURCE_LSB 0 |
| 575 #define GPIO_PIN16_SOURCE_MASK 0x00000001 |
| 576 #define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK)
>> GPIO_PIN16_SOURCE_LSB) |
| 577 #define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB)
& GPIO_PIN16_SOURCE_MASK) |
| 578 |
| 579 #define GPIO_PIN17_ADDRESS 0x0000006c |
| 580 #define GPIO_PIN17_OFFSET 0x0000006c |
| 581 #define GPIO_PIN17_CONFIG_MSB 12 |
| 582 #define GPIO_PIN17_CONFIG_LSB 11 |
| 583 #define GPIO_PIN17_CONFIG_MASK 0x00001800 |
| 584 #define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK)
>> GPIO_PIN17_CONFIG_LSB) |
| 585 #define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB)
& GPIO_PIN17_CONFIG_MASK) |
| 586 #define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 |
| 587 #define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 |
| 588 #define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 |
| 589 #define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABL
E_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) |
| 590 #define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENAB
LE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) |
| 591 #define GPIO_PIN17_INT_TYPE_MSB 9 |
| 592 #define GPIO_PIN17_INT_TYPE_LSB 7 |
| 593 #define GPIO_PIN17_INT_TYPE_MASK 0x00000380 |
| 594 #define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MAS
K) >> GPIO_PIN17_INT_TYPE_LSB) |
| 595 #define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LS
B) & GPIO_PIN17_INT_TYPE_MASK) |
| 596 #define GPIO_PIN17_PAD_DRIVER_MSB 2 |
| 597 #define GPIO_PIN17_PAD_DRIVER_LSB 2 |
| 598 #define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 |
| 599 #define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_M
ASK) >> GPIO_PIN17_PAD_DRIVER_LSB) |
| 600 #define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_
LSB) & GPIO_PIN17_PAD_DRIVER_MASK) |
| 601 #define GPIO_PIN17_SOURCE_MSB 0 |
| 602 #define GPIO_PIN17_SOURCE_LSB 0 |
| 603 #define GPIO_PIN17_SOURCE_MASK 0x00000001 |
| 604 #define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK)
>> GPIO_PIN17_SOURCE_LSB) |
| 605 #define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB)
& GPIO_PIN17_SOURCE_MASK) |
| 606 |
| 607 #define SDIO_PIN_ADDRESS 0x00000070 |
| 608 #define SDIO_PIN_OFFSET 0x00000070 |
| 609 #define SDIO_PIN_PAD_PULL_MSB 3 |
| 610 #define SDIO_PIN_PAD_PULL_LSB 2 |
| 611 #define SDIO_PIN_PAD_PULL_MASK 0x0000000c |
| 612 #define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK)
>> SDIO_PIN_PAD_PULL_LSB) |
| 613 #define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB)
& SDIO_PIN_PAD_PULL_MASK) |
| 614 #define SDIO_PIN_PAD_STRENGTH_MSB 1 |
| 615 #define SDIO_PIN_PAD_STRENGTH_LSB 0 |
| 616 #define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 617 #define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_M
ASK) >> SDIO_PIN_PAD_STRENGTH_LSB) |
| 618 #define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_
LSB) & SDIO_PIN_PAD_STRENGTH_MASK) |
| 619 |
| 620 #define CLK_REQ_PIN_ADDRESS 0x00000074 |
| 621 #define CLK_REQ_PIN_OFFSET 0x00000074 |
| 622 #define CLK_REQ_PIN_ATE_OE_L_MSB 4 |
| 623 #define CLK_REQ_PIN_ATE_OE_L_LSB 4 |
| 624 #define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 |
| 625 #define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MA
SK) >> CLK_REQ_PIN_ATE_OE_L_LSB) |
| 626 #define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_L
SB) & CLK_REQ_PIN_ATE_OE_L_MASK) |
| 627 #define CLK_REQ_PIN_PAD_PULL_MSB 3 |
| 628 #define CLK_REQ_PIN_PAD_PULL_LSB 2 |
| 629 #define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c |
| 630 #define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MA
SK) >> CLK_REQ_PIN_PAD_PULL_LSB) |
| 631 #define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_L
SB) & CLK_REQ_PIN_PAD_PULL_MASK) |
| 632 #define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 |
| 633 #define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 |
| 634 #define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 635 #define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGT
H_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) |
| 636 #define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENG
TH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) |
| 637 |
| 638 #define SIGMA_DELTA_ADDRESS 0x00000078 |
| 639 #define SIGMA_DELTA_OFFSET 0x00000078 |
| 640 #define SIGMA_DELTA_ENABLE_MSB 16 |
| 641 #define SIGMA_DELTA_ENABLE_LSB 16 |
| 642 #define SIGMA_DELTA_ENABLE_MASK 0x00010000 |
| 643 #define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK
) >> SIGMA_DELTA_ENABLE_LSB) |
| 644 #define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB
) & SIGMA_DELTA_ENABLE_MASK) |
| 645 #define SIGMA_DELTA_PRESCALAR_MSB 15 |
| 646 #define SIGMA_DELTA_PRESCALAR_LSB 8 |
| 647 #define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 |
| 648 #define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_M
ASK) >> SIGMA_DELTA_PRESCALAR_LSB) |
| 649 #define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_
LSB) & SIGMA_DELTA_PRESCALAR_MASK) |
| 650 #define SIGMA_DELTA_TARGET_MSB 7 |
| 651 #define SIGMA_DELTA_TARGET_LSB 0 |
| 652 #define SIGMA_DELTA_TARGET_MASK 0x000000ff |
| 653 #define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK
) >> SIGMA_DELTA_TARGET_LSB) |
| 654 #define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB
) & SIGMA_DELTA_TARGET_MASK) |
| 655 |
| 656 #define DEBUG_CONTROL_ADDRESS 0x0000007c |
| 657 #define DEBUG_CONTROL_OFFSET 0x0000007c |
| 658 #define DEBUG_CONTROL_OBS_OE_L_MSB 1 |
| 659 #define DEBUG_CONTROL_OBS_OE_L_LSB 1 |
| 660 #define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 |
| 661 #define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_
MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) |
| 662 #define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L
_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) |
| 663 #define DEBUG_CONTROL_ENABLE_MSB 0 |
| 664 #define DEBUG_CONTROL_ENABLE_LSB 0 |
| 665 #define DEBUG_CONTROL_ENABLE_MASK 0x00000001 |
| 666 #define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MA
SK) >> DEBUG_CONTROL_ENABLE_LSB) |
| 667 #define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_L
SB) & DEBUG_CONTROL_ENABLE_MASK) |
| 668 |
| 669 #define DEBUG_INPUT_SEL_ADDRESS 0x00000080 |
| 670 #define DEBUG_INPUT_SEL_OFFSET 0x00000080 |
| 671 #define DEBUG_INPUT_SEL_SRC_MSB 3 |
| 672 #define DEBUG_INPUT_SEL_SRC_LSB 0 |
| 673 #define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f |
| 674 #define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MAS
K) >> DEBUG_INPUT_SEL_SRC_LSB) |
| 675 #define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LS
B) & DEBUG_INPUT_SEL_SRC_MASK) |
| 676 |
| 677 #define DEBUG_OUT_ADDRESS 0x00000084 |
| 678 #define DEBUG_OUT_OFFSET 0x00000084 |
| 679 #define DEBUG_OUT_DATA_MSB 17 |
| 680 #define DEBUG_OUT_DATA_LSB 0 |
| 681 #define DEBUG_OUT_DATA_MASK 0x0003ffff |
| 682 #define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >>
DEBUG_OUT_DATA_LSB) |
| 683 #define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) &
DEBUG_OUT_DATA_MASK) |
| 684 |
| 685 #define LA_CONTROL_ADDRESS 0x00000088 |
| 686 #define LA_CONTROL_OFFSET 0x00000088 |
| 687 #define LA_CONTROL_RUN_MSB 1 |
| 688 #define LA_CONTROL_RUN_LSB 1 |
| 689 #define LA_CONTROL_RUN_MASK 0x00000002 |
| 690 #define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >>
LA_CONTROL_RUN_LSB) |
| 691 #define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) &
LA_CONTROL_RUN_MASK) |
| 692 #define LA_CONTROL_TRIGGERED_MSB 0 |
| 693 #define LA_CONTROL_TRIGGERED_LSB 0 |
| 694 #define LA_CONTROL_TRIGGERED_MASK 0x00000001 |
| 695 #define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MA
SK) >> LA_CONTROL_TRIGGERED_LSB) |
| 696 #define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_L
SB) & LA_CONTROL_TRIGGERED_MASK) |
| 697 |
| 698 #define LA_CLOCK_ADDRESS 0x0000008c |
| 699 #define LA_CLOCK_OFFSET 0x0000008c |
| 700 #define LA_CLOCK_DIV_MSB 7 |
| 701 #define LA_CLOCK_DIV_LSB 0 |
| 702 #define LA_CLOCK_DIV_MASK 0x000000ff |
| 703 #define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> L
A_CLOCK_DIV_LSB) |
| 704 #define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA
_CLOCK_DIV_MASK) |
| 705 |
| 706 #define LA_STATUS_ADDRESS 0x00000090 |
| 707 #define LA_STATUS_OFFSET 0x00000090 |
| 708 #define LA_STATUS_INTERRUPT_MSB 0 |
| 709 #define LA_STATUS_INTERRUPT_LSB 0 |
| 710 #define LA_STATUS_INTERRUPT_MASK 0x00000001 |
| 711 #define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MAS
K) >> LA_STATUS_INTERRUPT_LSB) |
| 712 #define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LS
B) & LA_STATUS_INTERRUPT_MASK) |
| 713 |
| 714 #define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 |
| 715 #define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 |
| 716 #define LA_TRIGGER_SAMPLE_COUNT_MSB 15 |
| 717 #define LA_TRIGGER_SAMPLE_COUNT_LSB 0 |
| 718 #define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff |
| 719 #define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT
_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) |
| 720 #define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUN
T_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) |
| 721 |
| 722 #define LA_TRIGGER_POSITION_ADDRESS 0x00000098 |
| 723 #define LA_TRIGGER_POSITION_OFFSET 0x00000098 |
| 724 #define LA_TRIGGER_POSITION_VALUE_MSB 15 |
| 725 #define LA_TRIGGER_POSITION_VALUE_LSB 0 |
| 726 #define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff |
| 727 #define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VAL
UE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) |
| 728 #define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VA
LUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) |
| 729 |
| 730 #define LA_PRE_TRIGGER_ADDRESS 0x0000009c |
| 731 #define LA_PRE_TRIGGER_OFFSET 0x0000009c |
| 732 #define LA_PRE_TRIGGER_COUNT_MSB 15 |
| 733 #define LA_PRE_TRIGGER_COUNT_LSB 0 |
| 734 #define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff |
| 735 #define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MA
SK) >> LA_PRE_TRIGGER_COUNT_LSB) |
| 736 #define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_L
SB) & LA_PRE_TRIGGER_COUNT_MASK) |
| 737 |
| 738 #define LA_POST_TRIGGER_ADDRESS 0x000000a0 |
| 739 #define LA_POST_TRIGGER_OFFSET 0x000000a0 |
| 740 #define LA_POST_TRIGGER_COUNT_MSB 15 |
| 741 #define LA_POST_TRIGGER_COUNT_LSB 0 |
| 742 #define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff |
| 743 #define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_M
ASK) >> LA_POST_TRIGGER_COUNT_LSB) |
| 744 #define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_
LSB) & LA_POST_TRIGGER_COUNT_MASK) |
| 745 |
| 746 #define LA_FILTER_CONTROL_ADDRESS 0x000000a4 |
| 747 #define LA_FILTER_CONTROL_OFFSET 0x000000a4 |
| 748 #define LA_FILTER_CONTROL_DELTA_MSB 0 |
| 749 #define LA_FILTER_CONTROL_DELTA_LSB 0 |
| 750 #define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 |
| 751 #define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA
_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) |
| 752 #define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELT
A_LSB) & LA_FILTER_CONTROL_DELTA_MASK) |
| 753 |
| 754 #define LA_FILTER_DATA_ADDRESS 0x000000a8 |
| 755 #define LA_FILTER_DATA_OFFSET 0x000000a8 |
| 756 #define LA_FILTER_DATA_MATCH_MSB 17 |
| 757 #define LA_FILTER_DATA_MATCH_LSB 0 |
| 758 #define LA_FILTER_DATA_MATCH_MASK 0x0003ffff |
| 759 #define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MA
SK) >> LA_FILTER_DATA_MATCH_LSB) |
| 760 #define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_L
SB) & LA_FILTER_DATA_MATCH_MASK) |
| 761 |
| 762 #define LA_FILTER_WILDCARD_ADDRESS 0x000000ac |
| 763 #define LA_FILTER_WILDCARD_OFFSET 0x000000ac |
| 764 #define LA_FILTER_WILDCARD_MATCH_MSB 17 |
| 765 #define LA_FILTER_WILDCARD_MATCH_LSB 0 |
| 766 #define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff |
| 767 #define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATC
H_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) |
| 768 #define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MAT
CH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) |
| 769 |
| 770 #define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 |
| 771 #define LA_TRIGGERA_DATA_OFFSET 0x000000b0 |
| 772 #define LA_TRIGGERA_DATA_MATCH_MSB 17 |
| 773 #define LA_TRIGGERA_DATA_MATCH_LSB 0 |
| 774 #define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff |
| 775 #define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_
MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) |
| 776 #define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH
_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) |
| 777 |
| 778 #define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 |
| 779 #define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 |
| 780 #define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 |
| 781 #define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 |
| 782 #define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff |
| 783 #define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MA
TCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) |
| 784 #define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_M
ATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) |
| 785 |
| 786 #define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 |
| 787 #define LA_TRIGGERB_DATA_OFFSET 0x000000b8 |
| 788 #define LA_TRIGGERB_DATA_MATCH_MSB 17 |
| 789 #define LA_TRIGGERB_DATA_MATCH_LSB 0 |
| 790 #define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff |
| 791 #define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_
MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) |
| 792 #define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH
_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) |
| 793 |
| 794 #define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc |
| 795 #define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc |
| 796 #define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 |
| 797 #define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 |
| 798 #define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff |
| 799 #define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MA
TCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) |
| 800 #define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_M
ATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) |
| 801 |
| 802 #define LA_TRIGGER_ADDRESS 0x000000c0 |
| 803 #define LA_TRIGGER_OFFSET 0x000000c0 |
| 804 #define LA_TRIGGER_EVENT_MSB 2 |
| 805 #define LA_TRIGGER_EVENT_LSB 0 |
| 806 #define LA_TRIGGER_EVENT_MASK 0x00000007 |
| 807 #define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK)
>> LA_TRIGGER_EVENT_LSB) |
| 808 #define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB)
& LA_TRIGGER_EVENT_MASK) |
| 809 |
| 810 #define LA_FIFO_ADDRESS 0x000000c4 |
| 811 #define LA_FIFO_OFFSET 0x000000c4 |
| 812 #define LA_FIFO_FULL_MSB 1 |
| 813 #define LA_FIFO_FULL_LSB 1 |
| 814 #define LA_FIFO_FULL_MASK 0x00000002 |
| 815 #define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> L
A_FIFO_FULL_LSB) |
| 816 #define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA
_FIFO_FULL_MASK) |
| 817 #define LA_FIFO_EMPTY_MSB 0 |
| 818 #define LA_FIFO_EMPTY_LSB 0 |
| 819 #define LA_FIFO_EMPTY_MASK 0x00000001 |
| 820 #define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >>
LA_FIFO_EMPTY_LSB) |
| 821 #define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & L
A_FIFO_EMPTY_MASK) |
| 822 |
| 823 #define LA_ADDRESS 0x000000c8 |
| 824 #define LA_OFFSET 0x000000c8 |
| 825 #define LA_DATA_MSB 17 |
| 826 #define LA_DATA_LSB 0 |
| 827 #define LA_DATA_MASK 0x0003ffff |
| 828 #define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DAT
A_LSB) |
| 829 #define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA
_MASK) |
| 830 |
| 831 #define ANT_PIN_ADDRESS 0x000000d0 |
| 832 #define ANT_PIN_OFFSET 0x000000d0 |
| 833 #define ANT_PIN_PAD_PULL_MSB 3 |
| 834 #define ANT_PIN_PAD_PULL_LSB 2 |
| 835 #define ANT_PIN_PAD_PULL_MASK 0x0000000c |
| 836 #define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK)
>> ANT_PIN_PAD_PULL_LSB) |
| 837 #define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB)
& ANT_PIN_PAD_PULL_MASK) |
| 838 #define ANT_PIN_PAD_STRENGTH_MSB 1 |
| 839 #define ANT_PIN_PAD_STRENGTH_LSB 0 |
| 840 #define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 841 #define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MA
SK) >> ANT_PIN_PAD_STRENGTH_LSB) |
| 842 #define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_L
SB) & ANT_PIN_PAD_STRENGTH_MASK) |
| 843 |
| 844 #define ANTD_PIN_ADDRESS 0x000000d4 |
| 845 #define ANTD_PIN_OFFSET 0x000000d4 |
| 846 #define ANTD_PIN_PAD_PULL_MSB 1 |
| 847 #define ANTD_PIN_PAD_PULL_LSB 0 |
| 848 #define ANTD_PIN_PAD_PULL_MASK 0x00000003 |
| 849 #define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK)
>> ANTD_PIN_PAD_PULL_LSB) |
| 850 #define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB)
& ANTD_PIN_PAD_PULL_MASK) |
| 851 |
| 852 #define GPIO_PIN_ADDRESS 0x000000d8 |
| 853 #define GPIO_PIN_OFFSET 0x000000d8 |
| 854 #define GPIO_PIN_PAD_PULL_MSB 3 |
| 855 #define GPIO_PIN_PAD_PULL_LSB 2 |
| 856 #define GPIO_PIN_PAD_PULL_MASK 0x0000000c |
| 857 #define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK)
>> GPIO_PIN_PAD_PULL_LSB) |
| 858 #define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB)
& GPIO_PIN_PAD_PULL_MASK) |
| 859 #define GPIO_PIN_PAD_STRENGTH_MSB 1 |
| 860 #define GPIO_PIN_PAD_STRENGTH_LSB 0 |
| 861 #define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 862 #define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_M
ASK) >> GPIO_PIN_PAD_STRENGTH_LSB) |
| 863 #define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_
LSB) & GPIO_PIN_PAD_STRENGTH_MASK) |
| 864 |
| 865 #define GPIO_H_PIN_ADDRESS 0x000000dc |
| 866 #define GPIO_H_PIN_OFFSET 0x000000dc |
| 867 #define GPIO_H_PIN_PAD_PULL_MSB 1 |
| 868 #define GPIO_H_PIN_PAD_PULL_LSB 0 |
| 869 #define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 |
| 870 #define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MAS
K) >> GPIO_H_PIN_PAD_PULL_LSB) |
| 871 #define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LS
B) & GPIO_H_PIN_PAD_PULL_MASK) |
| 872 |
| 873 #define BT_PIN_ADDRESS 0x000000e0 |
| 874 #define BT_PIN_OFFSET 0x000000e0 |
| 875 #define BT_PIN_PAD_PULL_MSB 3 |
| 876 #define BT_PIN_PAD_PULL_LSB 2 |
| 877 #define BT_PIN_PAD_PULL_MASK 0x0000000c |
| 878 #define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >
> BT_PIN_PAD_PULL_LSB) |
| 879 #define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) &
BT_PIN_PAD_PULL_MASK) |
| 880 #define BT_PIN_PAD_STRENGTH_MSB 1 |
| 881 #define BT_PIN_PAD_STRENGTH_LSB 0 |
| 882 #define BT_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 883 #define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MAS
K) >> BT_PIN_PAD_STRENGTH_LSB) |
| 884 #define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LS
B) & BT_PIN_PAD_STRENGTH_MASK) |
| 885 |
| 886 #define BT_WLAN_PIN_ADDRESS 0x000000e4 |
| 887 #define BT_WLAN_PIN_OFFSET 0x000000e4 |
| 888 #define BT_WLAN_PIN_PAD_PULL_MSB 1 |
| 889 #define BT_WLAN_PIN_PAD_PULL_LSB 0 |
| 890 #define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 |
| 891 #define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MA
SK) >> BT_WLAN_PIN_PAD_PULL_LSB) |
| 892 #define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_L
SB) & BT_WLAN_PIN_PAD_PULL_MASK) |
| 893 |
| 894 #define SI_UART_PIN_ADDRESS 0x000000e8 |
| 895 #define SI_UART_PIN_OFFSET 0x000000e8 |
| 896 #define SI_UART_PIN_PAD_PULL_MSB 3 |
| 897 #define SI_UART_PIN_PAD_PULL_LSB 2 |
| 898 #define SI_UART_PIN_PAD_PULL_MASK 0x0000000c |
| 899 #define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MA
SK) >> SI_UART_PIN_PAD_PULL_LSB) |
| 900 #define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_L
SB) & SI_UART_PIN_PAD_PULL_MASK) |
| 901 #define SI_UART_PIN_PAD_STRENGTH_MSB 1 |
| 902 #define SI_UART_PIN_PAD_STRENGTH_LSB 0 |
| 903 #define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 |
| 904 #define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGT
H_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) |
| 905 #define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENG
TH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) |
| 906 |
| 907 #define CLK32K_PIN_ADDRESS 0x000000ec |
| 908 #define CLK32K_PIN_OFFSET 0x000000ec |
| 909 #define CLK32K_PIN_PAD_PULL_MSB 1 |
| 910 #define CLK32K_PIN_PAD_PULL_LSB 0 |
| 911 #define CLK32K_PIN_PAD_PULL_MASK 0x00000003 |
| 912 #define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MAS
K) >> CLK32K_PIN_PAD_PULL_LSB) |
| 913 #define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LS
B) & CLK32K_PIN_PAD_PULL_MASK) |
| 914 |
| 915 #define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 |
| 916 #define RESET_TUPLE_STATUS_OFFSET 0x000000f0 |
| 917 #define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 |
| 918 #define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 |
| 919 #define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 |
| 920 #define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TE
ST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) |
| 921 #define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_T
EST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) |
| 922 #define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 |
| 923 #define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 |
| 924 #define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff |
| 925 #define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN
_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) |
| 926 #define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PI
N_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) |
| 927 |
| 928 |
| 929 #ifndef __ASSEMBLER__ |
| 930 |
| 931 typedef struct gpio_reg_reg_s { |
| 932 volatile unsigned int gpio_out; |
| 933 volatile unsigned int gpio_out_w1ts; |
| 934 volatile unsigned int gpio_out_w1tc; |
| 935 volatile unsigned int gpio_enable; |
| 936 volatile unsigned int gpio_enable_w1ts; |
| 937 volatile unsigned int gpio_enable_w1tc; |
| 938 volatile unsigned int gpio_in; |
| 939 volatile unsigned int gpio_status; |
| 940 volatile unsigned int gpio_status_w1ts; |
| 941 volatile unsigned int gpio_status_w1tc; |
| 942 volatile unsigned int gpio_pin0; |
| 943 volatile unsigned int gpio_pin1; |
| 944 volatile unsigned int gpio_pin2; |
| 945 volatile unsigned int gpio_pin3; |
| 946 volatile unsigned int gpio_pin4; |
| 947 volatile unsigned int gpio_pin5; |
| 948 volatile unsigned int gpio_pin6; |
| 949 volatile unsigned int gpio_pin7; |
| 950 volatile unsigned int gpio_pin8; |
| 951 volatile unsigned int gpio_pin9; |
| 952 volatile unsigned int gpio_pin10; |
| 953 volatile unsigned int gpio_pin11; |
| 954 volatile unsigned int gpio_pin12; |
| 955 volatile unsigned int gpio_pin13; |
| 956 volatile unsigned int gpio_pin14; |
| 957 volatile unsigned int gpio_pin15; |
| 958 volatile unsigned int gpio_pin16; |
| 959 volatile unsigned int gpio_pin17; |
| 960 volatile unsigned int sdio_pin; |
| 961 volatile unsigned int clk_req_pin; |
| 962 volatile unsigned int sigma_delta; |
| 963 volatile unsigned int debug_control; |
| 964 volatile unsigned int debug_input_sel; |
| 965 volatile unsigned int debug_out; |
| 966 volatile unsigned int la_control; |
| 967 volatile unsigned int la_clock; |
| 968 volatile unsigned int la_status; |
| 969 volatile unsigned int la_trigger_sample; |
| 970 volatile unsigned int la_trigger_position; |
| 971 volatile unsigned int la_pre_trigger; |
| 972 volatile unsigned int la_post_trigger; |
| 973 volatile unsigned int la_filter_control; |
| 974 volatile unsigned int la_filter_data; |
| 975 volatile unsigned int la_filter_wildcard; |
| 976 volatile unsigned int la_triggera_data; |
| 977 volatile unsigned int la_triggera_wildcard; |
| 978 volatile unsigned int la_triggerb_data; |
| 979 volatile unsigned int la_triggerb_wildcard; |
| 980 volatile unsigned int la_trigger; |
| 981 volatile unsigned int la_fifo; |
| 982 volatile unsigned int la[2]; |
| 983 volatile unsigned int ant_pin; |
| 984 volatile unsigned int antd_pin; |
| 985 volatile unsigned int gpio_pin; |
| 986 volatile unsigned int gpio_h_pin; |
| 987 volatile unsigned int bt_pin; |
| 988 volatile unsigned int bt_wlan_pin; |
| 989 volatile unsigned int si_uart_pin; |
| 990 volatile unsigned int clk32k_pin; |
| 991 volatile unsigned int reset_tuple_status; |
| 992 } gpio_reg_reg_t; |
| 993 |
| 994 #endif /* __ASSEMBLER__ */ |
| 995 |
| 996 #endif /* _GPIO_REG_H_ */ |
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