OLD | NEW |
(Empty) | |
| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _RTC_REG_REG_H_ |
| 21 #define _RTC_REG_REG_H_ |
| 22 |
| 23 #define RESET_CONTROL_ADDRESS 0x00000000 |
| 24 #define RESET_CONTROL_OFFSET 0x00000000 |
| 25 #define RESET_CONTROL_CPU_INIT_RESET_MSB 11 |
| 26 #define RESET_CONTROL_CPU_INIT_RESET_LSB 11 |
| 27 #define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 |
| 28 #define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_
RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) |
| 29 #define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT
_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) |
| 30 #define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 |
| 31 #define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 |
| 32 #define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 |
| 33 #define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP
_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) |
| 34 #define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMA
P_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) |
| 35 #define RESET_CONTROL_RST_OUT_MSB 9 |
| 36 #define RESET_CONTROL_RST_OUT_LSB 9 |
| 37 #define RESET_CONTROL_RST_OUT_MASK 0x00000200 |
| 38 #define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_M
ASK) >> RESET_CONTROL_RST_OUT_LSB) |
| 39 #define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_
LSB) & RESET_CONTROL_RST_OUT_MASK) |
| 40 #define RESET_CONTROL_COLD_RST_MSB 8 |
| 41 #define RESET_CONTROL_COLD_RST_LSB 8 |
| 42 #define RESET_CONTROL_COLD_RST_MASK 0x00000100 |
| 43 #define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_
MASK) >> RESET_CONTROL_COLD_RST_LSB) |
| 44 #define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST
_LSB) & RESET_CONTROL_COLD_RST_MASK) |
| 45 #define RESET_CONTROL_WARM_RST_MSB 7 |
| 46 #define RESET_CONTROL_WARM_RST_LSB 7 |
| 47 #define RESET_CONTROL_WARM_RST_MASK 0x00000080 |
| 48 #define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_
MASK) >> RESET_CONTROL_WARM_RST_LSB) |
| 49 #define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST
_LSB) & RESET_CONTROL_WARM_RST_MASK) |
| 50 #define RESET_CONTROL_CPU_WARM_RST_MSB 6 |
| 51 #define RESET_CONTROL_CPU_WARM_RST_LSB 6 |
| 52 #define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
| 53 #define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_
RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) |
| 54 #define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM
_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) |
| 55 #define RESET_CONTROL_MAC_COLD_RST_MSB 5 |
| 56 #define RESET_CONTROL_MAC_COLD_RST_LSB 5 |
| 57 #define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 |
| 58 #define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_
RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) |
| 59 #define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD
_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) |
| 60 #define RESET_CONTROL_MAC_WARM_RST_MSB 4 |
| 61 #define RESET_CONTROL_MAC_WARM_RST_LSB 4 |
| 62 #define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 |
| 63 #define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_
RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) |
| 64 #define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM
_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) |
| 65 #define RESET_CONTROL_MBOX_RST_MSB 2 |
| 66 #define RESET_CONTROL_MBOX_RST_LSB 2 |
| 67 #define RESET_CONTROL_MBOX_RST_MASK 0x00000004 |
| 68 #define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_
MASK) >> RESET_CONTROL_MBOX_RST_LSB) |
| 69 #define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST
_LSB) & RESET_CONTROL_MBOX_RST_MASK) |
| 70 #define RESET_CONTROL_UART_RST_MSB 1 |
| 71 #define RESET_CONTROL_UART_RST_LSB 1 |
| 72 #define RESET_CONTROL_UART_RST_MASK 0x00000002 |
| 73 #define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_
MASK) >> RESET_CONTROL_UART_RST_LSB) |
| 74 #define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST
_LSB) & RESET_CONTROL_UART_RST_MASK) |
| 75 #define RESET_CONTROL_SI0_RST_MSB 0 |
| 76 #define RESET_CONTROL_SI0_RST_LSB 0 |
| 77 #define RESET_CONTROL_SI0_RST_MASK 0x00000001 |
| 78 #define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_M
ASK) >> RESET_CONTROL_SI0_RST_LSB) |
| 79 #define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_
LSB) & RESET_CONTROL_SI0_RST_MASK) |
| 80 |
| 81 #define XTAL_CONTROL_ADDRESS 0x00000004 |
| 82 #define XTAL_CONTROL_OFFSET 0x00000004 |
| 83 #define XTAL_CONTROL_TCXO_MSB 0 |
| 84 #define XTAL_CONTROL_TCXO_LSB 0 |
| 85 #define XTAL_CONTROL_TCXO_MASK 0x00000001 |
| 86 #define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK)
>> XTAL_CONTROL_TCXO_LSB) |
| 87 #define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB)
& XTAL_CONTROL_TCXO_MASK) |
| 88 |
| 89 #define TCXO_DETECT_ADDRESS 0x00000008 |
| 90 #define TCXO_DETECT_OFFSET 0x00000008 |
| 91 #define TCXO_DETECT_PRESENT_MSB 0 |
| 92 #define TCXO_DETECT_PRESENT_LSB 0 |
| 93 #define TCXO_DETECT_PRESENT_MASK 0x00000001 |
| 94 #define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MAS
K) >> TCXO_DETECT_PRESENT_LSB) |
| 95 #define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LS
B) & TCXO_DETECT_PRESENT_MASK) |
| 96 |
| 97 #define XTAL_TEST_ADDRESS 0x0000000c |
| 98 #define XTAL_TEST_OFFSET 0x0000000c |
| 99 #define XTAL_TEST_NOTCXODET_MSB 0 |
| 100 #define XTAL_TEST_NOTCXODET_LSB 0 |
| 101 #define XTAL_TEST_NOTCXODET_MASK 0x00000001 |
| 102 #define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MAS
K) >> XTAL_TEST_NOTCXODET_LSB) |
| 103 #define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LS
B) & XTAL_TEST_NOTCXODET_MASK) |
| 104 |
| 105 #define QUADRATURE_ADDRESS 0x00000010 |
| 106 #define QUADRATURE_OFFSET 0x00000010 |
| 107 #define QUADRATURE_ADC_MSB 5 |
| 108 #define QUADRATURE_ADC_LSB 4 |
| 109 #define QUADRATURE_ADC_MASK 0x00000030 |
| 110 #define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >>
QUADRATURE_ADC_LSB) |
| 111 #define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) &
QUADRATURE_ADC_MASK) |
| 112 #define QUADRATURE_SEL_MSB 2 |
| 113 #define QUADRATURE_SEL_LSB 2 |
| 114 #define QUADRATURE_SEL_MASK 0x00000004 |
| 115 #define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >>
QUADRATURE_SEL_LSB) |
| 116 #define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) &
QUADRATURE_SEL_MASK) |
| 117 #define QUADRATURE_DAC_MSB 1 |
| 118 #define QUADRATURE_DAC_LSB 0 |
| 119 #define QUADRATURE_DAC_MASK 0x00000003 |
| 120 #define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >>
QUADRATURE_DAC_LSB) |
| 121 #define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) &
QUADRATURE_DAC_MASK) |
| 122 |
| 123 #define PLL_CONTROL_ADDRESS 0x00000014 |
| 124 #define PLL_CONTROL_OFFSET 0x00000014 |
| 125 #define PLL_CONTROL_DIG_TEST_CLK_MSB 20 |
| 126 #define PLL_CONTROL_DIG_TEST_CLK_LSB 20 |
| 127 #define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 |
| 128 #define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CL
K_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) |
| 129 #define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_C
LK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) |
| 130 #define PLL_CONTROL_MAC_OVERRIDE_MSB 19 |
| 131 #define PLL_CONTROL_MAC_OVERRIDE_LSB 19 |
| 132 #define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 |
| 133 #define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRID
E_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) |
| 134 #define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRI
DE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) |
| 135 #define PLL_CONTROL_NOPWD_MSB 18 |
| 136 #define PLL_CONTROL_NOPWD_LSB 18 |
| 137 #define PLL_CONTROL_NOPWD_MASK 0x00040000 |
| 138 #define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK)
>> PLL_CONTROL_NOPWD_LSB) |
| 139 #define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB)
& PLL_CONTROL_NOPWD_MASK) |
| 140 #define PLL_CONTROL_UPDATING_MSB 17 |
| 141 #define PLL_CONTROL_UPDATING_LSB 17 |
| 142 #define PLL_CONTROL_UPDATING_MASK 0x00020000 |
| 143 #define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MA
SK) >> PLL_CONTROL_UPDATING_LSB) |
| 144 #define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_L
SB) & PLL_CONTROL_UPDATING_MASK) |
| 145 #define PLL_CONTROL_BYPASS_MSB 16 |
| 146 #define PLL_CONTROL_BYPASS_LSB 16 |
| 147 #define PLL_CONTROL_BYPASS_MASK 0x00010000 |
| 148 #define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK
) >> PLL_CONTROL_BYPASS_LSB) |
| 149 #define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB
) & PLL_CONTROL_BYPASS_MASK) |
| 150 #define PLL_CONTROL_REFDIV_MSB 15 |
| 151 #define PLL_CONTROL_REFDIV_LSB 12 |
| 152 #define PLL_CONTROL_REFDIV_MASK 0x0000f000 |
| 153 #define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK
) >> PLL_CONTROL_REFDIV_LSB) |
| 154 #define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB
) & PLL_CONTROL_REFDIV_MASK) |
| 155 #define PLL_CONTROL_DIV_MSB 9 |
| 156 #define PLL_CONTROL_DIV_LSB 0 |
| 157 #define PLL_CONTROL_DIV_MASK 0x000003ff |
| 158 #define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >
> PLL_CONTROL_DIV_LSB) |
| 159 #define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) &
PLL_CONTROL_DIV_MASK) |
| 160 |
| 161 #define PLL_SETTLE_ADDRESS 0x00000018 |
| 162 #define PLL_SETTLE_OFFSET 0x00000018 |
| 163 #define PLL_SETTLE_TIME_MSB 11 |
| 164 #define PLL_SETTLE_TIME_LSB 0 |
| 165 #define PLL_SETTLE_TIME_MASK 0x00000fff |
| 166 #define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >
> PLL_SETTLE_TIME_LSB) |
| 167 #define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) &
PLL_SETTLE_TIME_MASK) |
| 168 |
| 169 #define XTAL_SETTLE_ADDRESS 0x0000001c |
| 170 #define XTAL_SETTLE_OFFSET 0x0000001c |
| 171 #define XTAL_SETTLE_TIME_MSB 7 |
| 172 #define XTAL_SETTLE_TIME_LSB 0 |
| 173 #define XTAL_SETTLE_TIME_MASK 0x000000ff |
| 174 #define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK)
>> XTAL_SETTLE_TIME_LSB) |
| 175 #define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB)
& XTAL_SETTLE_TIME_MASK) |
| 176 |
| 177 #define CPU_CLOCK_ADDRESS 0x00000020 |
| 178 #define CPU_CLOCK_OFFSET 0x00000020 |
| 179 #define CPU_CLOCK_STANDARD_MSB 1 |
| 180 #define CPU_CLOCK_STANDARD_LSB 0 |
| 181 #define CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 182 #define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK
) >> CPU_CLOCK_STANDARD_LSB) |
| 183 #define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB
) & CPU_CLOCK_STANDARD_MASK) |
| 184 |
| 185 #define CLOCK_OUT_ADDRESS 0x00000024 |
| 186 #define CLOCK_OUT_OFFSET 0x00000024 |
| 187 #define CLOCK_OUT_SELECT_MSB 3 |
| 188 #define CLOCK_OUT_SELECT_LSB 0 |
| 189 #define CLOCK_OUT_SELECT_MASK 0x0000000f |
| 190 #define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK)
>> CLOCK_OUT_SELECT_LSB) |
| 191 #define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB)
& CLOCK_OUT_SELECT_MASK) |
| 192 |
| 193 #define CLOCK_CONTROL_ADDRESS 0x00000028 |
| 194 #define CLOCK_CONTROL_OFFSET 0x00000028 |
| 195 #define CLOCK_CONTROL_LF_CLK32_MSB 2 |
| 196 #define CLOCK_CONTROL_LF_CLK32_LSB 2 |
| 197 #define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 |
| 198 #define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_
MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) |
| 199 #define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32
_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) |
| 200 #define CLOCK_CONTROL_UART_CLK_MSB 1 |
| 201 #define CLOCK_CONTROL_UART_CLK_LSB 1 |
| 202 #define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 |
| 203 #define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_
MASK) >> CLOCK_CONTROL_UART_CLK_LSB) |
| 204 #define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK
_LSB) & CLOCK_CONTROL_UART_CLK_MASK) |
| 205 #define CLOCK_CONTROL_SI0_CLK_MSB 0 |
| 206 #define CLOCK_CONTROL_SI0_CLK_LSB 0 |
| 207 #define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| 208 #define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_M
ASK) >> CLOCK_CONTROL_SI0_CLK_LSB) |
| 209 #define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_
LSB) & CLOCK_CONTROL_SI0_CLK_MASK) |
| 210 |
| 211 #define BIAS_OVERRIDE_ADDRESS 0x0000002c |
| 212 #define BIAS_OVERRIDE_OFFSET 0x0000002c |
| 213 #define BIAS_OVERRIDE_ON_MSB 0 |
| 214 #define BIAS_OVERRIDE_ON_LSB 0 |
| 215 #define BIAS_OVERRIDE_ON_MASK 0x00000001 |
| 216 #define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK)
>> BIAS_OVERRIDE_ON_LSB) |
| 217 #define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB)
& BIAS_OVERRIDE_ON_MASK) |
| 218 |
| 219 #define WDT_CONTROL_ADDRESS 0x00000030 |
| 220 #define WDT_CONTROL_OFFSET 0x00000030 |
| 221 #define WDT_CONTROL_ACTION_MSB 2 |
| 222 #define WDT_CONTROL_ACTION_LSB 0 |
| 223 #define WDT_CONTROL_ACTION_MASK 0x00000007 |
| 224 #define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK
) >> WDT_CONTROL_ACTION_LSB) |
| 225 #define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB
) & WDT_CONTROL_ACTION_MASK) |
| 226 |
| 227 #define WDT_STATUS_ADDRESS 0x00000034 |
| 228 #define WDT_STATUS_OFFSET 0x00000034 |
| 229 #define WDT_STATUS_INTERRUPT_MSB 0 |
| 230 #define WDT_STATUS_INTERRUPT_LSB 0 |
| 231 #define WDT_STATUS_INTERRUPT_MASK 0x00000001 |
| 232 #define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MA
SK) >> WDT_STATUS_INTERRUPT_LSB) |
| 233 #define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_L
SB) & WDT_STATUS_INTERRUPT_MASK) |
| 234 |
| 235 #define WDT_ADDRESS 0x00000038 |
| 236 #define WDT_OFFSET 0x00000038 |
| 237 #define WDT_TARGET_MSB 21 |
| 238 #define WDT_TARGET_LSB 0 |
| 239 #define WDT_TARGET_MASK 0x003fffff |
| 240 #define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT
_TARGET_LSB) |
| 241 #define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_
TARGET_MASK) |
| 242 |
| 243 #define WDT_COUNT_ADDRESS 0x0000003c |
| 244 #define WDT_COUNT_OFFSET 0x0000003c |
| 245 #define WDT_COUNT_VALUE_MSB 21 |
| 246 #define WDT_COUNT_VALUE_LSB 0 |
| 247 #define WDT_COUNT_VALUE_MASK 0x003fffff |
| 248 #define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >
> WDT_COUNT_VALUE_LSB) |
| 249 #define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) &
WDT_COUNT_VALUE_MASK) |
| 250 |
| 251 #define WDT_RESET_ADDRESS 0x00000040 |
| 252 #define WDT_RESET_OFFSET 0x00000040 |
| 253 #define WDT_RESET_VALUE_MSB 0 |
| 254 #define WDT_RESET_VALUE_LSB 0 |
| 255 #define WDT_RESET_VALUE_MASK 0x00000001 |
| 256 #define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >
> WDT_RESET_VALUE_LSB) |
| 257 #define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) &
WDT_RESET_VALUE_MASK) |
| 258 |
| 259 #define INT_STATUS_ADDRESS 0x00000044 |
| 260 #define INT_STATUS_OFFSET 0x00000044 |
| 261 #define INT_STATUS_RTC_POWER_MSB 14 |
| 262 #define INT_STATUS_RTC_POWER_LSB 14 |
| 263 #define INT_STATUS_RTC_POWER_MASK 0x00004000 |
| 264 #define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MA
SK) >> INT_STATUS_RTC_POWER_LSB) |
| 265 #define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_L
SB) & INT_STATUS_RTC_POWER_MASK) |
| 266 #define INT_STATUS_MAC_MSB 13 |
| 267 #define INT_STATUS_MAC_LSB 13 |
| 268 #define INT_STATUS_MAC_MASK 0x00002000 |
| 269 #define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >>
INT_STATUS_MAC_LSB) |
| 270 #define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) &
INT_STATUS_MAC_MASK) |
| 271 #define INT_STATUS_MAILBOX_MSB 12 |
| 272 #define INT_STATUS_MAILBOX_LSB 12 |
| 273 #define INT_STATUS_MAILBOX_MASK 0x00001000 |
| 274 #define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK
) >> INT_STATUS_MAILBOX_LSB) |
| 275 #define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB
) & INT_STATUS_MAILBOX_MASK) |
| 276 #define INT_STATUS_RTC_ALARM_MSB 11 |
| 277 #define INT_STATUS_RTC_ALARM_LSB 11 |
| 278 #define INT_STATUS_RTC_ALARM_MASK 0x00000800 |
| 279 #define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MA
SK) >> INT_STATUS_RTC_ALARM_LSB) |
| 280 #define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_L
SB) & INT_STATUS_RTC_ALARM_MASK) |
| 281 #define INT_STATUS_HF_TIMER_MSB 10 |
| 282 #define INT_STATUS_HF_TIMER_LSB 10 |
| 283 #define INT_STATUS_HF_TIMER_MASK 0x00000400 |
| 284 #define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MAS
K) >> INT_STATUS_HF_TIMER_LSB) |
| 285 #define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LS
B) & INT_STATUS_HF_TIMER_MASK) |
| 286 #define INT_STATUS_LF_TIMER3_MSB 9 |
| 287 #define INT_STATUS_LF_TIMER3_LSB 9 |
| 288 #define INT_STATUS_LF_TIMER3_MASK 0x00000200 |
| 289 #define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MA
SK) >> INT_STATUS_LF_TIMER3_LSB) |
| 290 #define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_L
SB) & INT_STATUS_LF_TIMER3_MASK) |
| 291 #define INT_STATUS_LF_TIMER2_MSB 8 |
| 292 #define INT_STATUS_LF_TIMER2_LSB 8 |
| 293 #define INT_STATUS_LF_TIMER2_MASK 0x00000100 |
| 294 #define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MA
SK) >> INT_STATUS_LF_TIMER2_LSB) |
| 295 #define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_L
SB) & INT_STATUS_LF_TIMER2_MASK) |
| 296 #define INT_STATUS_LF_TIMER1_MSB 7 |
| 297 #define INT_STATUS_LF_TIMER1_LSB 7 |
| 298 #define INT_STATUS_LF_TIMER1_MASK 0x00000080 |
| 299 #define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MA
SK) >> INT_STATUS_LF_TIMER1_LSB) |
| 300 #define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_L
SB) & INT_STATUS_LF_TIMER1_MASK) |
| 301 #define INT_STATUS_LF_TIMER0_MSB 6 |
| 302 #define INT_STATUS_LF_TIMER0_LSB 6 |
| 303 #define INT_STATUS_LF_TIMER0_MASK 0x00000040 |
| 304 #define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MA
SK) >> INT_STATUS_LF_TIMER0_LSB) |
| 305 #define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_L
SB) & INT_STATUS_LF_TIMER0_MASK) |
| 306 #define INT_STATUS_KEYPAD_MSB 5 |
| 307 #define INT_STATUS_KEYPAD_LSB 5 |
| 308 #define INT_STATUS_KEYPAD_MASK 0x00000020 |
| 309 #define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK)
>> INT_STATUS_KEYPAD_LSB) |
| 310 #define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB)
& INT_STATUS_KEYPAD_MASK) |
| 311 #define INT_STATUS_SI_MSB 4 |
| 312 #define INT_STATUS_SI_LSB 4 |
| 313 #define INT_STATUS_SI_MASK 0x00000010 |
| 314 #define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >>
INT_STATUS_SI_LSB) |
| 315 #define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & I
NT_STATUS_SI_MASK) |
| 316 #define INT_STATUS_GPIO_MSB 3 |
| 317 #define INT_STATUS_GPIO_LSB 3 |
| 318 #define INT_STATUS_GPIO_MASK 0x00000008 |
| 319 #define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >
> INT_STATUS_GPIO_LSB) |
| 320 #define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) &
INT_STATUS_GPIO_MASK) |
| 321 #define INT_STATUS_UART_MSB 2 |
| 322 #define INT_STATUS_UART_LSB 2 |
| 323 #define INT_STATUS_UART_MASK 0x00000004 |
| 324 #define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >
> INT_STATUS_UART_LSB) |
| 325 #define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) &
INT_STATUS_UART_MASK) |
| 326 #define INT_STATUS_ERROR_MSB 1 |
| 327 #define INT_STATUS_ERROR_LSB 1 |
| 328 #define INT_STATUS_ERROR_MASK 0x00000002 |
| 329 #define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK)
>> INT_STATUS_ERROR_LSB) |
| 330 #define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB)
& INT_STATUS_ERROR_MASK) |
| 331 #define INT_STATUS_WDT_INT_MSB 0 |
| 332 #define INT_STATUS_WDT_INT_LSB 0 |
| 333 #define INT_STATUS_WDT_INT_MASK 0x00000001 |
| 334 #define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK
) >> INT_STATUS_WDT_INT_LSB) |
| 335 #define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB
) & INT_STATUS_WDT_INT_MASK) |
| 336 |
| 337 #define LF_TIMER0_ADDRESS 0x00000048 |
| 338 #define LF_TIMER0_OFFSET 0x00000048 |
| 339 #define LF_TIMER0_TARGET_MSB 31 |
| 340 #define LF_TIMER0_TARGET_LSB 0 |
| 341 #define LF_TIMER0_TARGET_MASK 0xffffffff |
| 342 #define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK)
>> LF_TIMER0_TARGET_LSB) |
| 343 #define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB)
& LF_TIMER0_TARGET_MASK) |
| 344 |
| 345 #define LF_TIMER_COUNT0_ADDRESS 0x0000004c |
| 346 #define LF_TIMER_COUNT0_OFFSET 0x0000004c |
| 347 #define LF_TIMER_COUNT0_VALUE_MSB 31 |
| 348 #define LF_TIMER_COUNT0_VALUE_LSB 0 |
| 349 #define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff |
| 350 #define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_M
ASK) >> LF_TIMER_COUNT0_VALUE_LSB) |
| 351 #define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_
LSB) & LF_TIMER_COUNT0_VALUE_MASK) |
| 352 |
| 353 #define LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
| 354 #define LF_TIMER_CONTROL0_OFFSET 0x00000050 |
| 355 #define LF_TIMER_CONTROL0_ENABLE_MSB 2 |
| 356 #define LF_TIMER_CONTROL0_ENABLE_LSB 2 |
| 357 #define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 |
| 358 #define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABL
E_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) |
| 359 #define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENAB
LE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) |
| 360 #define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 |
| 361 #define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 |
| 362 #define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 |
| 363 #define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_
RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) |
| 364 #define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO
_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) |
| 365 #define LF_TIMER_CONTROL0_RESET_MSB 0 |
| 366 #define LF_TIMER_CONTROL0_RESET_LSB 0 |
| 367 #define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 |
| 368 #define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET
_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) |
| 369 #define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESE
T_LSB) & LF_TIMER_CONTROL0_RESET_MASK) |
| 370 |
| 371 #define LF_TIMER_STATUS0_ADDRESS 0x00000054 |
| 372 #define LF_TIMER_STATUS0_OFFSET 0x00000054 |
| 373 #define LF_TIMER_STATUS0_INTERRUPT_MSB 0 |
| 374 #define LF_TIMER_STATUS0_INTERRUPT_LSB 0 |
| 375 #define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 |
| 376 #define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERR
UPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) |
| 377 #define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTER
RUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) |
| 378 |
| 379 #define LF_TIMER1_ADDRESS 0x00000058 |
| 380 #define LF_TIMER1_OFFSET 0x00000058 |
| 381 #define LF_TIMER1_TARGET_MSB 31 |
| 382 #define LF_TIMER1_TARGET_LSB 0 |
| 383 #define LF_TIMER1_TARGET_MASK 0xffffffff |
| 384 #define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK)
>> LF_TIMER1_TARGET_LSB) |
| 385 #define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB)
& LF_TIMER1_TARGET_MASK) |
| 386 |
| 387 #define LF_TIMER_COUNT1_ADDRESS 0x0000005c |
| 388 #define LF_TIMER_COUNT1_OFFSET 0x0000005c |
| 389 #define LF_TIMER_COUNT1_VALUE_MSB 31 |
| 390 #define LF_TIMER_COUNT1_VALUE_LSB 0 |
| 391 #define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff |
| 392 #define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_M
ASK) >> LF_TIMER_COUNT1_VALUE_LSB) |
| 393 #define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_
LSB) & LF_TIMER_COUNT1_VALUE_MASK) |
| 394 |
| 395 #define LF_TIMER_CONTROL1_ADDRESS 0x00000060 |
| 396 #define LF_TIMER_CONTROL1_OFFSET 0x00000060 |
| 397 #define LF_TIMER_CONTROL1_ENABLE_MSB 2 |
| 398 #define LF_TIMER_CONTROL1_ENABLE_LSB 2 |
| 399 #define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 |
| 400 #define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABL
E_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) |
| 401 #define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENAB
LE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) |
| 402 #define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 |
| 403 #define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 |
| 404 #define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 |
| 405 #define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_
RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) |
| 406 #define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO
_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) |
| 407 #define LF_TIMER_CONTROL1_RESET_MSB 0 |
| 408 #define LF_TIMER_CONTROL1_RESET_LSB 0 |
| 409 #define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 |
| 410 #define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET
_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) |
| 411 #define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESE
T_LSB) & LF_TIMER_CONTROL1_RESET_MASK) |
| 412 |
| 413 #define LF_TIMER_STATUS1_ADDRESS 0x00000064 |
| 414 #define LF_TIMER_STATUS1_OFFSET 0x00000064 |
| 415 #define LF_TIMER_STATUS1_INTERRUPT_MSB 0 |
| 416 #define LF_TIMER_STATUS1_INTERRUPT_LSB 0 |
| 417 #define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 |
| 418 #define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERR
UPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) |
| 419 #define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTER
RUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) |
| 420 |
| 421 #define LF_TIMER2_ADDRESS 0x00000068 |
| 422 #define LF_TIMER2_OFFSET 0x00000068 |
| 423 #define LF_TIMER2_TARGET_MSB 31 |
| 424 #define LF_TIMER2_TARGET_LSB 0 |
| 425 #define LF_TIMER2_TARGET_MASK 0xffffffff |
| 426 #define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK)
>> LF_TIMER2_TARGET_LSB) |
| 427 #define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB)
& LF_TIMER2_TARGET_MASK) |
| 428 |
| 429 #define LF_TIMER_COUNT2_ADDRESS 0x0000006c |
| 430 #define LF_TIMER_COUNT2_OFFSET 0x0000006c |
| 431 #define LF_TIMER_COUNT2_VALUE_MSB 31 |
| 432 #define LF_TIMER_COUNT2_VALUE_LSB 0 |
| 433 #define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff |
| 434 #define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_M
ASK) >> LF_TIMER_COUNT2_VALUE_LSB) |
| 435 #define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_
LSB) & LF_TIMER_COUNT2_VALUE_MASK) |
| 436 |
| 437 #define LF_TIMER_CONTROL2_ADDRESS 0x00000070 |
| 438 #define LF_TIMER_CONTROL2_OFFSET 0x00000070 |
| 439 #define LF_TIMER_CONTROL2_ENABLE_MSB 2 |
| 440 #define LF_TIMER_CONTROL2_ENABLE_LSB 2 |
| 441 #define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 |
| 442 #define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABL
E_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) |
| 443 #define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENAB
LE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) |
| 444 #define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 |
| 445 #define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 |
| 446 #define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 |
| 447 #define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_
RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) |
| 448 #define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO
_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) |
| 449 #define LF_TIMER_CONTROL2_RESET_MSB 0 |
| 450 #define LF_TIMER_CONTROL2_RESET_LSB 0 |
| 451 #define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 |
| 452 #define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET
_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) |
| 453 #define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESE
T_LSB) & LF_TIMER_CONTROL2_RESET_MASK) |
| 454 |
| 455 #define LF_TIMER_STATUS2_ADDRESS 0x00000074 |
| 456 #define LF_TIMER_STATUS2_OFFSET 0x00000074 |
| 457 #define LF_TIMER_STATUS2_INTERRUPT_MSB 0 |
| 458 #define LF_TIMER_STATUS2_INTERRUPT_LSB 0 |
| 459 #define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 |
| 460 #define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERR
UPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) |
| 461 #define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTER
RUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) |
| 462 |
| 463 #define LF_TIMER3_ADDRESS 0x00000078 |
| 464 #define LF_TIMER3_OFFSET 0x00000078 |
| 465 #define LF_TIMER3_TARGET_MSB 31 |
| 466 #define LF_TIMER3_TARGET_LSB 0 |
| 467 #define LF_TIMER3_TARGET_MASK 0xffffffff |
| 468 #define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK)
>> LF_TIMER3_TARGET_LSB) |
| 469 #define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB)
& LF_TIMER3_TARGET_MASK) |
| 470 |
| 471 #define LF_TIMER_COUNT3_ADDRESS 0x0000007c |
| 472 #define LF_TIMER_COUNT3_OFFSET 0x0000007c |
| 473 #define LF_TIMER_COUNT3_VALUE_MSB 31 |
| 474 #define LF_TIMER_COUNT3_VALUE_LSB 0 |
| 475 #define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff |
| 476 #define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_M
ASK) >> LF_TIMER_COUNT3_VALUE_LSB) |
| 477 #define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_
LSB) & LF_TIMER_COUNT3_VALUE_MASK) |
| 478 |
| 479 #define LF_TIMER_CONTROL3_ADDRESS 0x00000080 |
| 480 #define LF_TIMER_CONTROL3_OFFSET 0x00000080 |
| 481 #define LF_TIMER_CONTROL3_ENABLE_MSB 2 |
| 482 #define LF_TIMER_CONTROL3_ENABLE_LSB 2 |
| 483 #define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 |
| 484 #define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABL
E_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) |
| 485 #define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENAB
LE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) |
| 486 #define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 |
| 487 #define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 |
| 488 #define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 |
| 489 #define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_
RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) |
| 490 #define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO
_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) |
| 491 #define LF_TIMER_CONTROL3_RESET_MSB 0 |
| 492 #define LF_TIMER_CONTROL3_RESET_LSB 0 |
| 493 #define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 |
| 494 #define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET
_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) |
| 495 #define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESE
T_LSB) & LF_TIMER_CONTROL3_RESET_MASK) |
| 496 |
| 497 #define LF_TIMER_STATUS3_ADDRESS 0x00000084 |
| 498 #define LF_TIMER_STATUS3_OFFSET 0x00000084 |
| 499 #define LF_TIMER_STATUS3_INTERRUPT_MSB 0 |
| 500 #define LF_TIMER_STATUS3_INTERRUPT_LSB 0 |
| 501 #define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 |
| 502 #define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERR
UPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) |
| 503 #define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTER
RUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) |
| 504 |
| 505 #define HF_TIMER_ADDRESS 0x00000088 |
| 506 #define HF_TIMER_OFFSET 0x00000088 |
| 507 #define HF_TIMER_TARGET_MSB 31 |
| 508 #define HF_TIMER_TARGET_LSB 12 |
| 509 #define HF_TIMER_TARGET_MASK 0xfffff000 |
| 510 #define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >
> HF_TIMER_TARGET_LSB) |
| 511 #define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) &
HF_TIMER_TARGET_MASK) |
| 512 |
| 513 #define HF_TIMER_COUNT_ADDRESS 0x0000008c |
| 514 #define HF_TIMER_COUNT_OFFSET 0x0000008c |
| 515 #define HF_TIMER_COUNT_VALUE_MSB 31 |
| 516 #define HF_TIMER_COUNT_VALUE_LSB 12 |
| 517 #define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 |
| 518 #define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MA
SK) >> HF_TIMER_COUNT_VALUE_LSB) |
| 519 #define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_L
SB) & HF_TIMER_COUNT_VALUE_MASK) |
| 520 |
| 521 #define HF_LF_COUNT_ADDRESS 0x00000090 |
| 522 #define HF_LF_COUNT_OFFSET 0x00000090 |
| 523 #define HF_LF_COUNT_VALUE_MSB 31 |
| 524 #define HF_LF_COUNT_VALUE_LSB 0 |
| 525 #define HF_LF_COUNT_VALUE_MASK 0xffffffff |
| 526 #define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK)
>> HF_LF_COUNT_VALUE_LSB) |
| 527 #define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB)
& HF_LF_COUNT_VALUE_MASK) |
| 528 |
| 529 #define HF_TIMER_CONTROL_ADDRESS 0x00000094 |
| 530 #define HF_TIMER_CONTROL_OFFSET 0x00000094 |
| 531 #define HF_TIMER_CONTROL_ENABLE_MSB 3 |
| 532 #define HF_TIMER_CONTROL_ENABLE_LSB 3 |
| 533 #define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 |
| 534 #define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE
_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) |
| 535 #define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABL
E_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) |
| 536 #define HF_TIMER_CONTROL_ON_MSB 2 |
| 537 #define HF_TIMER_CONTROL_ON_LSB 2 |
| 538 #define HF_TIMER_CONTROL_ON_MASK 0x00000004 |
| 539 #define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MAS
K) >> HF_TIMER_CONTROL_ON_LSB) |
| 540 #define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LS
B) & HF_TIMER_CONTROL_ON_MASK) |
| 541 #define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 |
| 542 #define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 |
| 543 #define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 |
| 544 #define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_R
ESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) |
| 545 #define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_
RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) |
| 546 #define HF_TIMER_CONTROL_RESET_MSB 0 |
| 547 #define HF_TIMER_CONTROL_RESET_LSB 0 |
| 548 #define HF_TIMER_CONTROL_RESET_MASK 0x00000001 |
| 549 #define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_
MASK) >> HF_TIMER_CONTROL_RESET_LSB) |
| 550 #define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET
_LSB) & HF_TIMER_CONTROL_RESET_MASK) |
| 551 |
| 552 #define HF_TIMER_STATUS_ADDRESS 0x00000098 |
| 553 #define HF_TIMER_STATUS_OFFSET 0x00000098 |
| 554 #define HF_TIMER_STATUS_INTERRUPT_MSB 0 |
| 555 #define HF_TIMER_STATUS_INTERRUPT_LSB 0 |
| 556 #define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 |
| 557 #define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRU
PT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) |
| 558 #define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERR
UPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) |
| 559 |
| 560 #define RTC_CONTROL_ADDRESS 0x0000009c |
| 561 #define RTC_CONTROL_OFFSET 0x0000009c |
| 562 #define RTC_CONTROL_ENABLE_MSB 2 |
| 563 #define RTC_CONTROL_ENABLE_LSB 2 |
| 564 #define RTC_CONTROL_ENABLE_MASK 0x00000004 |
| 565 #define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK
) >> RTC_CONTROL_ENABLE_LSB) |
| 566 #define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB
) & RTC_CONTROL_ENABLE_MASK) |
| 567 #define RTC_CONTROL_LOAD_RTC_MSB 1 |
| 568 #define RTC_CONTROL_LOAD_RTC_LSB 1 |
| 569 #define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 |
| 570 #define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MA
SK) >> RTC_CONTROL_LOAD_RTC_LSB) |
| 571 #define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_L
SB) & RTC_CONTROL_LOAD_RTC_MASK) |
| 572 #define RTC_CONTROL_LOAD_ALARM_MSB 0 |
| 573 #define RTC_CONTROL_LOAD_ALARM_LSB 0 |
| 574 #define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 |
| 575 #define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_
MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) |
| 576 #define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM
_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) |
| 577 |
| 578 #define RTC_TIME_ADDRESS 0x000000a0 |
| 579 #define RTC_TIME_OFFSET 0x000000a0 |
| 580 #define RTC_TIME_WEEK_DAY_MSB 26 |
| 581 #define RTC_TIME_WEEK_DAY_LSB 24 |
| 582 #define RTC_TIME_WEEK_DAY_MASK 0x07000000 |
| 583 #define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK)
>> RTC_TIME_WEEK_DAY_LSB) |
| 584 #define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB)
& RTC_TIME_WEEK_DAY_MASK) |
| 585 #define RTC_TIME_HOUR_MSB 21 |
| 586 #define RTC_TIME_HOUR_LSB 16 |
| 587 #define RTC_TIME_HOUR_MASK 0x003f0000 |
| 588 #define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >>
RTC_TIME_HOUR_LSB) |
| 589 #define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & R
TC_TIME_HOUR_MASK) |
| 590 #define RTC_TIME_MINUTE_MSB 14 |
| 591 #define RTC_TIME_MINUTE_LSB 8 |
| 592 #define RTC_TIME_MINUTE_MASK 0x00007f00 |
| 593 #define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >
> RTC_TIME_MINUTE_LSB) |
| 594 #define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) &
RTC_TIME_MINUTE_MASK) |
| 595 #define RTC_TIME_SECOND_MSB 6 |
| 596 #define RTC_TIME_SECOND_LSB 0 |
| 597 #define RTC_TIME_SECOND_MASK 0x0000007f |
| 598 #define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >
> RTC_TIME_SECOND_LSB) |
| 599 #define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) &
RTC_TIME_SECOND_MASK) |
| 600 |
| 601 #define RTC_DATE_ADDRESS 0x000000a4 |
| 602 #define RTC_DATE_OFFSET 0x000000a4 |
| 603 #define RTC_DATE_YEAR_MSB 23 |
| 604 #define RTC_DATE_YEAR_LSB 16 |
| 605 #define RTC_DATE_YEAR_MASK 0x00ff0000 |
| 606 #define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >>
RTC_DATE_YEAR_LSB) |
| 607 #define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & R
TC_DATE_YEAR_MASK) |
| 608 #define RTC_DATE_MONTH_MSB 12 |
| 609 #define RTC_DATE_MONTH_LSB 8 |
| 610 #define RTC_DATE_MONTH_MASK 0x00001f00 |
| 611 #define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >>
RTC_DATE_MONTH_LSB) |
| 612 #define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) &
RTC_DATE_MONTH_MASK) |
| 613 #define RTC_DATE_MONTH_DAY_MSB 5 |
| 614 #define RTC_DATE_MONTH_DAY_LSB 0 |
| 615 #define RTC_DATE_MONTH_DAY_MASK 0x0000003f |
| 616 #define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK
) >> RTC_DATE_MONTH_DAY_LSB) |
| 617 #define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB
) & RTC_DATE_MONTH_DAY_MASK) |
| 618 |
| 619 #define RTC_SET_TIME_ADDRESS 0x000000a8 |
| 620 #define RTC_SET_TIME_OFFSET 0x000000a8 |
| 621 #define RTC_SET_TIME_WEEK_DAY_MSB 26 |
| 622 #define RTC_SET_TIME_WEEK_DAY_LSB 24 |
| 623 #define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 |
| 624 #define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_M
ASK) >> RTC_SET_TIME_WEEK_DAY_LSB) |
| 625 #define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_
LSB) & RTC_SET_TIME_WEEK_DAY_MASK) |
| 626 #define RTC_SET_TIME_HOUR_MSB 21 |
| 627 #define RTC_SET_TIME_HOUR_LSB 16 |
| 628 #define RTC_SET_TIME_HOUR_MASK 0x003f0000 |
| 629 #define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK)
>> RTC_SET_TIME_HOUR_LSB) |
| 630 #define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB)
& RTC_SET_TIME_HOUR_MASK) |
| 631 #define RTC_SET_TIME_MINUTE_MSB 14 |
| 632 #define RTC_SET_TIME_MINUTE_LSB 8 |
| 633 #define RTC_SET_TIME_MINUTE_MASK 0x00007f00 |
| 634 #define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MAS
K) >> RTC_SET_TIME_MINUTE_LSB) |
| 635 #define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LS
B) & RTC_SET_TIME_MINUTE_MASK) |
| 636 #define RTC_SET_TIME_SECOND_MSB 6 |
| 637 #define RTC_SET_TIME_SECOND_LSB 0 |
| 638 #define RTC_SET_TIME_SECOND_MASK 0x0000007f |
| 639 #define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MAS
K) >> RTC_SET_TIME_SECOND_LSB) |
| 640 #define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LS
B) & RTC_SET_TIME_SECOND_MASK) |
| 641 |
| 642 #define RTC_SET_DATE_ADDRESS 0x000000ac |
| 643 #define RTC_SET_DATE_OFFSET 0x000000ac |
| 644 #define RTC_SET_DATE_YEAR_MSB 23 |
| 645 #define RTC_SET_DATE_YEAR_LSB 16 |
| 646 #define RTC_SET_DATE_YEAR_MASK 0x00ff0000 |
| 647 #define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK)
>> RTC_SET_DATE_YEAR_LSB) |
| 648 #define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB)
& RTC_SET_DATE_YEAR_MASK) |
| 649 #define RTC_SET_DATE_MONTH_MSB 12 |
| 650 #define RTC_SET_DATE_MONTH_LSB 8 |
| 651 #define RTC_SET_DATE_MONTH_MASK 0x00001f00 |
| 652 #define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK
) >> RTC_SET_DATE_MONTH_LSB) |
| 653 #define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB
) & RTC_SET_DATE_MONTH_MASK) |
| 654 #define RTC_SET_DATE_MONTH_DAY_MSB 5 |
| 655 #define RTC_SET_DATE_MONTH_DAY_LSB 0 |
| 656 #define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f |
| 657 #define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_
MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) |
| 658 #define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY
_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) |
| 659 |
| 660 #define RTC_SET_ALARM_ADDRESS 0x000000b0 |
| 661 #define RTC_SET_ALARM_OFFSET 0x000000b0 |
| 662 #define RTC_SET_ALARM_HOUR_MSB 21 |
| 663 #define RTC_SET_ALARM_HOUR_LSB 16 |
| 664 #define RTC_SET_ALARM_HOUR_MASK 0x003f0000 |
| 665 #define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK
) >> RTC_SET_ALARM_HOUR_LSB) |
| 666 #define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB
) & RTC_SET_ALARM_HOUR_MASK) |
| 667 #define RTC_SET_ALARM_MINUTE_MSB 14 |
| 668 #define RTC_SET_ALARM_MINUTE_LSB 8 |
| 669 #define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 |
| 670 #define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MA
SK) >> RTC_SET_ALARM_MINUTE_LSB) |
| 671 #define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_L
SB) & RTC_SET_ALARM_MINUTE_MASK) |
| 672 #define RTC_SET_ALARM_SECOND_MSB 6 |
| 673 #define RTC_SET_ALARM_SECOND_LSB 0 |
| 674 #define RTC_SET_ALARM_SECOND_MASK 0x0000007f |
| 675 #define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MA
SK) >> RTC_SET_ALARM_SECOND_LSB) |
| 676 #define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_L
SB) & RTC_SET_ALARM_SECOND_MASK) |
| 677 |
| 678 #define RTC_CONFIG_ADDRESS 0x000000b4 |
| 679 #define RTC_CONFIG_OFFSET 0x000000b4 |
| 680 #define RTC_CONFIG_BCD_MSB 2 |
| 681 #define RTC_CONFIG_BCD_LSB 2 |
| 682 #define RTC_CONFIG_BCD_MASK 0x00000004 |
| 683 #define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >>
RTC_CONFIG_BCD_LSB) |
| 684 #define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) &
RTC_CONFIG_BCD_MASK) |
| 685 #define RTC_CONFIG_TWELVE_HOUR_MSB 1 |
| 686 #define RTC_CONFIG_TWELVE_HOUR_LSB 1 |
| 687 #define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 |
| 688 #define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_
MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) |
| 689 #define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR
_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) |
| 690 #define RTC_CONFIG_DSE_MSB 0 |
| 691 #define RTC_CONFIG_DSE_LSB 0 |
| 692 #define RTC_CONFIG_DSE_MASK 0x00000001 |
| 693 #define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >>
RTC_CONFIG_DSE_LSB) |
| 694 #define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) &
RTC_CONFIG_DSE_MASK) |
| 695 |
| 696 #define RTC_ALARM_STATUS_ADDRESS 0x000000b8 |
| 697 #define RTC_ALARM_STATUS_OFFSET 0x000000b8 |
| 698 #define RTC_ALARM_STATUS_ENABLE_MSB 1 |
| 699 #define RTC_ALARM_STATUS_ENABLE_LSB 1 |
| 700 #define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 |
| 701 #define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE
_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) |
| 702 #define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABL
E_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) |
| 703 #define RTC_ALARM_STATUS_INTERRUPT_MSB 0 |
| 704 #define RTC_ALARM_STATUS_INTERRUPT_LSB 0 |
| 705 #define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 |
| 706 #define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERR
UPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) |
| 707 #define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTER
RUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) |
| 708 |
| 709 #define UART_WAKEUP_ADDRESS 0x000000bc |
| 710 #define UART_WAKEUP_OFFSET 0x000000bc |
| 711 #define UART_WAKEUP_ENABLE_MSB 0 |
| 712 #define UART_WAKEUP_ENABLE_LSB 0 |
| 713 #define UART_WAKEUP_ENABLE_MASK 0x00000001 |
| 714 #define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK
) >> UART_WAKEUP_ENABLE_LSB) |
| 715 #define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB
) & UART_WAKEUP_ENABLE_MASK) |
| 716 |
| 717 #define RESET_CAUSE_ADDRESS 0x000000c0 |
| 718 #define RESET_CAUSE_OFFSET 0x000000c0 |
| 719 #define RESET_CAUSE_LAST_MSB 2 |
| 720 #define RESET_CAUSE_LAST_LSB 0 |
| 721 #define RESET_CAUSE_LAST_MASK 0x00000007 |
| 722 #define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK)
>> RESET_CAUSE_LAST_LSB) |
| 723 #define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB)
& RESET_CAUSE_LAST_MASK) |
| 724 |
| 725 #define SYSTEM_SLEEP_ADDRESS 0x000000c4 |
| 726 #define SYSTEM_SLEEP_OFFSET 0x000000c4 |
| 727 #define SYSTEM_SLEEP_HOST_IF_MSB 4 |
| 728 #define SYSTEM_SLEEP_HOST_IF_LSB 4 |
| 729 #define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 |
| 730 #define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MA
SK) >> SYSTEM_SLEEP_HOST_IF_LSB) |
| 731 #define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_L
SB) & SYSTEM_SLEEP_HOST_IF_MASK) |
| 732 #define SYSTEM_SLEEP_MBOX_MSB 3 |
| 733 #define SYSTEM_SLEEP_MBOX_LSB 3 |
| 734 #define SYSTEM_SLEEP_MBOX_MASK 0x00000008 |
| 735 #define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK)
>> SYSTEM_SLEEP_MBOX_LSB) |
| 736 #define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB)
& SYSTEM_SLEEP_MBOX_MASK) |
| 737 #define SYSTEM_SLEEP_MAC_IF_MSB 2 |
| 738 #define SYSTEM_SLEEP_MAC_IF_LSB 2 |
| 739 #define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 |
| 740 #define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MAS
K) >> SYSTEM_SLEEP_MAC_IF_LSB) |
| 741 #define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LS
B) & SYSTEM_SLEEP_MAC_IF_MASK) |
| 742 #define SYSTEM_SLEEP_LIGHT_MSB 1 |
| 743 #define SYSTEM_SLEEP_LIGHT_LSB 1 |
| 744 #define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 |
| 745 #define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK
) >> SYSTEM_SLEEP_LIGHT_LSB) |
| 746 #define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB
) & SYSTEM_SLEEP_LIGHT_MASK) |
| 747 #define SYSTEM_SLEEP_DISABLE_MSB 0 |
| 748 #define SYSTEM_SLEEP_DISABLE_LSB 0 |
| 749 #define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| 750 #define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MA
SK) >> SYSTEM_SLEEP_DISABLE_LSB) |
| 751 #define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_L
SB) & SYSTEM_SLEEP_DISABLE_MASK) |
| 752 |
| 753 #define SDIO_WRAPPER_ADDRESS 0x000000c8 |
| 754 #define SDIO_WRAPPER_OFFSET 0x000000c8 |
| 755 #define SDIO_WRAPPER_SLEEP_MSB 3 |
| 756 #define SDIO_WRAPPER_SLEEP_LSB 3 |
| 757 #define SDIO_WRAPPER_SLEEP_MASK 0x00000008 |
| 758 #define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK
) >> SDIO_WRAPPER_SLEEP_LSB) |
| 759 #define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB
) & SDIO_WRAPPER_SLEEP_MASK) |
| 760 #define SDIO_WRAPPER_WAKEUP_MSB 2 |
| 761 #define SDIO_WRAPPER_WAKEUP_LSB 2 |
| 762 #define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 |
| 763 #define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MAS
K) >> SDIO_WRAPPER_WAKEUP_LSB) |
| 764 #define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LS
B) & SDIO_WRAPPER_WAKEUP_MASK) |
| 765 #define SDIO_WRAPPER_SOC_ON_MSB 1 |
| 766 #define SDIO_WRAPPER_SOC_ON_LSB 1 |
| 767 #define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 |
| 768 #define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MAS
K) >> SDIO_WRAPPER_SOC_ON_LSB) |
| 769 #define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LS
B) & SDIO_WRAPPER_SOC_ON_MASK) |
| 770 #define SDIO_WRAPPER_ON_MSB 0 |
| 771 #define SDIO_WRAPPER_ON_LSB 0 |
| 772 #define SDIO_WRAPPER_ON_MASK 0x00000001 |
| 773 #define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >
> SDIO_WRAPPER_ON_LSB) |
| 774 #define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) &
SDIO_WRAPPER_ON_MASK) |
| 775 |
| 776 #define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc |
| 777 #define MAC_SLEEP_CONTROL_OFFSET 0x000000cc |
| 778 #define MAC_SLEEP_CONTROL_ENABLE_MSB 1 |
| 779 #define MAC_SLEEP_CONTROL_ENABLE_LSB 0 |
| 780 #define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 |
| 781 #define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABL
E_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) |
| 782 #define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENAB
LE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) |
| 783 |
| 784 #define KEEP_AWAKE_ADDRESS 0x000000d0 |
| 785 #define KEEP_AWAKE_OFFSET 0x000000d0 |
| 786 #define KEEP_AWAKE_COUNT_MSB 7 |
| 787 #define KEEP_AWAKE_COUNT_LSB 0 |
| 788 #define KEEP_AWAKE_COUNT_MASK 0x000000ff |
| 789 #define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK)
>> KEEP_AWAKE_COUNT_LSB) |
| 790 #define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB)
& KEEP_AWAKE_COUNT_MASK) |
| 791 |
| 792 #define LPO_CAL_TIME_ADDRESS 0x000000d4 |
| 793 #define LPO_CAL_TIME_OFFSET 0x000000d4 |
| 794 #define LPO_CAL_TIME_LENGTH_MSB 13 |
| 795 #define LPO_CAL_TIME_LENGTH_LSB 0 |
| 796 #define LPO_CAL_TIME_LENGTH_MASK 0x00003fff |
| 797 #define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MAS
K) >> LPO_CAL_TIME_LENGTH_LSB) |
| 798 #define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LS
B) & LPO_CAL_TIME_LENGTH_MASK) |
| 799 |
| 800 #define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 |
| 801 #define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 |
| 802 #define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 |
| 803 #define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 |
| 804 #define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff |
| 805 #define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_V
ALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) |
| 806 #define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_
VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) |
| 807 |
| 808 #define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc |
| 809 #define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc |
| 810 #define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 |
| 811 #define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 |
| 812 #define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff |
| 813 #define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACT
ION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) |
| 814 #define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRAC
TION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) |
| 815 |
| 816 #define LPO_CAL_ADDRESS 0x000000e0 |
| 817 #define LPO_CAL_OFFSET 0x000000e0 |
| 818 #define LPO_CAL_ENABLE_MSB 20 |
| 819 #define LPO_CAL_ENABLE_LSB 20 |
| 820 #define LPO_CAL_ENABLE_MASK 0x00100000 |
| 821 #define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >>
LPO_CAL_ENABLE_LSB) |
| 822 #define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) &
LPO_CAL_ENABLE_MASK) |
| 823 #define LPO_CAL_COUNT_MSB 19 |
| 824 #define LPO_CAL_COUNT_LSB 0 |
| 825 #define LPO_CAL_COUNT_MASK 0x000fffff |
| 826 #define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >>
LPO_CAL_COUNT_LSB) |
| 827 #define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & L
PO_CAL_COUNT_MASK) |
| 828 |
| 829 #define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 |
| 830 #define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 |
| 831 #define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 |
| 832 #define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 |
| 833 #define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 |
| 834 #define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_EN
ABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) |
| 835 #define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_E
NABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) |
| 836 #define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 |
| 837 #define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 |
| 838 #define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f |
| 839 #define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RT
C_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) |
| 840 #define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_R
TC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) |
| 841 |
| 842 #define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 |
| 843 #define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 |
| 844 #define LPO_CAL_TEST_STATUS_READY_MSB 16 |
| 845 #define LPO_CAL_TEST_STATUS_READY_LSB 16 |
| 846 #define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 |
| 847 #define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_REA
DY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) |
| 848 #define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_RE
ADY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) |
| 849 #define LPO_CAL_TEST_STATUS_COUNT_MSB 15 |
| 850 #define LPO_CAL_TEST_STATUS_COUNT_LSB 0 |
| 851 #define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff |
| 852 #define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COU
NT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) |
| 853 #define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_CO
UNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) |
| 854 |
| 855 #define CHIP_ID_ADDRESS 0x000000ec |
| 856 #define CHIP_ID_OFFSET 0x000000ec |
| 857 #define CHIP_ID_DEVICE_ID_MSB 31 |
| 858 #define CHIP_ID_DEVICE_ID_LSB 16 |
| 859 #define CHIP_ID_DEVICE_ID_MASK 0xffff0000 |
| 860 #define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK)
>> CHIP_ID_DEVICE_ID_LSB) |
| 861 #define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB)
& CHIP_ID_DEVICE_ID_MASK) |
| 862 #define CHIP_ID_CONFIG_ID_MSB 15 |
| 863 #define CHIP_ID_CONFIG_ID_LSB 4 |
| 864 #define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 |
| 865 #define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK)
>> CHIP_ID_CONFIG_ID_LSB) |
| 866 #define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB)
& CHIP_ID_CONFIG_ID_MASK) |
| 867 #define CHIP_ID_VERSION_ID_MSB 3 |
| 868 #define CHIP_ID_VERSION_ID_LSB 0 |
| 869 #define CHIP_ID_VERSION_ID_MASK 0x0000000f |
| 870 #define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK
) >> CHIP_ID_VERSION_ID_LSB) |
| 871 #define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB
) & CHIP_ID_VERSION_ID_MASK) |
| 872 |
| 873 #define DERIVED_RTC_CLK_ADDRESS 0x000000f0 |
| 874 #define DERIVED_RTC_CLK_OFFSET 0x000000f0 |
| 875 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 |
| 876 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 |
| 877 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 |
| 878 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERN
AL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) |
| 879 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTER
NAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) |
| 880 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 |
| 881 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 |
| 882 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 |
| 883 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNA
L_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) |
| 884 #define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERN
AL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) |
| 885 #define DERIVED_RTC_CLK_FORCE_MSB 17 |
| 886 #define DERIVED_RTC_CLK_FORCE_LSB 16 |
| 887 #define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 |
| 888 #define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_M
ASK) >> DERIVED_RTC_CLK_FORCE_LSB) |
| 889 #define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_
LSB) & DERIVED_RTC_CLK_FORCE_MASK) |
| 890 #define DERIVED_RTC_CLK_PERIOD_MSB 15 |
| 891 #define DERIVED_RTC_CLK_PERIOD_LSB 1 |
| 892 #define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe |
| 893 #define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_
MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) |
| 894 #define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD
_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) |
| 895 |
| 896 #define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 |
| 897 #define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 |
| 898 #define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 |
| 899 #define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 |
| 900 #define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 |
| 901 #define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_T
SF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) |
| 902 #define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_
TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) |
| 903 #define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 |
| 904 #define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 |
| 905 #define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff |
| 906 #define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HA
LF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) |
| 907 #define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_H
ALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) |
| 908 |
| 909 #define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 |
| 910 #define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 |
| 911 #define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 |
| 912 #define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 |
| 913 #define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff |
| 914 #define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_
TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) |
| 915 #define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL
_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) |
| 916 |
| 917 #define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc |
| 918 #define MAC_PCU_SLP32_INC_OFFSET 0x000000fc |
| 919 #define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 |
| 920 #define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 |
| 921 #define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff |
| 922 #define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_I
NC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) |
| 923 #define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_
INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) |
| 924 |
| 925 #define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 |
| 926 #define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 |
| 927 #define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 |
| 928 #define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 |
| 929 #define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff |
| 930 #define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_
CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) |
| 931 #define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP
_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) |
| 932 |
| 933 #define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 |
| 934 #define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 |
| 935 #define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 |
| 936 #define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 |
| 937 #define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff |
| 938 #define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_
CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) |
| 939 #define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE
_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) |
| 940 |
| 941 #define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 |
| 942 #define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 |
| 943 #define MAC_PCU_SLP_MIB3_PENDING_MSB 1 |
| 944 #define MAC_PCU_SLP_MIB3_PENDING_LSB 1 |
| 945 #define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 |
| 946 #define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDIN
G_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) |
| 947 #define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDI
NG_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) |
| 948 #define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 |
| 949 #define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 |
| 950 #define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 |
| 951 #define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CN
T_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) |
| 952 #define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_C
NT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) |
| 953 |
| 954 #define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c |
| 955 #define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c |
| 956 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 |
| 957 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 |
| 958 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 |
| 959 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACO
N_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) |
| 960 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEAC
ON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) |
| 961 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 |
| 962 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 |
| 963 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff |
| 964 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMIS
S_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) |
| 965 #define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMI
SS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) |
| 966 |
| 967 #define POWER_REG_ADDRESS 0x00000110 |
| 968 #define POWER_REG_OFFSET 0x00000110 |
| 969 #define POWER_REG_VLVL_MSB 11 |
| 970 #define POWER_REG_VLVL_LSB 8 |
| 971 #define POWER_REG_VLVL_MASK 0x00000f00 |
| 972 #define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >>
POWER_REG_VLVL_LSB) |
| 973 #define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) &
POWER_REG_VLVL_MASK) |
| 974 #define POWER_REG_CPU_INT_ENABLE_MSB 7 |
| 975 #define POWER_REG_CPU_INT_ENABLE_LSB 7 |
| 976 #define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 |
| 977 #define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABL
E_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) |
| 978 #define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENAB
LE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) |
| 979 #define POWER_REG_WLAN_ISO_DIS_MSB 6 |
| 980 #define POWER_REG_WLAN_ISO_DIS_LSB 6 |
| 981 #define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 |
| 982 #define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_
MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) |
| 983 #define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS
_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) |
| 984 #define POWER_REG_WLAN_ISO_CNTL_MSB 5 |
| 985 #define POWER_REG_WLAN_ISO_CNTL_LSB 5 |
| 986 #define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 |
| 987 #define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL
_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) |
| 988 #define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNT
L_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) |
| 989 #define POWER_REG_RADIO_PWD_EN_MSB 4 |
| 990 #define POWER_REG_RADIO_PWD_EN_LSB 4 |
| 991 #define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 |
| 992 #define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_
MASK) >> POWER_REG_RADIO_PWD_EN_LSB) |
| 993 #define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN
_LSB) & POWER_REG_RADIO_PWD_EN_MASK) |
| 994 #define POWER_REG_SOC_SCALE_EN_MSB 3 |
| 995 #define POWER_REG_SOC_SCALE_EN_LSB 3 |
| 996 #define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 |
| 997 #define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_
MASK) >> POWER_REG_SOC_SCALE_EN_LSB) |
| 998 #define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN
_LSB) & POWER_REG_SOC_SCALE_EN_MASK) |
| 999 #define POWER_REG_WLAN_SCALE_EN_MSB 2 |
| 1000 #define POWER_REG_WLAN_SCALE_EN_LSB 2 |
| 1001 #define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 |
| 1002 #define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN
_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) |
| 1003 #define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_E
N_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) |
| 1004 #define POWER_REG_WLAN_PWD_EN_MSB 1 |
| 1005 #define POWER_REG_WLAN_PWD_EN_LSB 1 |
| 1006 #define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 |
| 1007 #define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_M
ASK) >> POWER_REG_WLAN_PWD_EN_LSB) |
| 1008 #define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_
LSB) & POWER_REG_WLAN_PWD_EN_MASK) |
| 1009 #define POWER_REG_POWER_EN_MSB 0 |
| 1010 #define POWER_REG_POWER_EN_LSB 0 |
| 1011 #define POWER_REG_POWER_EN_MASK 0x00000001 |
| 1012 #define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK
) >> POWER_REG_POWER_EN_LSB) |
| 1013 #define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB
) & POWER_REG_POWER_EN_MASK) |
| 1014 |
| 1015 #define CORE_CLK_CTRL_ADDRESS 0x00000114 |
| 1016 #define CORE_CLK_CTRL_OFFSET 0x00000114 |
| 1017 #define CORE_CLK_CTRL_DIV_MSB 2 |
| 1018 #define CORE_CLK_CTRL_DIV_LSB 0 |
| 1019 #define CORE_CLK_CTRL_DIV_MASK 0x00000007 |
| 1020 #define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK)
>> CORE_CLK_CTRL_DIV_LSB) |
| 1021 #define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB)
& CORE_CLK_CTRL_DIV_MASK) |
| 1022 |
| 1023 #define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 |
| 1024 #define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 |
| 1025 #define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 |
| 1026 #define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 |
| 1027 #define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff |
| 1028 #define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECT
OR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) |
| 1029 #define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VEC
TOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) |
| 1030 |
| 1031 #define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 |
| 1032 #define SDIO_SETUP_CONFIG_OFFSET 0x00000140 |
| 1033 #define SDIO_SETUP_CONFIG_ENABLE_MSB 1 |
| 1034 #define SDIO_SETUP_CONFIG_ENABLE_LSB 1 |
| 1035 #define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 |
| 1036 #define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABL
E_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) |
| 1037 #define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENAB
LE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) |
| 1038 #define SDIO_SETUP_CONFIG_CLEAR_MSB 0 |
| 1039 #define SDIO_SETUP_CONFIG_CLEAR_LSB 0 |
| 1040 #define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 |
| 1041 #define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR
_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) |
| 1042 #define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEA
R_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) |
| 1043 |
| 1044 #define CPU_SETUP_CONFIG_ADDRESS 0x00000144 |
| 1045 #define CPU_SETUP_CONFIG_OFFSET 0x00000144 |
| 1046 #define CPU_SETUP_CONFIG_ENABLE_MSB 1 |
| 1047 #define CPU_SETUP_CONFIG_ENABLE_LSB 1 |
| 1048 #define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 |
| 1049 #define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE
_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) |
| 1050 #define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABL
E_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) |
| 1051 #define CPU_SETUP_CONFIG_CLEAR_MSB 0 |
| 1052 #define CPU_SETUP_CONFIG_CLEAR_LSB 0 |
| 1053 #define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 |
| 1054 #define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_
MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) |
| 1055 #define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR
_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) |
| 1056 |
| 1057 #define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 |
| 1058 #define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 |
| 1059 #define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 |
| 1060 #define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 |
| 1061 #define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff |
| 1062 #define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTO
R_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) |
| 1063 #define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECT
OR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) |
| 1064 |
| 1065 #define BB_SETUP_CONFIG_ADDRESS 0x00000180 |
| 1066 #define BB_SETUP_CONFIG_OFFSET 0x00000180 |
| 1067 #define BB_SETUP_CONFIG_ENABLE_MSB 1 |
| 1068 #define BB_SETUP_CONFIG_ENABLE_LSB 1 |
| 1069 #define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 |
| 1070 #define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_
MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) |
| 1071 #define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE
_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) |
| 1072 #define BB_SETUP_CONFIG_CLEAR_MSB 0 |
| 1073 #define BB_SETUP_CONFIG_CLEAR_LSB 0 |
| 1074 #define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 |
| 1075 #define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_M
ASK) >> BB_SETUP_CONFIG_CLEAR_LSB) |
| 1076 #define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_
LSB) & BB_SETUP_CONFIG_CLEAR_MASK) |
| 1077 |
| 1078 #define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 |
| 1079 #define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 |
| 1080 #define BB_SETUP_CIRCUIT_VECTOR_MSB 7 |
| 1081 #define BB_SETUP_CIRCUIT_VECTOR_LSB 0 |
| 1082 #define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff |
| 1083 #define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR
_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) |
| 1084 #define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTO
R_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) |
| 1085 |
| 1086 #define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 |
| 1087 #define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 |
| 1088 #define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 |
| 1089 #define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 |
| 1090 #define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 |
| 1091 #define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENA
BLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) |
| 1092 #define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_EN
ABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) |
| 1093 |
| 1094 |
| 1095 #ifndef __ASSEMBLER__ |
| 1096 |
| 1097 typedef struct rtc_reg_reg_s { |
| 1098 volatile unsigned int reset_control; |
| 1099 volatile unsigned int xtal_control; |
| 1100 volatile unsigned int tcxo_detect; |
| 1101 volatile unsigned int xtal_test; |
| 1102 volatile unsigned int quadrature; |
| 1103 volatile unsigned int pll_control; |
| 1104 volatile unsigned int pll_settle; |
| 1105 volatile unsigned int xtal_settle; |
| 1106 volatile unsigned int cpu_clock; |
| 1107 volatile unsigned int clock_out; |
| 1108 volatile unsigned int clock_control; |
| 1109 volatile unsigned int bias_override; |
| 1110 volatile unsigned int wdt_control; |
| 1111 volatile unsigned int wdt_status; |
| 1112 volatile unsigned int wdt; |
| 1113 volatile unsigned int wdt_count; |
| 1114 volatile unsigned int wdt_reset; |
| 1115 volatile unsigned int int_status; |
| 1116 volatile unsigned int lf_timer0; |
| 1117 volatile unsigned int lf_timer_count0; |
| 1118 volatile unsigned int lf_timer_control0; |
| 1119 volatile unsigned int lf_timer_status0; |
| 1120 volatile unsigned int lf_timer1; |
| 1121 volatile unsigned int lf_timer_count1; |
| 1122 volatile unsigned int lf_timer_control1; |
| 1123 volatile unsigned int lf_timer_status1; |
| 1124 volatile unsigned int lf_timer2; |
| 1125 volatile unsigned int lf_timer_count2; |
| 1126 volatile unsigned int lf_timer_control2; |
| 1127 volatile unsigned int lf_timer_status2; |
| 1128 volatile unsigned int lf_timer3; |
| 1129 volatile unsigned int lf_timer_count3; |
| 1130 volatile unsigned int lf_timer_control3; |
| 1131 volatile unsigned int lf_timer_status3; |
| 1132 volatile unsigned int hf_timer; |
| 1133 volatile unsigned int hf_timer_count; |
| 1134 volatile unsigned int hf_lf_count; |
| 1135 volatile unsigned int hf_timer_control; |
| 1136 volatile unsigned int hf_timer_status; |
| 1137 volatile unsigned int rtc_control; |
| 1138 volatile unsigned int rtc_time; |
| 1139 volatile unsigned int rtc_date; |
| 1140 volatile unsigned int rtc_set_time; |
| 1141 volatile unsigned int rtc_set_date; |
| 1142 volatile unsigned int rtc_set_alarm; |
| 1143 volatile unsigned int rtc_config; |
| 1144 volatile unsigned int rtc_alarm_status; |
| 1145 volatile unsigned int uart_wakeup; |
| 1146 volatile unsigned int reset_cause; |
| 1147 volatile unsigned int system_sleep; |
| 1148 volatile unsigned int sdio_wrapper; |
| 1149 volatile unsigned int mac_sleep_control; |
| 1150 volatile unsigned int keep_awake; |
| 1151 volatile unsigned int lpo_cal_time; |
| 1152 volatile unsigned int lpo_init_dividend_int; |
| 1153 volatile unsigned int lpo_init_dividend_fraction; |
| 1154 volatile unsigned int lpo_cal; |
| 1155 volatile unsigned int lpo_cal_test_control; |
| 1156 volatile unsigned int lpo_cal_test_status; |
| 1157 volatile unsigned int chip_id; |
| 1158 volatile unsigned int derived_rtc_clk; |
| 1159 volatile unsigned int mac_pcu_slp32_mode; |
| 1160 volatile unsigned int mac_pcu_slp32_wake; |
| 1161 volatile unsigned int mac_pcu_slp32_inc; |
| 1162 volatile unsigned int mac_pcu_slp_mib1; |
| 1163 volatile unsigned int mac_pcu_slp_mib2; |
| 1164 volatile unsigned int mac_pcu_slp_mib3; |
| 1165 volatile unsigned int mac_pcu_slp_beacon; |
| 1166 volatile unsigned int power_reg; |
| 1167 volatile unsigned int core_clk_ctrl; |
| 1168 unsigned char pad0[8]; /* pad to 0x120 */ |
| 1169 volatile unsigned int sdio_setup_circuit[8]; |
| 1170 volatile unsigned int sdio_setup_config; |
| 1171 volatile unsigned int cpu_setup_config; |
| 1172 unsigned char pad1[24]; /* pad to 0x160 */ |
| 1173 volatile unsigned int cpu_setup_circuit[8]; |
| 1174 volatile unsigned int bb_setup_config; |
| 1175 unsigned char pad2[28]; /* pad to 0x1a0 */ |
| 1176 volatile unsigned int bb_setup_circuit[8]; |
| 1177 volatile unsigned int gpio_wakeup_control; |
| 1178 } rtc_reg_reg_t; |
| 1179 |
| 1180 #endif /* __ASSEMBLER__ */ |
| 1181 |
| 1182 #endif /* _RTC_REG_H_ */ |
OLD | NEW |