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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _ANALOG_REG_REG_H_ |
| 21 #define _ANALOG_REG_REG_H_ |
| 22 |
| 23 #define SYNTH_SYNTH1_ADDRESS 0x00000000 |
| 24 #define SYNTH_SYNTH1_OFFSET 0x00000000 |
| 25 #define SYNTH_SYNTH1_PWD_BIAS_MSB 31 |
| 26 #define SYNTH_SYNTH1_PWD_BIAS_LSB 31 |
| 27 #define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 |
| 28 #define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_M
ASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) |
| 29 #define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_
LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) |
| 30 #define SYNTH_SYNTH1_PWD_CP_MSB 30 |
| 31 #define SYNTH_SYNTH1_PWD_CP_LSB 30 |
| 32 #define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 |
| 33 #define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MAS
K) >> SYNTH_SYNTH1_PWD_CP_LSB) |
| 34 #define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LS
B) & SYNTH_SYNTH1_PWD_CP_MASK) |
| 35 #define SYNTH_SYNTH1_PWD_VCMON_MSB 29 |
| 36 #define SYNTH_SYNTH1_PWD_VCMON_LSB 29 |
| 37 #define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 |
| 38 #define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_
MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) |
| 39 #define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON
_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) |
| 40 #define SYNTH_SYNTH1_PWD_VCO_MSB 28 |
| 41 #define SYNTH_SYNTH1_PWD_VCO_LSB 28 |
| 42 #define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 |
| 43 #define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MA
SK) >> SYNTH_SYNTH1_PWD_VCO_LSB) |
| 44 #define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_L
SB) & SYNTH_SYNTH1_PWD_VCO_MASK) |
| 45 #define SYNTH_SYNTH1_PWD_PRESC_MSB 27 |
| 46 #define SYNTH_SYNTH1_PWD_PRESC_LSB 27 |
| 47 #define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 |
| 48 #define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_
MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) |
| 49 #define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC
_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) |
| 50 #define SYNTH_SYNTH1_PWD_LODIV_MSB 26 |
| 51 #define SYNTH_SYNTH1_PWD_LODIV_LSB 26 |
| 52 #define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 |
| 53 #define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_
MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) |
| 54 #define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV
_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) |
| 55 #define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 |
| 56 #define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 |
| 57 #define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 |
| 58 #define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_
MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) |
| 59 #define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX
_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) |
| 60 #define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 |
| 61 #define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 |
| 62 #define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 |
| 63 #define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_O
N_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) |
| 64 #define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_
ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) |
| 65 #define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 |
| 66 #define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 |
| 67 #define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 |
| 68 #define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5
G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) |
| 69 #define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF
5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) |
| 70 #define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 |
| 71 #define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 |
| 72 #define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 |
| 73 #define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPA
SS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) |
| 74 #define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYP
ASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) |
| 75 #define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 |
| 76 #define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 |
| 77 #define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 |
| 78 #define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVE
L_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) |
| 79 #define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEV
EL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) |
| 80 #define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 |
| 81 #define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 |
| 82 #define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 |
| 83 #define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS
_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) |
| 84 #define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIA
S_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) |
| 85 #define SYNTH_SYNTH1_SLIDINGIF_MSB 17 |
| 86 #define SYNTH_SYNTH1_SLIDINGIF_LSB 17 |
| 87 #define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 |
| 88 #define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_
MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) |
| 89 #define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF
_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) |
| 90 #define SYNTH_SYNTH1_SPARE_PWD_MSB 16 |
| 91 #define SYNTH_SYNTH1_SPARE_PWD_LSB 16 |
| 92 #define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 |
| 93 #define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_
MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) |
| 94 #define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD
_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) |
| 95 #define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 |
| 96 #define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 |
| 97 #define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 |
| 98 #define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCO
REG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) |
| 99 #define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVC
OREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) |
| 100 #define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 |
| 101 #define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 |
| 102 #define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 |
| 103 #define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCORE
G_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) |
| 104 #define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOR
EG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) |
| 105 #define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 |
| 106 #define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 |
| 107 #define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 |
| 108 #define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBU
F_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) |
| 109 #define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOB
UF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) |
| 110 #define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 |
| 111 #define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 |
| 112 #define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 |
| 113 #define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONA
BUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) |
| 114 #define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMON
ABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) |
| 115 #define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 |
| 116 #define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 |
| 117 #define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 |
| 118 #define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBU
F_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) |
| 119 #define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOB
UF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) |
| 120 #define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 |
| 121 #define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 |
| 122 #define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 |
| 123 #define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV
_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) |
| 124 #define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODI
V_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) |
| 125 #define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 |
| 126 #define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 |
| 127 #define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 |
| 128 #define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX
_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) |
| 129 #define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMI
X_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) |
| 130 #define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 |
| 131 #define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 |
| 132 #define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 |
| 133 #define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF
5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) |
| 134 #define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBU
F5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) |
| 135 #define SYNTH_SYNTH1_MONITOR_FB_MSB 5 |
| 136 #define SYNTH_SYNTH1_MONITOR_FB_LSB 5 |
| 137 #define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 |
| 138 #define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB
_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) |
| 139 #define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_F
B_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) |
| 140 #define SYNTH_SYNTH1_MONITOR_REF_MSB 4 |
| 141 #define SYNTH_SYNTH1_MONITOR_REF_LSB 4 |
| 142 #define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 |
| 143 #define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_RE
F_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) |
| 144 #define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_R
EF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) |
| 145 #define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 |
| 146 #define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 |
| 147 #define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 |
| 148 #define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB
_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) |
| 149 #define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_F
B_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) |
| 150 #define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 |
| 151 #define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 |
| 152 #define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 |
| 153 #define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC
2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) |
| 154 #define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_V
C2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) |
| 155 #define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 |
| 156 #define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 |
| 157 #define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 |
| 158 #define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC
2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) |
| 159 #define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_V
C2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) |
| 160 #define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 |
| 161 #define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 |
| 162 #define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 |
| 163 #define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_S
YNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) |
| 164 #define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_
SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) |
| 165 |
| 166 #define SYNTH_SYNTH2_ADDRESS 0x00000004 |
| 167 #define SYNTH_SYNTH2_OFFSET 0x00000004 |
| 168 #define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 |
| 169 #define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 |
| 170 #define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 |
| 171 #define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF
_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) |
| 172 #define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_RE
F_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) |
| 173 #define SYNTH_SYNTH2_VC_HI_REF_MSB 28 |
| 174 #define SYNTH_SYNTH2_VC_HI_REF_LSB 26 |
| 175 #define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 |
| 176 #define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_
MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) |
| 177 #define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF
_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) |
| 178 #define SYNTH_SYNTH2_VC_MID_REF_MSB 25 |
| 179 #define SYNTH_SYNTH2_VC_MID_REF_LSB 23 |
| 180 #define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 |
| 181 #define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF
_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) |
| 182 #define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_RE
F_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) |
| 183 #define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 |
| 184 #define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 |
| 185 #define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 |
| 186 #define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF
_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) |
| 187 #define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_RE
F_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) |
| 188 #define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 |
| 189 #define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 |
| 190 #define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 |
| 191 #define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_O
RDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) |
| 192 #define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_
ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) |
| 193 #define SYNTH_SYNTH2_LOOP_CP_MSB 14 |
| 194 #define SYNTH_SYNTH2_LOOP_CP_LSB 10 |
| 195 #define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 |
| 196 #define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MA
SK) >> SYNTH_SYNTH2_LOOP_CP_LSB) |
| 197 #define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_L
SB) & SYNTH_SYNTH2_LOOP_CP_MASK) |
| 198 #define SYNTH_SYNTH2_LOOP_RS_MSB 9 |
| 199 #define SYNTH_SYNTH2_LOOP_RS_LSB 5 |
| 200 #define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 |
| 201 #define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MA
SK) >> SYNTH_SYNTH2_LOOP_RS_LSB) |
| 202 #define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_L
SB) & SYNTH_SYNTH2_LOOP_RS_MASK) |
| 203 #define SYNTH_SYNTH2_LOOP_CS_MSB 4 |
| 204 #define SYNTH_SYNTH2_LOOP_CS_LSB 3 |
| 205 #define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 |
| 206 #define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MA
SK) >> SYNTH_SYNTH2_LOOP_CS_LSB) |
| 207 #define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_L
SB) & SYNTH_SYNTH2_LOOP_CS_MASK) |
| 208 #define SYNTH_SYNTH2_SPARE_BITS_MSB 2 |
| 209 #define SYNTH_SYNTH2_SPARE_BITS_LSB 0 |
| 210 #define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 |
| 211 #define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS
_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) |
| 212 #define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BIT
S_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) |
| 213 |
| 214 #define SYNTH_SYNTH3_ADDRESS 0x00000008 |
| 215 #define SYNTH_SYNTH3_OFFSET 0x00000008 |
| 216 #define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 |
| 217 #define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 |
| 218 #define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 |
| 219 #define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XT
AL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) |
| 220 #define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_X
TAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) |
| 221 #define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 |
| 222 #define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 |
| 223 #define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 |
| 224 #define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DI
V2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) |
| 225 #define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_D
IV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) |
| 226 #define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 |
| 227 #define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 |
| 228 #define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 |
| 229 #define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORT
R_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) |
| 230 #define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHOR
TR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) |
| 231 #define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 |
| 232 #define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 |
| 233 #define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 |
| 234 #define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP
_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) |
| 235 #define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRU
P_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) |
| 236 #define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 |
| 237 #define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 |
| 238 #define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 |
| 239 #define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_B
IN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) |
| 240 #define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_
BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) |
| 241 #define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 |
| 242 #define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 |
| 243 #define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 |
| 244 #define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_L
IN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) |
| 245 #define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_
LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) |
| 246 #define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 |
| 247 #define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 |
| 248 #define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f |
| 249 #define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CH
ECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) |
| 250 #define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_C
HECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) |
| 251 |
| 252 #define SYNTH_SYNTH4_ADDRESS 0x0000000c |
| 253 #define SYNTH_SYNTH4_OFFSET 0x0000000c |
| 254 #define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 |
| 255 #define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 |
| 256 #define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 |
| 257 #define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CA
PSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) |
| 258 #define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_C
APSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) |
| 259 #define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 |
| 260 #define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 |
| 261 #define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 |
| 262 #define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC
_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) |
| 263 #define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTV
C_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) |
| 264 #define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 |
| 265 #define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 |
| 266 #define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 |
| 267 #define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHO
RTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) |
| 268 #define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SH
ORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) |
| 269 #define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 |
| 270 #define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 |
| 271 #define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 |
| 272 #define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNT
IL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) |
| 273 #define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UN
TIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) |
| 274 #define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 |
| 275 #define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 |
| 276 #define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 |
| 277 #define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINV
C_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) |
| 278 #define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PIN
VC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) |
| 279 #define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 |
| 280 #define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 |
| 281 #define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 |
| 282 #define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOC
AP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) |
| 283 #define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCO
CAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) |
| 284 #define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 |
| 285 #define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 |
| 286 #define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 |
| 287 #define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR
_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) |
| 288 #define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OV
R_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) |
| 289 #define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 |
| 290 #define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 |
| 291 #define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 |
| 292 #define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULL
UP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) |
| 293 #define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPUL
LUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) |
| 294 #define SYNTH_SYNTH4_REFDIVSEL_MSB 16 |
| 295 #define SYNTH_SYNTH4_REFDIVSEL_LSB 15 |
| 296 #define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 |
| 297 #define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_
MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) |
| 298 #define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL
_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) |
| 299 #define SYNTH_SYNTH4_PFDDELAY_MSB 14 |
| 300 #define SYNTH_SYNTH4_PFDDELAY_LSB 14 |
| 301 #define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 |
| 302 #define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_M
ASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) |
| 303 #define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_
LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) |
| 304 #define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 |
| 305 #define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 |
| 306 #define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 |
| 307 #define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABL
E_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) |
| 308 #define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISAB
LE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) |
| 309 #define SYNTH_SYNTH4_PRESCSEL_MSB 12 |
| 310 #define SYNTH_SYNTH4_PRESCSEL_LSB 11 |
| 311 #define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 |
| 312 #define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_M
ASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) |
| 313 #define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_
LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) |
| 314 #define SYNTH_SYNTH4_RESET_PRESC_MSB 10 |
| 315 #define SYNTH_SYNTH4_RESET_PRESC_LSB 10 |
| 316 #define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 |
| 317 #define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRES
C_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) |
| 318 #define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRE
SC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) |
| 319 #define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 |
| 320 #define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 |
| 321 #define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 |
| 322 #define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABL
E_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) |
| 323 #define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISAB
LE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) |
| 324 #define SYNTH_SYNTH4_SDM_MODE_MSB 8 |
| 325 #define SYNTH_SYNTH4_SDM_MODE_LSB 8 |
| 326 #define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 |
| 327 #define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_M
ASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) |
| 328 #define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_
LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) |
| 329 #define SYNTH_SYNTH4_SDM_DITHER_MSB 7 |
| 330 #define SYNTH_SYNTH4_SDM_DITHER_LSB 6 |
| 331 #define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 |
| 332 #define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER
_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) |
| 333 #define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHE
R_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) |
| 334 #define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 |
| 335 #define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 |
| 336 #define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 |
| 337 #define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FB
SEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) |
| 338 #define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_F
BSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) |
| 339 #define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 |
| 340 #define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 |
| 341 #define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 |
| 342 #define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTA
L_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) |
| 343 #define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXT
AL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) |
| 344 #define SYNTH_SYNTH4_SPARE_MISC_MSB 3 |
| 345 #define SYNTH_SYNTH4_SPARE_MISC_LSB 2 |
| 346 #define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c |
| 347 #define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC
_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) |
| 348 #define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MIS
C_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) |
| 349 #define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 |
| 350 #define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 |
| 351 #define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 |
| 352 #define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTS
EL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) |
| 353 #define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFT
SEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) |
| 354 #define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 |
| 355 #define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 |
| 356 #define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 |
| 357 #define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIF
TREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) |
| 358 #define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHI
FTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) |
| 359 |
| 360 #define SYNTH_SYNTH5_ADDRESS 0x00000010 |
| 361 #define SYNTH_SYNTH5_OFFSET 0x00000010 |
| 362 #define SYNTH_SYNTH5_LOOP_IP0_MSB 31 |
| 363 #define SYNTH_SYNTH5_LOOP_IP0_LSB 28 |
| 364 #define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 |
| 365 #define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_M
ASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) |
| 366 #define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_
LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) |
| 367 #define SYNTH_SYNTH5_SLOPE_IP_MSB 27 |
| 368 #define SYNTH_SYNTH5_SLOPE_IP_LSB 25 |
| 369 #define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 |
| 370 #define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_M
ASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) |
| 371 #define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_
LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) |
| 372 #define SYNTH_SYNTH5_CPBIAS_MSB 24 |
| 373 #define SYNTH_SYNTH5_CPBIAS_LSB 23 |
| 374 #define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 |
| 375 #define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MAS
K) >> SYNTH_SYNTH5_CPBIAS_LSB) |
| 376 #define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LS
B) & SYNTH_SYNTH5_CPBIAS_MASK) |
| 377 #define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 |
| 378 #define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 |
| 379 #define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 |
| 380 #define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING
_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) |
| 381 #define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERIN
G_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) |
| 382 #define SYNTH_SYNTH5_CPLOWLK_MSB 21 |
| 383 #define SYNTH_SYNTH5_CPLOWLK_LSB 21 |
| 384 #define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 |
| 385 #define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MA
SK) >> SYNTH_SYNTH5_CPLOWLK_LSB) |
| 386 #define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_L
SB) & SYNTH_SYNTH5_CPLOWLK_MASK) |
| 387 #define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 |
| 388 #define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 |
| 389 #define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 |
| 390 #define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCU
R_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) |
| 391 #define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKC
UR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) |
| 392 #define SYNTH_SYNTH5_CAPRANGE1_MSB 16 |
| 393 #define SYNTH_SYNTH5_CAPRANGE1_LSB 13 |
| 394 #define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 |
| 395 #define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_
MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) |
| 396 #define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1
_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) |
| 397 #define SYNTH_SYNTH5_CAPRANGE2_MSB 12 |
| 398 #define SYNTH_SYNTH5_CAPRANGE2_LSB 9 |
| 399 #define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 |
| 400 #define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_
MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) |
| 401 #define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2
_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) |
| 402 #define SYNTH_SYNTH5_CAPRANGE3_MSB 8 |
| 403 #define SYNTH_SYNTH5_CAPRANGE3_LSB 5 |
| 404 #define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 |
| 405 #define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_
MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) |
| 406 #define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3
_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) |
| 407 #define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 |
| 408 #define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 |
| 409 #define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 |
| 410 #define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBU
F5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) |
| 411 #define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOB
UF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) |
| 412 #define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 |
| 413 #define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 |
| 414 #define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c |
| 415 #define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUN
E_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) |
| 416 #define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTU
NE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) |
| 417 #define SYNTH_SYNTH5_SPARE_MSB 1 |
| 418 #define SYNTH_SYNTH5_SPARE_LSB 0 |
| 419 #define SYNTH_SYNTH5_SPARE_MASK 0x00000003 |
| 420 #define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK
) >> SYNTH_SYNTH5_SPARE_LSB) |
| 421 #define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB
) & SYNTH_SYNTH5_SPARE_MASK) |
| 422 |
| 423 #define SYNTH_SYNTH6_ADDRESS 0x00000014 |
| 424 #define SYNTH_SYNTH6_OFFSET 0x00000014 |
| 425 #define SYNTH_SYNTH6_IRCP_MSB 31 |
| 426 #define SYNTH_SYNTH6_IRCP_LSB 29 |
| 427 #define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 |
| 428 #define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK)
>> SYNTH_SYNTH6_IRCP_LSB) |
| 429 #define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB)
& SYNTH_SYNTH6_IRCP_MASK) |
| 430 #define SYNTH_SYNTH6_IRVCMON_MSB 28 |
| 431 #define SYNTH_SYNTH6_IRVCMON_LSB 26 |
| 432 #define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 |
| 433 #define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MA
SK) >> SYNTH_SYNTH6_IRVCMON_LSB) |
| 434 #define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_L
SB) & SYNTH_SYNTH6_IRVCMON_MASK) |
| 435 #define SYNTH_SYNTH6_IRSPARE_MSB 25 |
| 436 #define SYNTH_SYNTH6_IRSPARE_LSB 23 |
| 437 #define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 |
| 438 #define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MA
SK) >> SYNTH_SYNTH6_IRSPARE_LSB) |
| 439 #define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_L
SB) & SYNTH_SYNTH6_IRSPARE_MASK) |
| 440 #define SYNTH_SYNTH6_ICPRESC_MSB 22 |
| 441 #define SYNTH_SYNTH6_ICPRESC_LSB 20 |
| 442 #define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 |
| 443 #define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MA
SK) >> SYNTH_SYNTH6_ICPRESC_LSB) |
| 444 #define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_L
SB) & SYNTH_SYNTH6_ICPRESC_MASK) |
| 445 #define SYNTH_SYNTH6_ICLODIV_MSB 19 |
| 446 #define SYNTH_SYNTH6_ICLODIV_LSB 17 |
| 447 #define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 |
| 448 #define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MA
SK) >> SYNTH_SYNTH6_ICLODIV_LSB) |
| 449 #define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_L
SB) & SYNTH_SYNTH6_ICLODIV_MASK) |
| 450 #define SYNTH_SYNTH6_ICLOMIX_MSB 16 |
| 451 #define SYNTH_SYNTH6_ICLOMIX_LSB 14 |
| 452 #define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 |
| 453 #define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MA
SK) >> SYNTH_SYNTH6_ICLOMIX_LSB) |
| 454 #define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_L
SB) & SYNTH_SYNTH6_ICLOMIX_MASK) |
| 455 #define SYNTH_SYNTH6_ICSPAREA_MSB 13 |
| 456 #define SYNTH_SYNTH6_ICSPAREA_LSB 11 |
| 457 #define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 |
| 458 #define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_M
ASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) |
| 459 #define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_
LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) |
| 460 #define SYNTH_SYNTH6_ICSPAREB_MSB 10 |
| 461 #define SYNTH_SYNTH6_ICSPAREB_LSB 8 |
| 462 #define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 |
| 463 #define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_M
ASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) |
| 464 #define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_
LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) |
| 465 #define SYNTH_SYNTH6_ICVCO_MSB 7 |
| 466 #define SYNTH_SYNTH6_ICVCO_LSB 5 |
| 467 #define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 |
| 468 #define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK
) >> SYNTH_SYNTH6_ICVCO_LSB) |
| 469 #define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB
) & SYNTH_SYNTH6_ICVCO_MASK) |
| 470 #define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 |
| 471 #define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 |
| 472 #define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 |
| 473 #define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS
_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) |
| 474 #define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIA
S_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) |
| 475 #define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 |
| 476 #define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 |
| 477 #define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 |
| 478 #define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS
_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) |
| 479 #define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIA
S_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) |
| 480 |
| 481 #define SYNTH_SYNTH7_ADDRESS 0x00000018 |
| 482 #define SYNTH_SYNTH7_OFFSET 0x00000018 |
| 483 #define SYNTH_SYNTH7_SYNTH_ON_MSB 31 |
| 484 #define SYNTH_SYNTH7_SYNTH_ON_LSB 31 |
| 485 #define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 |
| 486 #define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_M
ASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) |
| 487 #define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_
LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) |
| 488 #define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 |
| 489 #define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 |
| 490 #define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 |
| 491 #define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_S
TATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) |
| 492 #define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_
STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) |
| 493 #define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 |
| 494 #define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 |
| 495 #define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 |
| 496 #define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH
_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) |
| 497 #define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARC
H_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) |
| 498 #define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 |
| 499 #define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 |
| 500 #define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 |
| 501 #define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK
_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) |
| 502 #define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOC
K_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) |
| 503 #define SYNTH_SYNTH7_PIN_VC_MSB 24 |
| 504 #define SYNTH_SYNTH7_PIN_VC_LSB 24 |
| 505 #define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 |
| 506 #define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MAS
K) >> SYNTH_SYNTH7_PIN_VC_LSB) |
| 507 #define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LS
B) & SYNTH_SYNTH7_PIN_VC_MASK) |
| 508 #define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 |
| 509 #define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 |
| 510 #define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 |
| 511 #define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST
_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) |
| 512 #define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_S
T_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) |
| 513 #define SYNTH_SYNTH7_SHORT_R_MSB 15 |
| 514 #define SYNTH_SYNTH7_SHORT_R_LSB 15 |
| 515 #define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 |
| 516 #define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MA
SK) >> SYNTH_SYNTH7_SHORT_R_LSB) |
| 517 #define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_L
SB) & SYNTH_SYNTH7_SHORT_R_MASK) |
| 518 #define SYNTH_SYNTH7_RESET_RFD_MSB 14 |
| 519 #define SYNTH_SYNTH7_RESET_RFD_LSB 14 |
| 520 #define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 |
| 521 #define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_
MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) |
| 522 #define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD
_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) |
| 523 #define SYNTH_SYNTH7_RESET_PFD_MSB 13 |
| 524 #define SYNTH_SYNTH7_RESET_PFD_LSB 13 |
| 525 #define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 |
| 526 #define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_
MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) |
| 527 #define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD
_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) |
| 528 #define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 |
| 529 #define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 |
| 530 #define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 |
| 531 #define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCO
UNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) |
| 532 #define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSC
OUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) |
| 533 #define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 |
| 534 #define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 |
| 535 #define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 |
| 536 #define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_
B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) |
| 537 #define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM
_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) |
| 538 #define SYNTH_SYNTH7_VC2HIGH_MSB 10 |
| 539 #define SYNTH_SYNTH7_VC2HIGH_LSB 10 |
| 540 #define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 |
| 541 #define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MA
SK) >> SYNTH_SYNTH7_VC2HIGH_LSB) |
| 542 #define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_L
SB) & SYNTH_SYNTH7_VC2HIGH_MASK) |
| 543 #define SYNTH_SYNTH7_VC2LOW_MSB 9 |
| 544 #define SYNTH_SYNTH7_VC2LOW_LSB 9 |
| 545 #define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 |
| 546 #define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MAS
K) >> SYNTH_SYNTH7_VC2LOW_LSB) |
| 547 #define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LS
B) & SYNTH_SYNTH7_VC2LOW_MASK) |
| 548 #define SYNTH_SYNTH7_LOOP_IP_MSB 8 |
| 549 #define SYNTH_SYNTH7_LOOP_IP_LSB 5 |
| 550 #define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 |
| 551 #define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MA
SK) >> SYNTH_SYNTH7_LOOP_IP_LSB) |
| 552 #define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_L
SB) & SYNTH_SYNTH7_LOOP_IP_MASK) |
| 553 #define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 |
| 554 #define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 |
| 555 #define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 |
| 556 #define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUN
E_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) |
| 557 #define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTU
NE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) |
| 558 #define SYNTH_SYNTH7_SPARE_READ_MSB 2 |
| 559 #define SYNTH_SYNTH7_SPARE_READ_LSB 0 |
| 560 #define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 |
| 561 #define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ
_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) |
| 562 #define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_REA
D_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) |
| 563 |
| 564 #define SYNTH_SYNTH8_ADDRESS 0x0000001c |
| 565 #define SYNTH_SYNTH8_OFFSET 0x0000001c |
| 566 #define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 |
| 567 #define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 |
| 568 #define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 |
| 569 #define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHC
HANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) |
| 570 #define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTH
CHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) |
| 571 #define SYNTH_SYNTH8_FRACMODE_MSB 30 |
| 572 #define SYNTH_SYNTH8_FRACMODE_LSB 30 |
| 573 #define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 |
| 574 #define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_M
ASK) >> SYNTH_SYNTH8_FRACMODE_LSB) |
| 575 #define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_
LSB) & SYNTH_SYNTH8_FRACMODE_MASK) |
| 576 #define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 |
| 577 #define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 |
| 578 #define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 |
| 579 #define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSE
L_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) |
| 580 #define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFS
EL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) |
| 581 #define SYNTH_SYNTH8_SPARE_MSB 27 |
| 582 #define SYNTH_SYNTH8_SPARE_LSB 27 |
| 583 #define SYNTH_SYNTH8_SPARE_MASK 0x08000000 |
| 584 #define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK
) >> SYNTH_SYNTH8_SPARE_LSB) |
| 585 #define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB
) & SYNTH_SYNTH8_SPARE_MASK) |
| 586 #define SYNTH_SYNTH8_CHANSEL_MSB 26 |
| 587 #define SYNTH_SYNTH8_CHANSEL_LSB 18 |
| 588 #define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 |
| 589 #define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MA
SK) >> SYNTH_SYNTH8_CHANSEL_LSB) |
| 590 #define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_L
SB) & SYNTH_SYNTH8_CHANSEL_MASK) |
| 591 #define SYNTH_SYNTH8_CHANFRAC_MSB 17 |
| 592 #define SYNTH_SYNTH8_CHANFRAC_LSB 1 |
| 593 #define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe |
| 594 #define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_M
ASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) |
| 595 #define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_
LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) |
| 596 #define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 |
| 597 #define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 |
| 598 #define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 |
| 599 #define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRAC
LSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) |
| 600 #define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRA
CLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) |
| 601 |
| 602 #define RF5G_RF5G1_ADDRESS 0x00000020 |
| 603 #define RF5G_RF5G1_OFFSET 0x00000020 |
| 604 #define RF5G_RF5G1_PDTXLO5_MSB 31 |
| 605 #define RF5G_RF5G1_PDTXLO5_LSB 31 |
| 606 #define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 |
| 607 #define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK
) >> RF5G_RF5G1_PDTXLO5_LSB) |
| 608 #define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB
) & RF5G_RF5G1_PDTXLO5_MASK) |
| 609 #define RF5G_RF5G1_PDTXMIX5_MSB 30 |
| 610 #define RF5G_RF5G1_PDTXMIX5_LSB 30 |
| 611 #define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 |
| 612 #define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MAS
K) >> RF5G_RF5G1_PDTXMIX5_LSB) |
| 613 #define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LS
B) & RF5G_RF5G1_PDTXMIX5_MASK) |
| 614 #define RF5G_RF5G1_PDTXBUF5_MSB 29 |
| 615 #define RF5G_RF5G1_PDTXBUF5_LSB 29 |
| 616 #define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 |
| 617 #define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MAS
K) >> RF5G_RF5G1_PDTXBUF5_LSB) |
| 618 #define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LS
B) & RF5G_RF5G1_PDTXBUF5_MASK) |
| 619 #define RF5G_RF5G1_PDPADRV5_MSB 28 |
| 620 #define RF5G_RF5G1_PDPADRV5_LSB 28 |
| 621 #define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 |
| 622 #define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MAS
K) >> RF5G_RF5G1_PDPADRV5_LSB) |
| 623 #define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LS
B) & RF5G_RF5G1_PDPADRV5_MASK) |
| 624 #define RF5G_RF5G1_PDPAOUT5_MSB 27 |
| 625 #define RF5G_RF5G1_PDPAOUT5_LSB 27 |
| 626 #define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 |
| 627 #define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MAS
K) >> RF5G_RF5G1_PDPAOUT5_LSB) |
| 628 #define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LS
B) & RF5G_RF5G1_PDPAOUT5_MASK) |
| 629 #define RF5G_RF5G1_TUNE_PADRV5_MSB 26 |
| 630 #define RF5G_RF5G1_TUNE_PADRV5_LSB 24 |
| 631 #define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 |
| 632 #define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_
MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) |
| 633 #define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5
_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) |
| 634 #define RF5G_RF5G1_PWDTXPKD_MSB 23 |
| 635 #define RF5G_RF5G1_PWDTXPKD_LSB 21 |
| 636 #define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 |
| 637 #define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MAS
K) >> RF5G_RF5G1_PWDTXPKD_LSB) |
| 638 #define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LS
B) & RF5G_RF5G1_PWDTXPKD_MASK) |
| 639 #define RF5G_RF5G1_DB5_MSB 20 |
| 640 #define RF5G_RF5G1_DB5_LSB 18 |
| 641 #define RF5G_RF5G1_DB5_MASK 0x001c0000 |
| 642 #define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >>
RF5G_RF5G1_DB5_LSB) |
| 643 #define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) &
RF5G_RF5G1_DB5_MASK) |
| 644 #define RF5G_RF5G1_OB5_MSB 17 |
| 645 #define RF5G_RF5G1_OB5_LSB 15 |
| 646 #define RF5G_RF5G1_OB5_MASK 0x00038000 |
| 647 #define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >>
RF5G_RF5G1_OB5_LSB) |
| 648 #define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) &
RF5G_RF5G1_OB5_MASK) |
| 649 #define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 |
| 650 #define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 |
| 651 #define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 |
| 652 #define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_
MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) |
| 653 #define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL
_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) |
| 654 #define RF5G_RF5G1_PDLO5DIV_MSB 11 |
| 655 #define RF5G_RF5G1_PDLO5DIV_LSB 11 |
| 656 #define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 |
| 657 #define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MAS
K) >> RF5G_RF5G1_PDLO5DIV_LSB) |
| 658 #define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LS
B) & RF5G_RF5G1_PDLO5DIV_MASK) |
| 659 #define RF5G_RF5G1_PDLO5MIX_MSB 10 |
| 660 #define RF5G_RF5G1_PDLO5MIX_LSB 10 |
| 661 #define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 |
| 662 #define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MAS
K) >> RF5G_RF5G1_PDLO5MIX_LSB) |
| 663 #define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LS
B) & RF5G_RF5G1_PDLO5MIX_MASK) |
| 664 #define RF5G_RF5G1_PDQBUF5_MSB 9 |
| 665 #define RF5G_RF5G1_PDQBUF5_LSB 9 |
| 666 #define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 |
| 667 #define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK
) >> RF5G_RF5G1_PDQBUF5_LSB) |
| 668 #define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB
) & RF5G_RF5G1_PDQBUF5_MASK) |
| 669 #define RF5G_RF5G1_PDLO5AGC_MSB 8 |
| 670 #define RF5G_RF5G1_PDLO5AGC_LSB 8 |
| 671 #define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 |
| 672 #define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MAS
K) >> RF5G_RF5G1_PDLO5AGC_LSB) |
| 673 #define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LS
B) & RF5G_RF5G1_PDLO5AGC_MASK) |
| 674 #define RF5G_RF5G1_PDREGLO5_MSB 7 |
| 675 #define RF5G_RF5G1_PDREGLO5_LSB 7 |
| 676 #define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 |
| 677 #define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MAS
K) >> RF5G_RF5G1_PDREGLO5_LSB) |
| 678 #define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LS
B) & RF5G_RF5G1_PDREGLO5_MASK) |
| 679 #define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 |
| 680 #define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 |
| 681 #define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 |
| 682 #define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_
MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) |
| 683 #define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL
_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) |
| 684 #define RF5G_RF5G1_LO5CONTROL_MSB 3 |
| 685 #define RF5G_RF5G1_LO5CONTROL_LSB 3 |
| 686 #define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 |
| 687 #define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_M
ASK) >> RF5G_RF5G1_LO5CONTROL_LSB) |
| 688 #define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_
LSB) & RF5G_RF5G1_LO5CONTROL_MASK) |
| 689 #define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 |
| 690 #define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 |
| 691 #define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 |
| 692 #define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS
5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) |
| 693 #define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPAS
S5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) |
| 694 #define RF5G_RF5G1_SPARE_MSB 1 |
| 695 #define RF5G_RF5G1_SPARE_LSB 0 |
| 696 #define RF5G_RF5G1_SPARE_MASK 0x00000003 |
| 697 #define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK)
>> RF5G_RF5G1_SPARE_LSB) |
| 698 #define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB)
& RF5G_RF5G1_SPARE_MASK) |
| 699 |
| 700 #define RF5G_RF5G2_ADDRESS 0x00000024 |
| 701 #define RF5G_RF5G2_OFFSET 0x00000024 |
| 702 #define RF5G_RF5G2_AGCLO_B_MSB 31 |
| 703 #define RF5G_RF5G2_AGCLO_B_LSB 29 |
| 704 #define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 |
| 705 #define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK
) >> RF5G_RF5G2_AGCLO_B_LSB) |
| 706 #define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB
) & RF5G_RF5G2_AGCLO_B_MASK) |
| 707 #define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 |
| 708 #define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 |
| 709 #define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 |
| 710 #define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_
MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) |
| 711 #define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL
_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) |
| 712 #define RF5G_RF5G2_PDCMOSLO5_MSB 25 |
| 713 #define RF5G_RF5G2_PDCMOSLO5_LSB 25 |
| 714 #define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 |
| 715 #define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MA
SK) >> RF5G_RF5G2_PDCMOSLO5_LSB) |
| 716 #define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_L
SB) & RF5G_RF5G2_PDCMOSLO5_MASK) |
| 717 #define RF5G_RF5G2_PDVGM5_MSB 24 |
| 718 #define RF5G_RF5G2_PDVGM5_LSB 24 |
| 719 #define RF5G_RF5G2_PDVGM5_MASK 0x01000000 |
| 720 #define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK)
>> RF5G_RF5G2_PDVGM5_LSB) |
| 721 #define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB)
& RF5G_RF5G2_PDVGM5_MASK) |
| 722 #define RF5G_RF5G2_PDCSLNA5_MSB 23 |
| 723 #define RF5G_RF5G2_PDCSLNA5_LSB 23 |
| 724 #define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 |
| 725 #define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MAS
K) >> RF5G_RF5G2_PDCSLNA5_LSB) |
| 726 #define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LS
B) & RF5G_RF5G2_PDCSLNA5_MASK) |
| 727 #define RF5G_RF5G2_PDRFVGA5_MSB 22 |
| 728 #define RF5G_RF5G2_PDRFVGA5_LSB 22 |
| 729 #define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 |
| 730 #define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MAS
K) >> RF5G_RF5G2_PDRFVGA5_LSB) |
| 731 #define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LS
B) & RF5G_RF5G2_PDRFVGA5_MASK) |
| 732 #define RF5G_RF5G2_PDREGFE5_MSB 21 |
| 733 #define RF5G_RF5G2_PDREGFE5_LSB 21 |
| 734 #define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 |
| 735 #define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MAS
K) >> RF5G_RF5G2_PDREGFE5_LSB) |
| 736 #define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LS
B) & RF5G_RF5G2_PDREGFE5_MASK) |
| 737 #define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 |
| 738 #define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 |
| 739 #define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 |
| 740 #define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_
MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) |
| 741 #define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5
_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) |
| 742 #define RF5G_RF5G2_BRFVGA5_MSB 17 |
| 743 #define RF5G_RF5G2_BRFVGA5_LSB 15 |
| 744 #define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 |
| 745 #define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK
) >> RF5G_RF5G2_BRFVGA5_LSB) |
| 746 #define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB
) & RF5G_RF5G2_BRFVGA5_MASK) |
| 747 #define RF5G_RF5G2_BCSLNA5_MSB 14 |
| 748 #define RF5G_RF5G2_BCSLNA5_LSB 12 |
| 749 #define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 |
| 750 #define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK
) >> RF5G_RF5G2_BCSLNA5_LSB) |
| 751 #define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB
) & RF5G_RF5G2_BCSLNA5_MASK) |
| 752 #define RF5G_RF5G2_BVGM5_MSB 11 |
| 753 #define RF5G_RF5G2_BVGM5_LSB 9 |
| 754 #define RF5G_RF5G2_BVGM5_MASK 0x00000e00 |
| 755 #define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK)
>> RF5G_RF5G2_BVGM5_LSB) |
| 756 #define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB)
& RF5G_RF5G2_BVGM5_MASK) |
| 757 #define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 |
| 758 #define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 |
| 759 #define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 |
| 760 #define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS
5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) |
| 761 #define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPAS
S5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) |
| 762 #define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 |
| 763 #define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 |
| 764 #define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 |
| 765 #define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMO
DE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) |
| 766 #define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENM
ODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) |
| 767 #define RF5G_RF5G2_ENABLE_PCA_MSB 5 |
| 768 #define RF5G_RF5G2_ENABLE_PCA_LSB 5 |
| 769 #define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 |
| 770 #define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_M
ASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) |
| 771 #define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_
LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) |
| 772 #define RF5G_RF5G2_TUNE_LO_MSB 4 |
| 773 #define RF5G_RF5G2_TUNE_LO_LSB 2 |
| 774 #define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c |
| 775 #define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK
) >> RF5G_RF5G2_TUNE_LO_LSB) |
| 776 #define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB
) & RF5G_RF5G2_TUNE_LO_MASK) |
| 777 #define RF5G_RF5G2_SPARE_MSB 1 |
| 778 #define RF5G_RF5G2_SPARE_LSB 0 |
| 779 #define RF5G_RF5G2_SPARE_MASK 0x00000003 |
| 780 #define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK)
>> RF5G_RF5G2_SPARE_LSB) |
| 781 #define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB)
& RF5G_RF5G2_SPARE_MASK) |
| 782 |
| 783 #define RF2G_RF2G1_ADDRESS 0x00000028 |
| 784 #define RF2G_RF2G1_OFFSET 0x00000028 |
| 785 #define RF2G_RF2G1_BLNA1_MSB 31 |
| 786 #define RF2G_RF2G1_BLNA1_LSB 29 |
| 787 #define RF2G_RF2G1_BLNA1_MASK 0xe0000000 |
| 788 #define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK)
>> RF2G_RF2G1_BLNA1_LSB) |
| 789 #define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB)
& RF2G_RF2G1_BLNA1_MASK) |
| 790 #define RF2G_RF2G1_BLNA1F_MSB 28 |
| 791 #define RF2G_RF2G1_BLNA1F_LSB 26 |
| 792 #define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 |
| 793 #define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK)
>> RF2G_RF2G1_BLNA1F_LSB) |
| 794 #define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB)
& RF2G_RF2G1_BLNA1F_MASK) |
| 795 #define RF2G_RF2G1_BLNA1BUF_MSB 25 |
| 796 #define RF2G_RF2G1_BLNA1BUF_LSB 23 |
| 797 #define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 |
| 798 #define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MAS
K) >> RF2G_RF2G1_BLNA1BUF_LSB) |
| 799 #define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LS
B) & RF2G_RF2G1_BLNA1BUF_MASK) |
| 800 #define RF2G_RF2G1_BLNA2_MSB 22 |
| 801 #define RF2G_RF2G1_BLNA2_LSB 20 |
| 802 #define RF2G_RF2G1_BLNA2_MASK 0x00700000 |
| 803 #define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK)
>> RF2G_RF2G1_BLNA2_LSB) |
| 804 #define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB)
& RF2G_RF2G1_BLNA2_MASK) |
| 805 #define RF2G_RF2G1_DB_MSB 19 |
| 806 #define RF2G_RF2G1_DB_LSB 17 |
| 807 #define RF2G_RF2G1_DB_MASK 0x000e0000 |
| 808 #define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >>
RF2G_RF2G1_DB_LSB) |
| 809 #define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & R
F2G_RF2G1_DB_MASK) |
| 810 #define RF2G_RF2G1_OB_MSB 16 |
| 811 #define RF2G_RF2G1_OB_LSB 14 |
| 812 #define RF2G_RF2G1_OB_MASK 0x0001c000 |
| 813 #define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >>
RF2G_RF2G1_OB_LSB) |
| 814 #define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & R
F2G_RF2G1_OB_MASK) |
| 815 #define RF2G_RF2G1_FE_ATB_SEL_MSB 13 |
| 816 #define RF2G_RF2G1_FE_ATB_SEL_LSB 11 |
| 817 #define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 |
| 818 #define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_M
ASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) |
| 819 #define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_
LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) |
| 820 #define RF2G_RF2G1_RF_ATB_SEL_MSB 10 |
| 821 #define RF2G_RF2G1_RF_ATB_SEL_LSB 8 |
| 822 #define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 |
| 823 #define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_M
ASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) |
| 824 #define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_
LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) |
| 825 #define RF2G_RF2G1_SELLNA_MSB 7 |
| 826 #define RF2G_RF2G1_SELLNA_LSB 7 |
| 827 #define RF2G_RF2G1_SELLNA_MASK 0x00000080 |
| 828 #define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK)
>> RF2G_RF2G1_SELLNA_LSB) |
| 829 #define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB)
& RF2G_RF2G1_SELLNA_MASK) |
| 830 #define RF2G_RF2G1_LOCONTROL_MSB 6 |
| 831 #define RF2G_RF2G1_LOCONTROL_LSB 6 |
| 832 #define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 |
| 833 #define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MA
SK) >> RF2G_RF2G1_LOCONTROL_LSB) |
| 834 #define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_L
SB) & RF2G_RF2G1_LOCONTROL_MASK) |
| 835 #define RF2G_RF2G1_SHORTLNA2_MSB 5 |
| 836 #define RF2G_RF2G1_SHORTLNA2_LSB 5 |
| 837 #define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 |
| 838 #define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MA
SK) >> RF2G_RF2G1_SHORTLNA2_LSB) |
| 839 #define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_L
SB) & RF2G_RF2G1_SHORTLNA2_MASK) |
| 840 #define RF2G_RF2G1_SPARE_MSB 4 |
| 841 #define RF2G_RF2G1_SPARE_LSB 0 |
| 842 #define RF2G_RF2G1_SPARE_MASK 0x0000001f |
| 843 #define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK)
>> RF2G_RF2G1_SPARE_LSB) |
| 844 #define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB)
& RF2G_RF2G1_SPARE_MASK) |
| 845 |
| 846 #define RF2G_RF2G2_ADDRESS 0x0000002c |
| 847 #define RF2G_RF2G2_OFFSET 0x0000002c |
| 848 #define RF2G_RF2G2_PDCGLNA_MSB 31 |
| 849 #define RF2G_RF2G2_PDCGLNA_LSB 31 |
| 850 #define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 |
| 851 #define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK
) >> RF2G_RF2G2_PDCGLNA_LSB) |
| 852 #define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB
) & RF2G_RF2G2_PDCGLNA_MASK) |
| 853 #define RF2G_RF2G2_PDCGLNABUF_MSB 30 |
| 854 #define RF2G_RF2G2_PDCGLNABUF_LSB 30 |
| 855 #define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 |
| 856 #define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_M
ASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) |
| 857 #define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_
LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) |
| 858 #define RF2G_RF2G2_PDCSLNA_MSB 29 |
| 859 #define RF2G_RF2G2_PDCSLNA_LSB 29 |
| 860 #define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 |
| 861 #define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK
) >> RF2G_RF2G2_PDCSLNA_LSB) |
| 862 #define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB
) & RF2G_RF2G2_PDCSLNA_MASK) |
| 863 #define RF2G_RF2G2_PDDIV_MSB 28 |
| 864 #define RF2G_RF2G2_PDDIV_LSB 28 |
| 865 #define RF2G_RF2G2_PDDIV_MASK 0x10000000 |
| 866 #define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK)
>> RF2G_RF2G2_PDDIV_LSB) |
| 867 #define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB)
& RF2G_RF2G2_PDDIV_MASK) |
| 868 #define RF2G_RF2G2_PDPADRV_MSB 27 |
| 869 #define RF2G_RF2G2_PDPADRV_LSB 27 |
| 870 #define RF2G_RF2G2_PDPADRV_MASK 0x08000000 |
| 871 #define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK
) >> RF2G_RF2G2_PDPADRV_LSB) |
| 872 #define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB
) & RF2G_RF2G2_PDPADRV_MASK) |
| 873 #define RF2G_RF2G2_PDPAOUT_MSB 26 |
| 874 #define RF2G_RF2G2_PDPAOUT_LSB 26 |
| 875 #define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 |
| 876 #define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK
) >> RF2G_RF2G2_PDPAOUT_LSB) |
| 877 #define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB
) & RF2G_RF2G2_PDPAOUT_MASK) |
| 878 #define RF2G_RF2G2_PDREGLNA_MSB 25 |
| 879 #define RF2G_RF2G2_PDREGLNA_LSB 25 |
| 880 #define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 |
| 881 #define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MAS
K) >> RF2G_RF2G2_PDREGLNA_LSB) |
| 882 #define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LS
B) & RF2G_RF2G2_PDREGLNA_MASK) |
| 883 #define RF2G_RF2G2_PDREGLO_MSB 24 |
| 884 #define RF2G_RF2G2_PDREGLO_LSB 24 |
| 885 #define RF2G_RF2G2_PDREGLO_MASK 0x01000000 |
| 886 #define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK
) >> RF2G_RF2G2_PDREGLO_LSB) |
| 887 #define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB
) & RF2G_RF2G2_PDREGLO_MASK) |
| 888 #define RF2G_RF2G2_PDRFGM_MSB 23 |
| 889 #define RF2G_RF2G2_PDRFGM_LSB 23 |
| 890 #define RF2G_RF2G2_PDRFGM_MASK 0x00800000 |
| 891 #define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK)
>> RF2G_RF2G2_PDRFGM_LSB) |
| 892 #define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB)
& RF2G_RF2G2_PDRFGM_MASK) |
| 893 #define RF2G_RF2G2_PDRXLO_MSB 22 |
| 894 #define RF2G_RF2G2_PDRXLO_LSB 22 |
| 895 #define RF2G_RF2G2_PDRXLO_MASK 0x00400000 |
| 896 #define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK)
>> RF2G_RF2G2_PDRXLO_LSB) |
| 897 #define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB)
& RF2G_RF2G2_PDRXLO_MASK) |
| 898 #define RF2G_RF2G2_PDTXLO_MSB 21 |
| 899 #define RF2G_RF2G2_PDTXLO_LSB 21 |
| 900 #define RF2G_RF2G2_PDTXLO_MASK 0x00200000 |
| 901 #define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK)
>> RF2G_RF2G2_PDTXLO_LSB) |
| 902 #define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB)
& RF2G_RF2G2_PDTXLO_MASK) |
| 903 #define RF2G_RF2G2_PDTXMIX_MSB 20 |
| 904 #define RF2G_RF2G2_PDTXMIX_LSB 20 |
| 905 #define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 |
| 906 #define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK
) >> RF2G_RF2G2_PDTXMIX_LSB) |
| 907 #define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB
) & RF2G_RF2G2_PDTXMIX_MASK) |
| 908 #define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 |
| 909 #define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 |
| 910 #define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 |
| 911 #define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPAS
S_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) |
| 912 #define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPA
SS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) |
| 913 #define RF2G_RF2G2_REGLO_BYPASS_MSB 18 |
| 914 #define RF2G_RF2G2_REGLO_BYPASS_LSB 18 |
| 915 #define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 |
| 916 #define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS
_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) |
| 917 #define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPAS
S_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) |
| 918 #define RF2G_RF2G2_ENABLE_PCB_MSB 17 |
| 919 #define RF2G_RF2G2_ENABLE_PCB_LSB 17 |
| 920 #define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 |
| 921 #define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_M
ASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) |
| 922 #define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_
LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) |
| 923 #define RF2G_RF2G2_SPARE_MSB 16 |
| 924 #define RF2G_RF2G2_SPARE_LSB 0 |
| 925 #define RF2G_RF2G2_SPARE_MASK 0x0001ffff |
| 926 #define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK)
>> RF2G_RF2G2_SPARE_LSB) |
| 927 #define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB)
& RF2G_RF2G2_SPARE_MASK) |
| 928 |
| 929 #define TOP_GAIN_ADDRESS 0x00000030 |
| 930 #define TOP_GAIN_OFFSET 0x00000030 |
| 931 #define TOP_GAIN_TX6DBLOQGAIN_MSB 31 |
| 932 #define TOP_GAIN_TX6DBLOQGAIN_LSB 30 |
| 933 #define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 |
| 934 #define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_M
ASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) |
| 935 #define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_
LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) |
| 936 #define TOP_GAIN_TX1DBLOQGAIN_MSB 29 |
| 937 #define TOP_GAIN_TX1DBLOQGAIN_LSB 27 |
| 938 #define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 |
| 939 #define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_M
ASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) |
| 940 #define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_
LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) |
| 941 #define TOP_GAIN_TXV2IGAIN_MSB 26 |
| 942 #define TOP_GAIN_TXV2IGAIN_LSB 25 |
| 943 #define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 |
| 944 #define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK
) >> TOP_GAIN_TXV2IGAIN_LSB) |
| 945 #define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB
) & TOP_GAIN_TXV2IGAIN_MASK) |
| 946 #define TOP_GAIN_PABUF5GN_MSB 24 |
| 947 #define TOP_GAIN_PABUF5GN_LSB 24 |
| 948 #define TOP_GAIN_PABUF5GN_MASK 0x01000000 |
| 949 #define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK)
>> TOP_GAIN_PABUF5GN_LSB) |
| 950 #define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB)
& TOP_GAIN_PABUF5GN_MASK) |
| 951 #define TOP_GAIN_PADRVGN_MSB 23 |
| 952 #define TOP_GAIN_PADRVGN_LSB 21 |
| 953 #define TOP_GAIN_PADRVGN_MASK 0x00e00000 |
| 954 #define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK)
>> TOP_GAIN_PADRVGN_LSB) |
| 955 #define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB)
& TOP_GAIN_PADRVGN_MASK) |
| 956 #define TOP_GAIN_PAOUT2GN_MSB 20 |
| 957 #define TOP_GAIN_PAOUT2GN_LSB 18 |
| 958 #define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 |
| 959 #define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK)
>> TOP_GAIN_PAOUT2GN_LSB) |
| 960 #define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB)
& TOP_GAIN_PAOUT2GN_MASK) |
| 961 #define TOP_GAIN_LNAON_MSB 17 |
| 962 #define TOP_GAIN_LNAON_LSB 17 |
| 963 #define TOP_GAIN_LNAON_MASK 0x00020000 |
| 964 #define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >>
TOP_GAIN_LNAON_LSB) |
| 965 #define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) &
TOP_GAIN_LNAON_MASK) |
| 966 #define TOP_GAIN_LNAGAIN_MSB 16 |
| 967 #define TOP_GAIN_LNAGAIN_LSB 13 |
| 968 #define TOP_GAIN_LNAGAIN_MASK 0x0001e000 |
| 969 #define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK)
>> TOP_GAIN_LNAGAIN_LSB) |
| 970 #define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB)
& TOP_GAIN_LNAGAIN_MASK) |
| 971 #define TOP_GAIN_RFVGA5GAIN_MSB 12 |
| 972 #define TOP_GAIN_RFVGA5GAIN_LSB 11 |
| 973 #define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 |
| 974 #define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MAS
K) >> TOP_GAIN_RFVGA5GAIN_LSB) |
| 975 #define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LS
B) & TOP_GAIN_RFVGA5GAIN_MASK) |
| 976 #define TOP_GAIN_RFGMGN_MSB 10 |
| 977 #define TOP_GAIN_RFGMGN_LSB 8 |
| 978 #define TOP_GAIN_RFGMGN_MASK 0x00000700 |
| 979 #define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >
> TOP_GAIN_RFGMGN_LSB) |
| 980 #define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) &
TOP_GAIN_RFGMGN_MASK) |
| 981 #define TOP_GAIN_RX6DBLOQGAIN_MSB 7 |
| 982 #define TOP_GAIN_RX6DBLOQGAIN_LSB 6 |
| 983 #define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 |
| 984 #define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_M
ASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) |
| 985 #define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_
LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) |
| 986 #define TOP_GAIN_RX1DBLOQGAIN_MSB 5 |
| 987 #define TOP_GAIN_RX1DBLOQGAIN_LSB 3 |
| 988 #define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 |
| 989 #define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_M
ASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) |
| 990 #define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_
LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) |
| 991 #define TOP_GAIN_RX6DBHIQGAIN_MSB 2 |
| 992 #define TOP_GAIN_RX6DBHIQGAIN_LSB 1 |
| 993 #define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 |
| 994 #define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_M
ASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) |
| 995 #define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_
LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) |
| 996 #define TOP_GAIN_SPARE_MSB 0 |
| 997 #define TOP_GAIN_SPARE_LSB 0 |
| 998 #define TOP_GAIN_SPARE_MASK 0x00000001 |
| 999 #define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >>
TOP_GAIN_SPARE_LSB) |
| 1000 #define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) &
TOP_GAIN_SPARE_MASK) |
| 1001 |
| 1002 #define TOP_TOP_ADDRESS 0x00000034 |
| 1003 #define TOP_TOP_OFFSET 0x00000034 |
| 1004 #define TOP_TOP_LOCALTXGAIN_MSB 31 |
| 1005 #define TOP_TOP_LOCALTXGAIN_LSB 31 |
| 1006 #define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 |
| 1007 #define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MAS
K) >> TOP_TOP_LOCALTXGAIN_LSB) |
| 1008 #define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LS
B) & TOP_TOP_LOCALTXGAIN_MASK) |
| 1009 #define TOP_TOP_LOCALRXGAIN_MSB 30 |
| 1010 #define TOP_TOP_LOCALRXGAIN_LSB 30 |
| 1011 #define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 |
| 1012 #define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MAS
K) >> TOP_TOP_LOCALRXGAIN_LSB) |
| 1013 #define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LS
B) & TOP_TOP_LOCALRXGAIN_MASK) |
| 1014 #define TOP_TOP_LOCALMODE_MSB 29 |
| 1015 #define TOP_TOP_LOCALMODE_LSB 29 |
| 1016 #define TOP_TOP_LOCALMODE_MASK 0x20000000 |
| 1017 #define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK)
>> TOP_TOP_LOCALMODE_LSB) |
| 1018 #define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB)
& TOP_TOP_LOCALMODE_MASK) |
| 1019 #define TOP_TOP_CALFC_MSB 28 |
| 1020 #define TOP_TOP_CALFC_LSB 28 |
| 1021 #define TOP_TOP_CALFC_MASK 0x10000000 |
| 1022 #define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >>
TOP_TOP_CALFC_LSB) |
| 1023 #define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & T
OP_TOP_CALFC_MASK) |
| 1024 #define TOP_TOP_CALDC_MSB 27 |
| 1025 #define TOP_TOP_CALDC_LSB 27 |
| 1026 #define TOP_TOP_CALDC_MASK 0x08000000 |
| 1027 #define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >>
TOP_TOP_CALDC_LSB) |
| 1028 #define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & T
OP_TOP_CALDC_MASK) |
| 1029 #define TOP_TOP_CAL_RESIDUE_MSB 26 |
| 1030 #define TOP_TOP_CAL_RESIDUE_LSB 26 |
| 1031 #define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 |
| 1032 #define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MAS
K) >> TOP_TOP_CAL_RESIDUE_LSB) |
| 1033 #define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LS
B) & TOP_TOP_CAL_RESIDUE_MASK) |
| 1034 #define TOP_TOP_BMODE_MSB 25 |
| 1035 #define TOP_TOP_BMODE_LSB 25 |
| 1036 #define TOP_TOP_BMODE_MASK 0x02000000 |
| 1037 #define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >>
TOP_TOP_BMODE_LSB) |
| 1038 #define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & T
OP_TOP_BMODE_MASK) |
| 1039 #define TOP_TOP_SYNTHON_MSB 24 |
| 1040 #define TOP_TOP_SYNTHON_LSB 24 |
| 1041 #define TOP_TOP_SYNTHON_MASK 0x01000000 |
| 1042 #define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >
> TOP_TOP_SYNTHON_LSB) |
| 1043 #define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) &
TOP_TOP_SYNTHON_MASK) |
| 1044 #define TOP_TOP_RXON_MSB 23 |
| 1045 #define TOP_TOP_RXON_LSB 23 |
| 1046 #define TOP_TOP_RXON_MASK 0x00800000 |
| 1047 #define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> T
OP_TOP_RXON_LSB) |
| 1048 #define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TO
P_TOP_RXON_MASK) |
| 1049 #define TOP_TOP_TXON_MSB 22 |
| 1050 #define TOP_TOP_TXON_LSB 22 |
| 1051 #define TOP_TOP_TXON_MASK 0x00400000 |
| 1052 #define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> T
OP_TOP_TXON_LSB) |
| 1053 #define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TO
P_TOP_TXON_MASK) |
| 1054 #define TOP_TOP_PAON_MSB 21 |
| 1055 #define TOP_TOP_PAON_LSB 21 |
| 1056 #define TOP_TOP_PAON_MASK 0x00200000 |
| 1057 #define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> T
OP_TOP_PAON_LSB) |
| 1058 #define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TO
P_TOP_PAON_MASK) |
| 1059 #define TOP_TOP_CALTX_MSB 20 |
| 1060 #define TOP_TOP_CALTX_LSB 20 |
| 1061 #define TOP_TOP_CALTX_MASK 0x00100000 |
| 1062 #define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >>
TOP_TOP_CALTX_LSB) |
| 1063 #define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & T
OP_TOP_CALTX_MASK) |
| 1064 #define TOP_TOP_LOCALADDAC_MSB 19 |
| 1065 #define TOP_TOP_LOCALADDAC_LSB 19 |
| 1066 #define TOP_TOP_LOCALADDAC_MASK 0x00080000 |
| 1067 #define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK
) >> TOP_TOP_LOCALADDAC_LSB) |
| 1068 #define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB
) & TOP_TOP_LOCALADDAC_MASK) |
| 1069 #define TOP_TOP_PWDPLL_MSB 18 |
| 1070 #define TOP_TOP_PWDPLL_LSB 18 |
| 1071 #define TOP_TOP_PWDPLL_MASK 0x00040000 |
| 1072 #define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >>
TOP_TOP_PWDPLL_LSB) |
| 1073 #define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) &
TOP_TOP_PWDPLL_MASK) |
| 1074 #define TOP_TOP_PWDADC_MSB 17 |
| 1075 #define TOP_TOP_PWDADC_LSB 17 |
| 1076 #define TOP_TOP_PWDADC_MASK 0x00020000 |
| 1077 #define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >>
TOP_TOP_PWDADC_LSB) |
| 1078 #define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) &
TOP_TOP_PWDADC_MASK) |
| 1079 #define TOP_TOP_PWDDAC_MSB 16 |
| 1080 #define TOP_TOP_PWDDAC_LSB 16 |
| 1081 #define TOP_TOP_PWDDAC_MASK 0x00010000 |
| 1082 #define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >>
TOP_TOP_PWDDAC_LSB) |
| 1083 #define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) &
TOP_TOP_PWDDAC_MASK) |
| 1084 #define TOP_TOP_LOCALXTAL_MSB 15 |
| 1085 #define TOP_TOP_LOCALXTAL_LSB 15 |
| 1086 #define TOP_TOP_LOCALXTAL_MASK 0x00008000 |
| 1087 #define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK)
>> TOP_TOP_LOCALXTAL_LSB) |
| 1088 #define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB)
& TOP_TOP_LOCALXTAL_MASK) |
| 1089 #define TOP_TOP_PWDCLKIN_MSB 14 |
| 1090 #define TOP_TOP_PWDCLKIN_LSB 14 |
| 1091 #define TOP_TOP_PWDCLKIN_MASK 0x00004000 |
| 1092 #define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK)
>> TOP_TOP_PWDCLKIN_LSB) |
| 1093 #define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB)
& TOP_TOP_PWDCLKIN_MASK) |
| 1094 #define TOP_TOP_OSCON_MSB 13 |
| 1095 #define TOP_TOP_OSCON_LSB 13 |
| 1096 #define TOP_TOP_OSCON_MASK 0x00002000 |
| 1097 #define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >>
TOP_TOP_OSCON_LSB) |
| 1098 #define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & T
OP_TOP_OSCON_MASK) |
| 1099 #define TOP_TOP_SCLKEN_FORCE_MSB 12 |
| 1100 #define TOP_TOP_SCLKEN_FORCE_LSB 12 |
| 1101 #define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 |
| 1102 #define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MA
SK) >> TOP_TOP_SCLKEN_FORCE_LSB) |
| 1103 #define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_L
SB) & TOP_TOP_SCLKEN_FORCE_MASK) |
| 1104 #define TOP_TOP_SYNTHON_FORCE_MSB 11 |
| 1105 #define TOP_TOP_SYNTHON_FORCE_LSB 11 |
| 1106 #define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 |
| 1107 #define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_M
ASK) >> TOP_TOP_SYNTHON_FORCE_LSB) |
| 1108 #define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_
LSB) & TOP_TOP_SYNTHON_FORCE_MASK) |
| 1109 #define TOP_TOP_PDBIAS_MSB 10 |
| 1110 #define TOP_TOP_PDBIAS_LSB 10 |
| 1111 #define TOP_TOP_PDBIAS_MASK 0x00000400 |
| 1112 #define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >>
TOP_TOP_PDBIAS_LSB) |
| 1113 #define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) &
TOP_TOP_PDBIAS_MASK) |
| 1114 #define TOP_TOP_DATAOUTSEL_MSB 9 |
| 1115 #define TOP_TOP_DATAOUTSEL_LSB 8 |
| 1116 #define TOP_TOP_DATAOUTSEL_MASK 0x00000300 |
| 1117 #define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK
) >> TOP_TOP_DATAOUTSEL_LSB) |
| 1118 #define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB
) & TOP_TOP_DATAOUTSEL_MASK) |
| 1119 #define TOP_TOP_REVID_MSB 7 |
| 1120 #define TOP_TOP_REVID_LSB 5 |
| 1121 #define TOP_TOP_REVID_MASK 0x000000e0 |
| 1122 #define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >>
TOP_TOP_REVID_LSB) |
| 1123 #define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & T
OP_TOP_REVID_MASK) |
| 1124 #define TOP_TOP_INT2PAD_MSB 4 |
| 1125 #define TOP_TOP_INT2PAD_LSB 4 |
| 1126 #define TOP_TOP_INT2PAD_MASK 0x00000010 |
| 1127 #define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >
> TOP_TOP_INT2PAD_LSB) |
| 1128 #define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) &
TOP_TOP_INT2PAD_MASK) |
| 1129 #define TOP_TOP_INTH2PAD_MSB 3 |
| 1130 #define TOP_TOP_INTH2PAD_LSB 3 |
| 1131 #define TOP_TOP_INTH2PAD_MASK 0x00000008 |
| 1132 #define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK)
>> TOP_TOP_INTH2PAD_LSB) |
| 1133 #define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB)
& TOP_TOP_INTH2PAD_MASK) |
| 1134 #define TOP_TOP_PAD2GND_MSB 2 |
| 1135 #define TOP_TOP_PAD2GND_LSB 2 |
| 1136 #define TOP_TOP_PAD2GND_MASK 0x00000004 |
| 1137 #define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >
> TOP_TOP_PAD2GND_LSB) |
| 1138 #define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) &
TOP_TOP_PAD2GND_MASK) |
| 1139 #define TOP_TOP_INT2GND_MSB 1 |
| 1140 #define TOP_TOP_INT2GND_LSB 1 |
| 1141 #define TOP_TOP_INT2GND_MASK 0x00000002 |
| 1142 #define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >
> TOP_TOP_INT2GND_LSB) |
| 1143 #define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) &
TOP_TOP_INT2GND_MASK) |
| 1144 #define TOP_TOP_FORCE_XPAON_MSB 0 |
| 1145 #define TOP_TOP_FORCE_XPAON_LSB 0 |
| 1146 #define TOP_TOP_FORCE_XPAON_MASK 0x00000001 |
| 1147 #define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MAS
K) >> TOP_TOP_FORCE_XPAON_LSB) |
| 1148 #define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LS
B) & TOP_TOP_FORCE_XPAON_MASK) |
| 1149 |
| 1150 #define BIAS_BIAS_SEL_ADDRESS 0x00000038 |
| 1151 #define BIAS_BIAS_SEL_OFFSET 0x00000038 |
| 1152 #define BIAS_BIAS_SEL_PADON_MSB 31 |
| 1153 #define BIAS_BIAS_SEL_PADON_LSB 31 |
| 1154 #define BIAS_BIAS_SEL_PADON_MASK 0x80000000 |
| 1155 #define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MAS
K) >> BIAS_BIAS_SEL_PADON_LSB) |
| 1156 #define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LS
B) & BIAS_BIAS_SEL_PADON_MASK) |
| 1157 #define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 |
| 1158 #define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 |
| 1159 #define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 |
| 1160 #define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_
MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) |
| 1161 #define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS
_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) |
| 1162 #define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 |
| 1163 #define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 |
| 1164 #define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 |
| 1165 #define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE
_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) |
| 1166 #define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPAR
E_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) |
| 1167 #define BIAS_BIAS_SEL_SPARE_MSB 20 |
| 1168 #define BIAS_BIAS_SEL_SPARE_LSB 20 |
| 1169 #define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 |
| 1170 #define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MAS
K) >> BIAS_BIAS_SEL_SPARE_LSB) |
| 1171 #define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LS
B) & BIAS_BIAS_SEL_SPARE_MASK) |
| 1172 #define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 |
| 1173 #define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 |
| 1174 #define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 |
| 1175 #define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICRE
FBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) |
| 1176 #define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICR
EFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) |
| 1177 #define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 |
| 1178 #define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 |
| 1179 #define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 |
| 1180 #define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDAC
REGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) |
| 1181 #define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDA
CREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) |
| 1182 #define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 |
| 1183 #define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 |
| 1184 #define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 |
| 1185 #define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_I
RREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) |
| 1186 #define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_
IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) |
| 1187 #define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 |
| 1188 #define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 |
| 1189 #define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 |
| 1190 #define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICRE
FOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) |
| 1191 #define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICR
EFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) |
| 1192 #define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 |
| 1193 #define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 |
| 1194 #define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 |
| 1195 #define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPL
L25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) |
| 1196 #define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCP
LL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) |
| 1197 #define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 |
| 1198 #define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 |
| 1199 #define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 |
| 1200 #define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOM
PBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) |
| 1201 #define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCO
MPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) |
| 1202 #define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 |
| 1203 #define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 |
| 1204 #define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 |
| 1205 #define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTA
L25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) |
| 1206 #define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXT
AL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) |
| 1207 #define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 |
| 1208 #define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 |
| 1209 #define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 |
| 1210 #define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSE
NS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) |
| 1211 #define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTS
ENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) |
| 1212 #define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 |
| 1213 #define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 |
| 1214 #define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e |
| 1215 #define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXP
C25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) |
| 1216 #define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTX
PC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) |
| 1217 #define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 |
| 1218 #define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 |
| 1219 #define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 |
| 1220 #define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO
25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) |
| 1221 #define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLD
O25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) |
| 1222 |
| 1223 #define BIAS_BIAS1_ADDRESS 0x0000003c |
| 1224 #define BIAS_BIAS1_OFFSET 0x0000003c |
| 1225 #define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 |
| 1226 #define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 |
| 1227 #define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 |
| 1228 #define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB
25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) |
| 1229 #define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2B
B25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) |
| 1230 #define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 |
| 1231 #define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 |
| 1232 #define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 |
| 1233 #define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM2
5_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) |
| 1234 #define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM
25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) |
| 1235 #define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 |
| 1236 #define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 |
| 1237 #define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 |
| 1238 #define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE
25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) |
| 1239 #define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFF
E25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) |
| 1240 #define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 |
| 1241 #define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 |
| 1242 #define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 |
| 1243 #define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLORE
G25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) |
| 1244 #define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOR
EG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) |
| 1245 #define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 |
| 1246 #define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 |
| 1247 #define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 |
| 1248 #define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAR
EG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) |
| 1249 #define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNA
REG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) |
| 1250 #define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 |
| 1251 #define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 |
| 1252 #define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 |
| 1253 #define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECT
ORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) |
| 1254 #define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETEC
TORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) |
| 1255 #define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 |
| 1256 #define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 |
| 1257 #define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 |
| 1258 #define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECT
ORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) |
| 1259 #define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETEC
TORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) |
| 1260 #define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 |
| 1261 #define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 |
| 1262 #define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 |
| 1263 #define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF
25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) |
| 1264 #define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXR
F25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) |
| 1265 #define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 |
| 1266 #define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 |
| 1267 #define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 |
| 1268 #define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA
25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) |
| 1269 #define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXP
A25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) |
| 1270 #define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 |
| 1271 #define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 |
| 1272 #define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 |
| 1273 #define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBU
F25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) |
| 1274 #define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXB
UF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) |
| 1275 #define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 |
| 1276 #define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 |
| 1277 #define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 |
| 1278 #define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25
_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) |
| 1279 #define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB2
5_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) |
| 1280 #define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 |
| 1281 #define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 |
| 1282 #define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c |
| 1283 #define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ
25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) |
| 1284 #define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIX
Q25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) |
| 1285 #define BIAS_BIAS1_SPARE_MSB 1 |
| 1286 #define BIAS_BIAS1_SPARE_LSB 0 |
| 1287 #define BIAS_BIAS1_SPARE_MASK 0x00000003 |
| 1288 #define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK)
>> BIAS_BIAS1_SPARE_LSB) |
| 1289 #define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB)
& BIAS_BIAS1_SPARE_MASK) |
| 1290 |
| 1291 #define BIAS_BIAS2_ADDRESS 0x00000040 |
| 1292 #define BIAS_BIAS2_OFFSET 0x00000040 |
| 1293 #define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 |
| 1294 #define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 |
| 1295 #define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 |
| 1296 #define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI
25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) |
| 1297 #define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIX
I25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) |
| 1298 #define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 |
| 1299 #define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 |
| 1300 #define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 |
| 1301 #define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV2
5_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) |
| 1302 #define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV
25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) |
| 1303 #define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 |
| 1304 #define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 |
| 1305 #define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 |
| 1306 #define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLORE
G25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) |
| 1307 #define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOR
EG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) |
| 1308 #define BIAS_BIAS2_PWD_IRPLL25_MSB 22 |
| 1309 #define BIAS_BIAS2_PWD_IRPLL25_LSB 22 |
| 1310 #define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 |
| 1311 #define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_
MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) |
| 1312 #define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25
_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) |
| 1313 #define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 |
| 1314 #define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 |
| 1315 #define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 |
| 1316 #define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25
_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) |
| 1317 #define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL2
5_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) |
| 1318 #define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 |
| 1319 #define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 |
| 1320 #define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 |
| 1321 #define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS2
5_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) |
| 1322 #define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS
25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) |
| 1323 #define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 |
| 1324 #define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 |
| 1325 #define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 |
| 1326 #define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25
_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) |
| 1327 #define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC2
5_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) |
| 1328 #define BIAS_BIAS2_PWD_IRLDO25_MSB 12 |
| 1329 #define BIAS_BIAS2_PWD_IRLDO25_LSB 12 |
| 1330 #define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 |
| 1331 #define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_
MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) |
| 1332 #define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25
_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) |
| 1333 #define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 |
| 1334 #define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 |
| 1335 #define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 |
| 1336 #define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMI
X25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) |
| 1337 #define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXM
IX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) |
| 1338 #define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 |
| 1339 #define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 |
| 1340 #define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 |
| 1341 #define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLORE
G25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) |
| 1342 #define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOR
EG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) |
| 1343 #define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 |
| 1344 #define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 |
| 1345 #define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 |
| 1346 #define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAR
EG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) |
| 1347 #define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNA
REG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) |
| 1348 #define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 |
| 1349 #define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 |
| 1350 #define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 |
| 1351 #define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVR
EF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) |
| 1352 #define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFV
REF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) |
| 1353 |
| 1354 #define BIAS_BIAS3_ADDRESS 0x00000044 |
| 1355 #define BIAS_BIAS3_OFFSET 0x00000044 |
| 1356 #define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 |
| 1357 #define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 |
| 1358 #define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 |
| 1359 #define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMI
X25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) |
| 1360 #define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXM
IX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) |
| 1361 #define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 |
| 1362 #define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 |
| 1363 #define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 |
| 1364 #define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC2
5_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) |
| 1365 #define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC
25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) |
| 1366 #define BIAS_BIAS3_PWD_ICDAC50_MSB 25 |
| 1367 #define BIAS_BIAS3_PWD_ICDAC50_LSB 23 |
| 1368 #define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 |
| 1369 #define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_
MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) |
| 1370 #define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50
_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) |
| 1371 #define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 |
| 1372 #define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 |
| 1373 #define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 |
| 1374 #define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH5
0_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) |
| 1375 #define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH
50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) |
| 1376 #define BIAS_BIAS3_PWD_ICBB50_MSB 21 |
| 1377 #define BIAS_BIAS3_PWD_ICBB50_LSB 21 |
| 1378 #define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 |
| 1379 #define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_M
ASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) |
| 1380 #define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_
LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) |
| 1381 #define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 |
| 1382 #define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 |
| 1383 #define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 |
| 1384 #define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV5
0_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) |
| 1385 #define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV
50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) |
| 1386 #define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 |
| 1387 #define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 |
| 1388 #define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 |
| 1389 #define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH5
0_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) |
| 1390 #define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH
50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) |
| 1391 #define BIAS_BIAS3_PWD_IRBB50_MSB 16 |
| 1392 #define BIAS_BIAS3_PWD_IRBB50_LSB 16 |
| 1393 #define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 |
| 1394 #define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_M
ASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) |
| 1395 #define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_
LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) |
| 1396 #define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 |
| 1397 #define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 |
| 1398 #define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 |
| 1399 #define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPAR
E1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) |
| 1400 #define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPA
RE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) |
| 1401 #define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 |
| 1402 #define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 |
| 1403 #define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 |
| 1404 #define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPAR
E2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) |
| 1405 #define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPA
RE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) |
| 1406 #define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 |
| 1407 #define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 |
| 1408 #define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 |
| 1409 #define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPAR
E1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) |
| 1410 #define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPA
RE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) |
| 1411 #define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 |
| 1412 #define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 |
| 1413 #define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 |
| 1414 #define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPAR
E2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) |
| 1415 #define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPA
RE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) |
| 1416 #define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 |
| 1417 #define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 |
| 1418 #define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e |
| 1419 #define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG
12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) |
| 1420 #define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACRE
G12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) |
| 1421 #define BIAS_BIAS3_SPARE_MSB 0 |
| 1422 #define BIAS_BIAS3_SPARE_LSB 0 |
| 1423 #define BIAS_BIAS3_SPARE_MASK 0x00000001 |
| 1424 #define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK)
>> BIAS_BIAS3_SPARE_LSB) |
| 1425 #define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB)
& BIAS_BIAS3_SPARE_MASK) |
| 1426 |
| 1427 #define TXPC_TXPC_ADDRESS 0x00000048 |
| 1428 #define TXPC_TXPC_OFFSET 0x00000048 |
| 1429 #define TXPC_TXPC_SELINTPD_MSB 31 |
| 1430 #define TXPC_TXPC_SELINTPD_LSB 31 |
| 1431 #define TXPC_TXPC_SELINTPD_MASK 0x80000000 |
| 1432 #define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK
) >> TXPC_TXPC_SELINTPD_LSB) |
| 1433 #define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB
) & TXPC_TXPC_SELINTPD_MASK) |
| 1434 #define TXPC_TXPC_TEST_MSB 30 |
| 1435 #define TXPC_TXPC_TEST_LSB 30 |
| 1436 #define TXPC_TXPC_TEST_MASK 0x40000000 |
| 1437 #define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >>
TXPC_TXPC_TEST_LSB) |
| 1438 #define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) &
TXPC_TXPC_TEST_MASK) |
| 1439 #define TXPC_TXPC_TESTGAIN_MSB 29 |
| 1440 #define TXPC_TXPC_TESTGAIN_LSB 28 |
| 1441 #define TXPC_TXPC_TESTGAIN_MASK 0x30000000 |
| 1442 #define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK
) >> TXPC_TXPC_TESTGAIN_LSB) |
| 1443 #define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB
) & TXPC_TXPC_TESTGAIN_MASK) |
| 1444 #define TXPC_TXPC_TESTDAC_MSB 27 |
| 1445 #define TXPC_TXPC_TESTDAC_LSB 22 |
| 1446 #define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 |
| 1447 #define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK)
>> TXPC_TXPC_TESTDAC_LSB) |
| 1448 #define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB)
& TXPC_TXPC_TESTDAC_MASK) |
| 1449 #define TXPC_TXPC_TESTPWDPC_MSB 21 |
| 1450 #define TXPC_TXPC_TESTPWDPC_LSB 21 |
| 1451 #define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 |
| 1452 #define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MAS
K) >> TXPC_TXPC_TESTPWDPC_LSB) |
| 1453 #define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LS
B) & TXPC_TXPC_TESTPWDPC_MASK) |
| 1454 #define TXPC_TXPC_CURHALF_MSB 20 |
| 1455 #define TXPC_TXPC_CURHALF_LSB 20 |
| 1456 #define TXPC_TXPC_CURHALF_MASK 0x00100000 |
| 1457 #define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK)
>> TXPC_TXPC_CURHALF_LSB) |
| 1458 #define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB)
& TXPC_TXPC_CURHALF_MASK) |
| 1459 #define TXPC_TXPC_NEGOUT_MSB 19 |
| 1460 #define TXPC_TXPC_NEGOUT_LSB 19 |
| 1461 #define TXPC_TXPC_NEGOUT_MASK 0x00080000 |
| 1462 #define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK)
>> TXPC_TXPC_NEGOUT_LSB) |
| 1463 #define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB)
& TXPC_TXPC_NEGOUT_MASK) |
| 1464 #define TXPC_TXPC_CLKDELAY_MSB 18 |
| 1465 #define TXPC_TXPC_CLKDELAY_LSB 18 |
| 1466 #define TXPC_TXPC_CLKDELAY_MASK 0x00040000 |
| 1467 #define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK
) >> TXPC_TXPC_CLKDELAY_LSB) |
| 1468 #define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB
) & TXPC_TXPC_CLKDELAY_MASK) |
| 1469 #define TXPC_TXPC_SELMODREF_MSB 17 |
| 1470 #define TXPC_TXPC_SELMODREF_LSB 17 |
| 1471 #define TXPC_TXPC_SELMODREF_MASK 0x00020000 |
| 1472 #define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MAS
K) >> TXPC_TXPC_SELMODREF_LSB) |
| 1473 #define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LS
B) & TXPC_TXPC_SELMODREF_MASK) |
| 1474 #define TXPC_TXPC_SELCMOUT_MSB 16 |
| 1475 #define TXPC_TXPC_SELCMOUT_LSB 16 |
| 1476 #define TXPC_TXPC_SELCMOUT_MASK 0x00010000 |
| 1477 #define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK
) >> TXPC_TXPC_SELCMOUT_LSB) |
| 1478 #define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB
) & TXPC_TXPC_SELCMOUT_MASK) |
| 1479 #define TXPC_TXPC_TSMODE_MSB 15 |
| 1480 #define TXPC_TXPC_TSMODE_LSB 14 |
| 1481 #define TXPC_TXPC_TSMODE_MASK 0x0000c000 |
| 1482 #define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK)
>> TXPC_TXPC_TSMODE_LSB) |
| 1483 #define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB)
& TXPC_TXPC_TSMODE_MASK) |
| 1484 #define TXPC_TXPC_N_MSB 13 |
| 1485 #define TXPC_TXPC_N_LSB 6 |
| 1486 #define TXPC_TXPC_N_MASK 0x00003fc0 |
| 1487 #define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TX
PC_TXPC_N_LSB) |
| 1488 #define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXP
C_TXPC_N_MASK) |
| 1489 #define TXPC_TXPC_ON1STSYNTHON_MSB 5 |
| 1490 #define TXPC_TXPC_ON1STSYNTHON_LSB 5 |
| 1491 #define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 |
| 1492 #define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_
MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) |
| 1493 #define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON
_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) |
| 1494 #define TXPC_TXPC_SELINIT_MSB 4 |
| 1495 #define TXPC_TXPC_SELINIT_LSB 3 |
| 1496 #define TXPC_TXPC_SELINIT_MASK 0x00000018 |
| 1497 #define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK)
>> TXPC_TXPC_SELINIT_LSB) |
| 1498 #define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB)
& TXPC_TXPC_SELINIT_MASK) |
| 1499 #define TXPC_TXPC_SELCOUNT_MSB 2 |
| 1500 #define TXPC_TXPC_SELCOUNT_LSB 2 |
| 1501 #define TXPC_TXPC_SELCOUNT_MASK 0x00000004 |
| 1502 #define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK
) >> TXPC_TXPC_SELCOUNT_LSB) |
| 1503 #define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB
) & TXPC_TXPC_SELCOUNT_MASK) |
| 1504 #define TXPC_TXPC_ATBSEL_MSB 1 |
| 1505 #define TXPC_TXPC_ATBSEL_LSB 0 |
| 1506 #define TXPC_TXPC_ATBSEL_MASK 0x00000003 |
| 1507 #define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK)
>> TXPC_TXPC_ATBSEL_LSB) |
| 1508 #define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB)
& TXPC_TXPC_ATBSEL_MASK) |
| 1509 |
| 1510 #define TXPC_MISC_ADDRESS 0x0000004c |
| 1511 #define TXPC_MISC_OFFSET 0x0000004c |
| 1512 #define TXPC_MISC_FLIPBMODE_MSB 31 |
| 1513 #define TXPC_MISC_FLIPBMODE_LSB 31 |
| 1514 #define TXPC_MISC_FLIPBMODE_MASK 0x80000000 |
| 1515 #define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MAS
K) >> TXPC_MISC_FLIPBMODE_LSB) |
| 1516 #define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LS
B) & TXPC_MISC_FLIPBMODE_MASK) |
| 1517 #define TXPC_MISC_LEVEL_MSB 30 |
| 1518 #define TXPC_MISC_LEVEL_LSB 29 |
| 1519 #define TXPC_MISC_LEVEL_MASK 0x60000000 |
| 1520 #define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >
> TXPC_MISC_LEVEL_LSB) |
| 1521 #define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) &
TXPC_MISC_LEVEL_MASK) |
| 1522 #define TXPC_MISC_LDO_TEST_MODE_MSB 28 |
| 1523 #define TXPC_MISC_LDO_TEST_MODE_LSB 28 |
| 1524 #define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 |
| 1525 #define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE
_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) |
| 1526 #define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MOD
E_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) |
| 1527 #define TXPC_MISC_NOTCXODET_MSB 27 |
| 1528 #define TXPC_MISC_NOTCXODET_LSB 27 |
| 1529 #define TXPC_MISC_NOTCXODET_MASK 0x08000000 |
| 1530 #define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MAS
K) >> TXPC_MISC_NOTCXODET_LSB) |
| 1531 #define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LS
B) & TXPC_MISC_NOTCXODET_MASK) |
| 1532 #define TXPC_MISC_PWDCLKIND_MSB 26 |
| 1533 #define TXPC_MISC_PWDCLKIND_LSB 26 |
| 1534 #define TXPC_MISC_PWDCLKIND_MASK 0x04000000 |
| 1535 #define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MAS
K) >> TXPC_MISC_PWDCLKIND_LSB) |
| 1536 #define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LS
B) & TXPC_MISC_PWDCLKIND_MASK) |
| 1537 #define TXPC_MISC_PWDXINPAD_MSB 25 |
| 1538 #define TXPC_MISC_PWDXINPAD_LSB 25 |
| 1539 #define TXPC_MISC_PWDXINPAD_MASK 0x02000000 |
| 1540 #define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MAS
K) >> TXPC_MISC_PWDXINPAD_LSB) |
| 1541 #define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LS
B) & TXPC_MISC_PWDXINPAD_MASK) |
| 1542 #define TXPC_MISC_LOCALBIAS_MSB 24 |
| 1543 #define TXPC_MISC_LOCALBIAS_LSB 24 |
| 1544 #define TXPC_MISC_LOCALBIAS_MASK 0x01000000 |
| 1545 #define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MAS
K) >> TXPC_MISC_LOCALBIAS_LSB) |
| 1546 #define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LS
B) & TXPC_MISC_LOCALBIAS_MASK) |
| 1547 #define TXPC_MISC_LOCALBIAS2X_MSB 23 |
| 1548 #define TXPC_MISC_LOCALBIAS2X_LSB 23 |
| 1549 #define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 |
| 1550 #define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_M
ASK) >> TXPC_MISC_LOCALBIAS2X_LSB) |
| 1551 #define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_
LSB) & TXPC_MISC_LOCALBIAS2X_MASK) |
| 1552 #define TXPC_MISC_SELTSP_MSB 22 |
| 1553 #define TXPC_MISC_SELTSP_LSB 22 |
| 1554 #define TXPC_MISC_SELTSP_MASK 0x00400000 |
| 1555 #define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK)
>> TXPC_MISC_SELTSP_LSB) |
| 1556 #define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB)
& TXPC_MISC_SELTSP_MASK) |
| 1557 #define TXPC_MISC_SELTSN_MSB 21 |
| 1558 #define TXPC_MISC_SELTSN_LSB 21 |
| 1559 #define TXPC_MISC_SELTSN_MASK 0x00200000 |
| 1560 #define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK)
>> TXPC_MISC_SELTSN_LSB) |
| 1561 #define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB)
& TXPC_MISC_SELTSN_MASK) |
| 1562 #define TXPC_MISC_SPARE_A_MSB 20 |
| 1563 #define TXPC_MISC_SPARE_A_LSB 18 |
| 1564 #define TXPC_MISC_SPARE_A_MASK 0x001c0000 |
| 1565 #define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK)
>> TXPC_MISC_SPARE_A_LSB) |
| 1566 #define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB)
& TXPC_MISC_SPARE_A_MASK) |
| 1567 #define TXPC_MISC_DECOUT_MSB 17 |
| 1568 #define TXPC_MISC_DECOUT_LSB 8 |
| 1569 #define TXPC_MISC_DECOUT_MASK 0x0003ff00 |
| 1570 #define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK)
>> TXPC_MISC_DECOUT_LSB) |
| 1571 #define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB)
& TXPC_MISC_DECOUT_MASK) |
| 1572 #define TXPC_MISC_XTALDIV_MSB 7 |
| 1573 #define TXPC_MISC_XTALDIV_LSB 6 |
| 1574 #define TXPC_MISC_XTALDIV_MASK 0x000000c0 |
| 1575 #define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK)
>> TXPC_MISC_XTALDIV_LSB) |
| 1576 #define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB)
& TXPC_MISC_XTALDIV_MASK) |
| 1577 #define TXPC_MISC_SPARE_MSB 5 |
| 1578 #define TXPC_MISC_SPARE_LSB 0 |
| 1579 #define TXPC_MISC_SPARE_MASK 0x0000003f |
| 1580 #define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >
> TXPC_MISC_SPARE_LSB) |
| 1581 #define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) &
TXPC_MISC_SPARE_MASK) |
| 1582 |
| 1583 #define RXTXBB_RXTXBB1_ADDRESS 0x00000050 |
| 1584 #define RXTXBB_RXTXBB1_OFFSET 0x00000050 |
| 1585 #define RXTXBB_RXTXBB1_SPARE_MSB 31 |
| 1586 #define RXTXBB_RXTXBB1_SPARE_LSB 19 |
| 1587 #define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 |
| 1588 #define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MA
SK) >> RXTXBB_RXTXBB1_SPARE_LSB) |
| 1589 #define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_L
SB) & RXTXBB_RXTXBB1_SPARE_MASK) |
| 1590 #define RXTXBB_RXTXBB1_FNOTCH_MSB 18 |
| 1591 #define RXTXBB_RXTXBB1_FNOTCH_LSB 17 |
| 1592 #define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 |
| 1593 #define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_M
ASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) |
| 1594 #define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_
LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) |
| 1595 #define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 |
| 1596 #define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 |
| 1597 #define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 |
| 1598 #define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_
MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) |
| 1599 #define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB
_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) |
| 1600 #define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 |
| 1601 #define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 |
| 1602 #define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 |
| 1603 #define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINT
ERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) |
| 1604 #define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACIN
TERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) |
| 1605 #define RXTXBB_RXTXBB1_PDV2I_MSB 7 |
| 1606 #define RXTXBB_RXTXBB1_PDV2I_LSB 7 |
| 1607 #define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 |
| 1608 #define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MA
SK) >> RXTXBB_RXTXBB1_PDV2I_LSB) |
| 1609 #define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_L
SB) & RXTXBB_RXTXBB1_PDV2I_MASK) |
| 1610 #define RXTXBB_RXTXBB1_PDI2V_MSB 6 |
| 1611 #define RXTXBB_RXTXBB1_PDI2V_LSB 6 |
| 1612 #define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 |
| 1613 #define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MA
SK) >> RXTXBB_RXTXBB1_PDI2V_LSB) |
| 1614 #define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_L
SB) & RXTXBB_RXTXBB1_PDI2V_MASK) |
| 1615 #define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 |
| 1616 #define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 |
| 1617 #define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 |
| 1618 #define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB
_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) |
| 1619 #define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXB
B_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) |
| 1620 #define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 |
| 1621 #define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 |
| 1622 #define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 |
| 1623 #define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSET
LOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) |
| 1624 #define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSE
TLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) |
| 1625 #define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 |
| 1626 #define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 |
| 1627 #define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 |
| 1628 #define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSET
HIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) |
| 1629 #define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSE
THIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) |
| 1630 #define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 |
| 1631 #define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 |
| 1632 #define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 |
| 1633 #define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSET
I2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) |
| 1634 #define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSE
TI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) |
| 1635 #define RXTXBB_RXTXBB1_PDLOQ_MSB 1 |
| 1636 #define RXTXBB_RXTXBB1_PDLOQ_LSB 1 |
| 1637 #define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 |
| 1638 #define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MA
SK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) |
| 1639 #define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_L
SB) & RXTXBB_RXTXBB1_PDLOQ_MASK) |
| 1640 #define RXTXBB_RXTXBB1_PDHIQ_MSB 0 |
| 1641 #define RXTXBB_RXTXBB1_PDHIQ_LSB 0 |
| 1642 #define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 |
| 1643 #define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MA
SK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) |
| 1644 #define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_L
SB) & RXTXBB_RXTXBB1_PDHIQ_MASK) |
| 1645 |
| 1646 #define RXTXBB_RXTXBB2_ADDRESS 0x00000054 |
| 1647 #define RXTXBB_RXTXBB2_OFFSET 0x00000054 |
| 1648 #define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 |
| 1649 #define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 |
| 1650 #define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 |
| 1651 #define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5
_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) |
| 1652 #define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P
5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) |
| 1653 #define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 |
| 1654 #define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 |
| 1655 #define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 |
| 1656 #define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5
_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) |
| 1657 #define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P
5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) |
| 1658 #define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 |
| 1659 #define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 |
| 1660 #define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 |
| 1661 #define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P
5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) |
| 1662 #define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37
P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) |
| 1663 #define RXTXBB_RXTXBB2_SPARE_MSB 22 |
| 1664 #define RXTXBB_RXTXBB2_SPARE_LSB 21 |
| 1665 #define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 |
| 1666 #define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MA
SK) >> RXTXBB_RXTXBB2_SPARE_LSB) |
| 1667 #define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_L
SB) & RXTXBB_RXTXBB2_SPARE_MASK) |
| 1668 #define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 |
| 1669 #define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 |
| 1670 #define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 |
| 1671 #define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUF
FER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) |
| 1672 #define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBU
FFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) |
| 1673 #define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 |
| 1674 #define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 |
| 1675 #define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 |
| 1676 #define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFE
R_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) |
| 1677 #define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFF
ER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) |
| 1678 #define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 |
| 1679 #define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 |
| 1680 #define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 |
| 1681 #define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_
TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) |
| 1682 #define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC
_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) |
| 1683 #define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 |
| 1684 #define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 |
| 1685 #define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 |
| 1686 #define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_
TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) |
| 1687 #define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ
_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) |
| 1688 #define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 |
| 1689 #define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 |
| 1690 #define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 |
| 1691 #define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_
TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) |
| 1692 #define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ
_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) |
| 1693 #define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 |
| 1694 #define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 |
| 1695 #define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 |
| 1696 #define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_
TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) |
| 1697 #define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V
_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) |
| 1698 #define RXTXBB_RXTXBB2_CMSEL_MSB 14 |
| 1699 #define RXTXBB_RXTXBB2_CMSEL_LSB 13 |
| 1700 #define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 |
| 1701 #define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MA
SK) >> RXTXBB_RXTXBB2_CMSEL_LSB) |
| 1702 #define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_L
SB) & RXTXBB_RXTXBB2_CMSEL_MASK) |
| 1703 #define RXTXBB_RXTXBB2_FILTERFC_MSB 12 |
| 1704 #define RXTXBB_RXTXBB2_FILTERFC_LSB 8 |
| 1705 #define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 |
| 1706 #define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC
_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) |
| 1707 #define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERF
C_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) |
| 1708 #define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 |
| 1709 #define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 |
| 1710 #define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 |
| 1711 #define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFIL
TERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) |
| 1712 #define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFI
LTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) |
| 1713 #define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 |
| 1714 #define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 |
| 1715 #define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 |
| 1716 #define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDO
UBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) |
| 1717 #define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERD
OUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) |
| 1718 #define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 |
| 1719 #define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 |
| 1720 #define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 |
| 1721 #define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ
_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) |
| 1722 #define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HI
Q_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) |
| 1723 #define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 |
| 1724 #define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 |
| 1725 #define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 |
| 1726 #define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ
_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) |
| 1727 #define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HI
Q_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) |
| 1728 #define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 |
| 1729 #define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 |
| 1730 #define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 |
| 1731 #define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ
_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) |
| 1732 #define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LO
Q_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) |
| 1733 #define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 |
| 1734 #define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 |
| 1735 #define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 |
| 1736 #define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ
_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) |
| 1737 #define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LO
Q_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) |
| 1738 #define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 |
| 1739 #define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 |
| 1740 #define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 |
| 1741 #define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ
_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) |
| 1742 #define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LO
Q_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) |
| 1743 #define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 |
| 1744 #define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 |
| 1745 #define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 |
| 1746 #define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVE
RRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) |
| 1747 #define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OV
ERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) |
| 1748 |
| 1749 #define RXTXBB_RXTXBB3_ADDRESS 0x00000058 |
| 1750 #define RXTXBB_RXTXBB3_OFFSET 0x00000058 |
| 1751 #define RXTXBB_RXTXBB3_SPARE_MSB 31 |
| 1752 #define RXTXBB_RXTXBB3_SPARE_LSB 27 |
| 1753 #define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 |
| 1754 #define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MA
SK) >> RXTXBB_RXTXBB3_SPARE_LSB) |
| 1755 #define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_L
SB) & RXTXBB_RXTXBB3_SPARE_MASK) |
| 1756 #define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 |
| 1757 #define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 |
| 1758 #define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 |
| 1759 #define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_
25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) |
| 1760 #define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN
_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) |
| 1761 #define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 |
| 1762 #define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 |
| 1763 #define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 |
| 1764 #define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) |
| 1765 #define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) |
| 1766 #define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 |
| 1767 #define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 |
| 1768 #define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 |
| 1769 #define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) |
| 1770 #define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) |
| 1771 #define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 |
| 1772 #define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 |
| 1773 #define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 |
| 1774 #define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) |
| 1775 #define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) |
| 1776 #define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 |
| 1777 #define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 |
| 1778 #define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 |
| 1779 #define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) |
| 1780 #define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) |
| 1781 #define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 |
| 1782 #define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 |
| 1783 #define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 |
| 1784 #define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) |
| 1785 #define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) |
| 1786 #define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 |
| 1787 #define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 |
| 1788 #define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 |
| 1789 #define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_
LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) |
| 1790 #define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U
_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) |
| 1791 #define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 |
| 1792 #define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 |
| 1793 #define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 |
| 1794 #define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P
5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) |
| 1795 #define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12
P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) |
| 1796 #define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 |
| 1797 #define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 |
| 1798 #define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 |
| 1799 #define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U
_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) |
| 1800 #define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100
U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) |
| 1801 |
| 1802 #define RXTXBB_RXTXBB4_ADDRESS 0x0000005c |
| 1803 #define RXTXBB_RXTXBB4_OFFSET 0x0000005c |
| 1804 #define RXTXBB_RXTXBB4_SPARE_MSB 31 |
| 1805 #define RXTXBB_RXTXBB4_SPARE_LSB 31 |
| 1806 #define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 |
| 1807 #define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MA
SK) >> RXTXBB_RXTXBB4_SPARE_LSB) |
| 1808 #define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_L
SB) & RXTXBB_RXTXBB4_SPARE_MASK) |
| 1809 #define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 |
| 1810 #define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 |
| 1811 #define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 |
| 1812 #define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFF
SET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) |
| 1813 #define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOF
FSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) |
| 1814 #define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 |
| 1815 #define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 |
| 1816 #define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 |
| 1817 #define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
HII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) |
| 1818 #define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) |
| 1819 #define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 |
| 1820 #define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 |
| 1821 #define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 |
| 1822 #define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
HIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) |
| 1823 #define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) |
| 1824 #define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 |
| 1825 #define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 |
| 1826 #define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 |
| 1827 #define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
LOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) |
| 1828 #define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) |
| 1829 #define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 |
| 1830 #define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 |
| 1831 #define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 |
| 1832 #define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
LOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) |
| 1833 #define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) |
| 1834 #define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 |
| 1835 #define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 |
| 1836 #define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 |
| 1837 #define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
I2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) |
| 1838 #define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) |
| 1839 #define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 |
| 1840 #define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 |
| 1841 #define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f |
| 1842 #define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORR
I2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) |
| 1843 #define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCOR
RI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) |
| 1844 |
| 1845 #define ADDAC_ADDAC1_ADDRESS 0x00000060 |
| 1846 #define ADDAC_ADDAC1_OFFSET 0x00000060 |
| 1847 #define ADDAC_ADDAC1_PLL_SVREG_MSB 31 |
| 1848 #define ADDAC_ADDAC1_PLL_SVREG_LSB 31 |
| 1849 #define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 |
| 1850 #define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_
MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) |
| 1851 #define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG
_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) |
| 1852 #define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 |
| 1853 #define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 |
| 1854 #define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 |
| 1855 #define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP
_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) |
| 1856 #define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAM
P_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) |
| 1857 #define ADDAC_ADDAC1_PLL_ATB_MSB 27 |
| 1858 #define ADDAC_ADDAC1_PLL_ATB_LSB 26 |
| 1859 #define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 |
| 1860 #define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MA
SK) >> ADDAC_ADDAC1_PLL_ATB_LSB) |
| 1861 #define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_L
SB) & ADDAC_ADDAC1_PLL_ATB_MASK) |
| 1862 #define ADDAC_ADDAC1_PLL_ICP_MSB 25 |
| 1863 #define ADDAC_ADDAC1_PLL_ICP_LSB 23 |
| 1864 #define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 |
| 1865 #define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MA
SK) >> ADDAC_ADDAC1_PLL_ICP_LSB) |
| 1866 #define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_L
SB) & ADDAC_ADDAC1_PLL_ICP_MASK) |
| 1867 #define ADDAC_ADDAC1_PLL_FILTER_MSB 22 |
| 1868 #define ADDAC_ADDAC1_PLL_FILTER_LSB 15 |
| 1869 #define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 |
| 1870 #define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER
_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) |
| 1871 #define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTE
R_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) |
| 1872 #define ADDAC_ADDAC1_PWDPLL_MSB 14 |
| 1873 #define ADDAC_ADDAC1_PWDPLL_LSB 14 |
| 1874 #define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 |
| 1875 #define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MAS
K) >> ADDAC_ADDAC1_PWDPLL_LSB) |
| 1876 #define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LS
B) & ADDAC_ADDAC1_PWDPLL_MASK) |
| 1877 #define ADDAC_ADDAC1_PWDADC_MSB 13 |
| 1878 #define ADDAC_ADDAC1_PWDADC_LSB 13 |
| 1879 #define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 |
| 1880 #define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MAS
K) >> ADDAC_ADDAC1_PWDADC_LSB) |
| 1881 #define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LS
B) & ADDAC_ADDAC1_PWDADC_MASK) |
| 1882 #define ADDAC_ADDAC1_PWDDAC_MSB 12 |
| 1883 #define ADDAC_ADDAC1_PWDDAC_LSB 12 |
| 1884 #define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 |
| 1885 #define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MAS
K) >> ADDAC_ADDAC1_PWDDAC_LSB) |
| 1886 #define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LS
B) & ADDAC_ADDAC1_PWDDAC_MASK) |
| 1887 #define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 |
| 1888 #define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 |
| 1889 #define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 |
| 1890 #define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLO
W_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) |
| 1891 #define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBL
OW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) |
| 1892 #define ADDAC_ADDAC1_SELMANPWDS_MSB 10 |
| 1893 #define ADDAC_ADDAC1_SELMANPWDS_LSB 10 |
| 1894 #define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 |
| 1895 #define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS
_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) |
| 1896 #define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWD
S_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) |
| 1897 #define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 |
| 1898 #define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 |
| 1899 #define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 |
| 1900 #define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160
_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) |
| 1901 #define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK16
0_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) |
| 1902 #define ADDAC_ADDAC1_CM_SEL_MSB 8 |
| 1903 #define ADDAC_ADDAC1_CM_SEL_LSB 7 |
| 1904 #define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 |
| 1905 #define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MAS
K) >> ADDAC_ADDAC1_CM_SEL_LSB) |
| 1906 #define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LS
B) & ADDAC_ADDAC1_CM_SEL_MASK) |
| 1907 #define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 |
| 1908 #define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 |
| 1909 #define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 |
| 1910 #define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DA
C_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) |
| 1911 #define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_D
AC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) |
| 1912 #define ADDAC_ADDAC1_SPARE_MSB 5 |
| 1913 #define ADDAC_ADDAC1_SPARE_LSB 0 |
| 1914 #define ADDAC_ADDAC1_SPARE_MASK 0x0000003f |
| 1915 #define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK
) >> ADDAC_ADDAC1_SPARE_LSB) |
| 1916 #define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB
) & ADDAC_ADDAC1_SPARE_MASK) |
| 1917 |
| 1918 |
| 1919 #ifndef __ASSEMBLER__ |
| 1920 |
| 1921 typedef struct analog_reg_reg_s { |
| 1922 volatile unsigned int synth_synth1; |
| 1923 volatile unsigned int synth_synth2; |
| 1924 volatile unsigned int synth_synth3; |
| 1925 volatile unsigned int synth_synth4; |
| 1926 volatile unsigned int synth_synth5; |
| 1927 volatile unsigned int synth_synth6; |
| 1928 volatile unsigned int synth_synth7; |
| 1929 volatile unsigned int synth_synth8; |
| 1930 volatile unsigned int rf5g_rf5g1; |
| 1931 volatile unsigned int rf5g_rf5g2; |
| 1932 volatile unsigned int rf2g_rf2g1; |
| 1933 volatile unsigned int rf2g_rf2g2; |
| 1934 volatile unsigned int top_gain; |
| 1935 volatile unsigned int top_top; |
| 1936 volatile unsigned int bias_bias_sel; |
| 1937 volatile unsigned int bias_bias1; |
| 1938 volatile unsigned int bias_bias2; |
| 1939 volatile unsigned int bias_bias3; |
| 1940 volatile unsigned int txpc_txpc; |
| 1941 volatile unsigned int txpc_misc; |
| 1942 volatile unsigned int rxtxbb_rxtxbb1; |
| 1943 volatile unsigned int rxtxbb_rxtxbb2; |
| 1944 volatile unsigned int rxtxbb_rxtxbb3; |
| 1945 volatile unsigned int rxtxbb_rxtxbb4; |
| 1946 volatile unsigned int addac_addac1; |
| 1947 } analog_reg_reg_t; |
| 1948 |
| 1949 #endif /* __ASSEMBLER__ */ |
| 1950 |
| 1951 #endif /* _ANALOG_REG_H_ */ |
OLD | NEW |