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Issue 645493002: [ia32] Better code generation for materialization of float/double constants. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE Created 6 years, 2 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/v8.h" 5 #include "src/v8.h"
6 6
7 #if V8_TARGET_ARCH_IA32 7 #if V8_TARGET_ARCH_IA32
8 8
9 #include "src/base/bits.h" 9 #include "src/base/bits.h"
10 #include "src/base/division-by-constant.h" 10 #include "src/base/division-by-constant.h"
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2609 mov(dst, x); 2609 mov(dst, x);
2610 } 2610 }
2611 } 2611 }
2612 2612
2613 2613
2614 void MacroAssembler::Move(const Operand& dst, const Immediate& x) { 2614 void MacroAssembler::Move(const Operand& dst, const Immediate& x) {
2615 mov(dst, x); 2615 mov(dst, x);
2616 } 2616 }
2617 2617
2618 2618
2619 void MacroAssembler::Move(XMMRegister dst, double val) { 2619 void MacroAssembler::Move(XMMRegister dst, uint32_t src) {
2620 // TODO(titzer): recognize double constants with ExternalReferences. 2620 if (src == 0) {
2621 uint64_t int_val = bit_cast<uint64_t, double>(val); 2621 pxor(dst, dst);
2622 if (int_val == 0) {
2623 xorps(dst, dst);
2624 } else { 2622 } else {
2625 int32_t lower = static_cast<int32_t>(int_val); 2623 unsigned cnt = base::bits::CountPopulation32(src);
2626 int32_t upper = static_cast<int32_t>(int_val >> kBitsPerInt); 2624 unsigned nlz = base::bits::CountLeadingZeros32(src);
2627 push(Immediate(upper)); 2625 unsigned ntz = base::bits::CountTrailingZeros32(src);
2628 push(Immediate(lower)); 2626 if (nlz + cnt + ntz == 32) {
2629 movsd(dst, Operand(esp, 0)); 2627 pcmpeqd(dst, dst);
2630 add(esp, Immediate(kDoubleSize)); 2628 if (ntz == 0) {
2629 psrld(dst, 32 - cnt);
2630 } else {
2631 pslld(dst, 32 - cnt);
2632 if (nlz != 0) psrld(dst, nlz);
2633 }
2634 } else {
2635 push(eax);
2636 mov(eax, Immediate(src));
2637 movd(dst, Operand(eax));
2638 pop(eax);
2639 }
2631 } 2640 }
2632 } 2641 }
2633 2642
2643
2644 void MacroAssembler::Move(XMMRegister dst, uint64_t src) {
2645 uint32_t lower = static_cast<uint32_t>(src);
2646 uint32_t upper = static_cast<uint32_t>(src >> 32);
2647 if (upper == 0) {
2648 Move(dst, lower);
2649 } else {
2650 unsigned cnt = base::bits::CountPopulation64(src);
2651 unsigned nlz = base::bits::CountLeadingZeros64(src);
2652 unsigned ntz = base::bits::CountTrailingZeros64(src);
2653 if (nlz + cnt + ntz == 64) {
2654 pcmpeqd(dst, dst);
2655 if (ntz == 0) {
2656 psrlq(dst, 64 - cnt);
2657 } else {
2658 psllq(dst, 64 - cnt);
2659 if (nlz != 0) psrlq(dst, nlz);
2660 }
2661 } else if (lower == 0) {
2662 Move(dst, upper);
2663 psllq(dst, 32);
2664 } else {
2665 push(eax);
2666 Move(eax, Immediate(lower));
2667 movd(dst, Operand(eax));
2668 Move(eax, Immediate(upper));
2669 if (CpuFeatures::IsSupported(SSE4_1)) {
2670 CpuFeatureScope scope(this, SSE4_1);
2671 pinsrd(dst, Operand(eax), 1);
2672 } else {
2673 psllq(dst, 32);
2674 movd(xmm0, Operand(eax));
2675 orpd(dst, xmm0);
2676 }
2677 pop(eax);
2678 }
2679 }
2680 }
2681
2634 2682
2635 void MacroAssembler::SetCounter(StatsCounter* counter, int value) { 2683 void MacroAssembler::SetCounter(StatsCounter* counter, int value) {
2636 if (FLAG_native_code_counters && counter->Enabled()) { 2684 if (FLAG_native_code_counters && counter->Enabled()) {
2637 mov(Operand::StaticVariable(ExternalReference(counter)), Immediate(value)); 2685 mov(Operand::StaticVariable(ExternalReference(counter)), Immediate(value));
2638 } 2686 }
2639 } 2687 }
2640 2688
2641 2689
2642 void MacroAssembler::IncrementCounter(StatsCounter* counter, int value) { 2690 void MacroAssembler::IncrementCounter(StatsCounter* counter, int value) {
2643 DCHECK(value > 0); 2691 DCHECK(value > 0);
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3391 if (mag.shift > 0) sar(edx, mag.shift); 3439 if (mag.shift > 0) sar(edx, mag.shift);
3392 mov(eax, dividend); 3440 mov(eax, dividend);
3393 shr(eax, 31); 3441 shr(eax, 31);
3394 add(edx, eax); 3442 add(edx, eax);
3395 } 3443 }
3396 3444
3397 3445
3398 } } // namespace v8::internal 3446 } } // namespace v8::internal
3399 3447
3400 #endif // V8_TARGET_ARCH_IA32 3448 #endif // V8_TARGET_ARCH_IA32
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