Subzero: Do class definition cleanups for assembler files too.

src/assembler_ia32.h

+//===- subzero/src/assembler_ia32.h - Assembler for x86-32 ------*- C++ -*-===//
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
-//===- subzero/src/assembler_ia32.h - Assembler for x86-32 ----------------===//
+//===----------------------------------------------------------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the Assembler class for x86-32.
 //
@@ skipping 20 matching lines @@
 using RegX8632::ByteRegister;
 using RegX8632::X87STRegister;
 
 namespace x86 {
 
 const int MAX_NOP_SIZE = 8;
 
 enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
 
 class DisplacementRelocation : public AssemblerFixup {
+  DisplacementRelocation(const DisplacementRelocation &) = delete;
+  DisplacementRelocation &operator=(const DisplacementRelocation &) = delete;
+
 public:
   static DisplacementRelocation *create(Assembler *Asm, FixupKind Kind,
                                         const ConstantRelocatable *Sym) {
     return new (Asm->Allocate<DisplacementRelocation>())
         DisplacementRelocation(Kind, Sym);
   }
 
   void Process(const MemoryRegion &region, intptr_t position) override {
     (void)region;
     (void)position;
     llvm_unreachable("We might not be using this Process() method later.");
   }
 
 private:
   DisplacementRelocation(FixupKind Kind, const ConstantRelocatable *Sym)
       : AssemblerFixup(Kind, Sym) {}
-  DisplacementRelocation(const DisplacementRelocation &) = delete;
-  DisplacementRelocation &operator=(const DisplacementRelocation &) = delete;
 };
 
 class Immediate {
+  Immediate(const Immediate &) = delete;
+  Immediate &operator=(const Immediate &) = delete;
+
 public:
   explicit Immediate(int32_t value) : value_(value), fixup_(NULL) {}
 
-  explicit Immediate(const Immediate &other)
-      : value_(other.value_), fixup_(other.fixup_) {}
-
   explicit Immediate(AssemblerFixup *fixup)
       : value_(fixup->value()->getOffset()), fixup_(fixup) {
     // Use the Offset in the "value" for now. If the symbol is part of
     // ".bss", then the relocation's symbol will be plain ".bss" and
     // the value will need to be adjusted further to be sym's
     // bss offset + Offset.
   }
 
   int32_t value() const { return value_; }
   AssemblerFixup *fixup() const { return fixup_; }
 
   bool is_int8() const {
     // We currently only allow 32-bit fixups, and they usually have value = 0,
     // so if fixup_ != NULL, it shouldn't be classified as int8/16.
     return fixup_ == NULL && Utils::IsInt(8, value_);
   }
   bool is_uint8() const { return fixup_ == NULL && Utils::IsUint(8, value_); }
   bool is_uint16() const { return fixup_ == NULL && Utils::IsUint(16, value_); }
 
 private:
   const int32_t value_;
   AssemblerFixup *fixup_;
 };
 
 class Operand {
 public:
+  Operand(const Operand &other) : length_(other.length_), fixup_(other.fixup_) {
+    memmove(&encoding_[0], &other.encoding_[0], other.length_);
+  }
+
+  Operand &operator=(const Operand &other) {
+    length_ = other.length_;
+    fixup_ = other.fixup_;
+    memmove(&encoding_[0], &other.encoding_[0], other.length_);
+    return *this;
+  }
+
   uint8_t mod() const { return (encoding_at(0) >> 6) & 3; }
 
   GPRRegister rm() const {
     return static_cast<GPRRegister>(encoding_at(0) & 7);
   }
 
   ScaleFactor scale() const {
     return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
   }
 
@@ skipping 10 matching lines @@
     return static_cast<int8_t>(encoding_[length_ - 1]);
   }
 
   int32_t disp32() const {
     assert(length_ >= 5);
     return bit_copy<int32_t>(encoding_[length_ - 4]);
   }
 
   AssemblerFixup *fixup() const { return fixup_; }
 
-  Operand(const Operand &other) : length_(other.length_), fixup_(other.fixup_) {
-    memmove(&encoding_[0], &other.encoding_[0], other.length_);
-  }
-
-  Operand &operator=(const Operand &other) {
-    length_ = other.length_;
-    fixup_ = other.fixup_;
-    memmove(&encoding_[0], &other.encoding_[0], other.length_);
-    return *this;
-  }
-
 protected:
   Operand() : length_(0), fixup_(NULL) {} // Needed by subclass Address.
 
   void SetModRM(int mod, GPRRegister rm) {
     assert((mod & ~3) == 0);
     encoding_[0] = (mod << 6) | rm;
     length_ = 1;
   }
 
   void SetSIB(ScaleFactor scale, GPRRegister index, GPRRegister base) {
@@ skipping 35 matching lines @@
   bool IsRegister(GPRRegister reg) const {
     return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
            && ((encoding_[0] & 0x07) == reg); // Register codes match.
   }
 
   friend class AssemblerX86;
 };
 
 class Address : public Operand {
 public:
+  Address(const Address &other) : Operand(other) {}
+
+  Address &operator=(const Address &other) {
+    Operand::operator=(other);
+    return *this;
+  }
+
   Address(GPRRegister base, int32_t disp) {
     if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) {
       SetModRM(0, base);
       if (base == RegX8632::Encoded_Reg_esp)
         SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
     } else if (Utils::IsInt(8, disp)) {
       SetModRM(1, base);
       if (base == RegX8632::Encoded_Reg_esp)
         SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
       SetDisp8(disp);
@@ skipping 22 matching lines @@
       SetModRM(1, RegX8632::Encoded_Reg_esp);
       SetSIB(scale, index, base);
       SetDisp8(disp);
     } else {
       SetModRM(2, RegX8632::Encoded_Reg_esp);
       SetSIB(scale, index, base);
       SetDisp32(disp);
     }
   }
 
-  Address(const Address &other) : Operand(other) {}
-
-  Address &operator=(const Address &other) {
-    Operand::operator=(other);
-    return *this;
-  }
-
   static Address Absolute(const uintptr_t addr) {
     Address result;
     result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
     result.SetDisp32(addr);
     return result;
   }
 
   static Address Absolute(AssemblerFixup *fixup) {
     Address result;
     result.SetModRM(0, RegX8632::Encoded_Reg_ebp);
     // Use the Offset in the displacement for now. If the symbol is part of
     // ".bss", then the relocation's symbol will be plain .bss and the
     // displacement will need to be adjusted further to be sym's
     // bss offset + Offset.
     result.SetDisp32(fixup->value()->getOffset());
     result.SetFixup(fixup);
     return result;
   }
 
   static Address ofConstPool(GlobalContext *Ctx, Assembler *Asm,
                              const Constant *Imm);
 
 private:
   Address() {} // Needed by Address::Absolute.
 };
 
 class Label {
+  Label(const Label &) = delete;
+  Label &operator=(const Label &) = delete;
+
 public:
   Label() : position_(0), num_unresolved_(0) {
-#ifdef DEBUG
+#ifndef NDEBUG
     for (int i = 0; i < kMaxUnresolvedBranches; i++) {
       unresolved_near_positions_[i] = -1;
     }
-#endif // DEBUG
+#endif // !NDEBUG
   }
 
   ~Label() {
     // Assert if label is being destroyed with unresolved branches pending.
     assert(!IsLinked());
     assert(!HasNear());
   }
 
   // TODO(jvoung): why are labels offset by this?
   static const uint32_t kWordSize = sizeof(uint32_t);
@@ skipping 49 matching lines @@
     unresolved_near_positions_[num_unresolved_++] = position;
   }
 
   static const int kMaxUnresolvedBranches = 20;
 
   intptr_t position_;
   intptr_t num_unresolved_;
   intptr_t unresolved_near_positions_[kMaxUnresolvedBranches];
 
   friend class AssemblerX86;
-  Label(const Label &) = delete;
-  Label &operator=(const Label &) = delete;
 };
 
 class AssemblerX86 : public Assembler {
+  AssemblerX86(const AssemblerX86 &) = delete;
+  AssemblerX86 &operator=(const AssemblerX86 &) = delete;
+
 public:
   explicit AssemblerX86(bool use_far_branches = false) : buffer_(*this) {
     // This mode is only needed and implemented for MIPS and ARM.
     assert(!use_far_branches);
     (void)use_far_branches;
   }
   ~AssemblerX86() {}
 
   static const bool kNearJump = true;
   static const bool kFarJump = false;
@@ skipping 429 matching lines @@
   void cmpxchg(Type Ty, const Address &address, GPRRegister reg);
   void cmpxchg8b(const Address &address);
   void xadd(Type Ty, const Address &address, GPRRegister reg);
   void xchg(Type Ty, const Address &address, GPRRegister reg);
 
   void LockCmpxchg(Type Ty, const Address &address, GPRRegister reg) {
     lock();
     cmpxchg(Ty, address, reg);
   }
 
-  void EmitSegmentOverride(uint8_t prefix) { EmitUint8(prefix); }
+  void EmitSegmentOverride(uint8_t prefix);
 
   intptr_t PreferredLoopAlignment() { return 16; }
   void Align(intptr_t alignment, intptr_t offset);
   void Bind(Label *label);
 
   intptr_t CodeSize() const { return buffer_.Size(); }
 
   void FinalizeInstructions(const MemoryRegion &region) {
     buffer_.FinalizeInstructions(region);
   }
@@ skipping 22 matching lines @@
                    const Immediate &immediate);
   void EmitLabel(Label *label, intptr_t instruction_size);
   void EmitLabelLink(Label *label);
   void EmitNearLabelLink(Label *label);
 
   void EmitGenericShift(int rm, Type Ty, GPRRegister reg, const Immediate &imm);
   void EmitGenericShift(int rm, Type Ty, const Operand &operand,
                         GPRRegister shifter);
 
   AssemblerBuffer buffer_;
-
-  AssemblerX86(const AssemblerX86 &) = delete;
-  AssemblerX86 &operator=(const AssemblerX86 &) = delete;
 };
 
 inline void AssemblerX86::EmitUint8(uint8_t value) {
   buffer_.Emit<uint8_t>(value);
 }
 
 inline void AssemblerX86::EmitInt16(int16_t value) {
   buffer_.Emit<int16_t>(value);
 }
 
@@ skipping 13 matching lines @@
 inline void AssemblerX86::EmitFixup(AssemblerFixup *fixup) {
   buffer_.EmitFixup(fixup);
 }
 
 inline void AssemblerX86::EmitOperandSizeOverride() { EmitUint8(0x66); }
 
 } // end of namespace x86
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ASSEMBLER_IA32_H_