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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 | 6 |
7 #include "src/arm64/macro-assembler-arm64.h" | 7 #include "src/arm64/macro-assembler-arm64.h" |
8 #include "src/compiler/code-generator-impl.h" | 8 #include "src/compiler/code-generator-impl.h" |
9 #include "src/compiler/gap-resolver.h" | 9 #include "src/compiler/gap-resolver.h" |
10 #include "src/compiler/node-matchers.h" | 10 #include "src/compiler/node-matchers.h" |
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39 Operand InputOperand64(int index) { return InputOperand(index); } | 39 Operand InputOperand64(int index) { return InputOperand(index); } |
40 | 40 |
41 Operand InputOperand32(int index) { | 41 Operand InputOperand32(int index) { |
42 return ToOperand32(instr_->InputAt(index)); | 42 return ToOperand32(instr_->InputAt(index)); |
43 } | 43 } |
44 | 44 |
45 Register OutputRegister64() { return OutputRegister(); } | 45 Register OutputRegister64() { return OutputRegister(); } |
46 | 46 |
47 Register OutputRegister32() { return ToRegister(instr_->Output()).W(); } | 47 Register OutputRegister32() { return ToRegister(instr_->Output()).W(); } |
48 | 48 |
| 49 Operand InputOperand2_32(int index) { |
| 50 switch (AddressingModeField::decode(instr_->opcode())) { |
| 51 case kMode_None: |
| 52 return InputOperand32(index); |
| 53 case kMode_Operand2_R_LSL_I: |
| 54 return Operand(InputRegister32(index), LSL, InputInt5(index + 1)); |
| 55 case kMode_Operand2_R_LSR_I: |
| 56 return Operand(InputRegister32(index), LSR, InputInt5(index + 1)); |
| 57 case kMode_Operand2_R_ASR_I: |
| 58 return Operand(InputRegister32(index), ASR, InputInt5(index + 1)); |
| 59 case kMode_Operand2_R_ROR_I: |
| 60 return Operand(InputRegister32(index), ROR, InputInt5(index + 1)); |
| 61 case kMode_MRI: |
| 62 case kMode_MRR: |
| 63 break; |
| 64 } |
| 65 UNREACHABLE(); |
| 66 return Operand(-1); |
| 67 } |
| 68 |
| 69 Operand InputOperand2_64(int index) { |
| 70 switch (AddressingModeField::decode(instr_->opcode())) { |
| 71 case kMode_None: |
| 72 return InputOperand64(index); |
| 73 case kMode_Operand2_R_LSL_I: |
| 74 return Operand(InputRegister64(index), LSL, InputInt6(index + 1)); |
| 75 case kMode_Operand2_R_LSR_I: |
| 76 return Operand(InputRegister64(index), LSR, InputInt6(index + 1)); |
| 77 case kMode_Operand2_R_ASR_I: |
| 78 return Operand(InputRegister64(index), ASR, InputInt6(index + 1)); |
| 79 case kMode_Operand2_R_ROR_I: |
| 80 return Operand(InputRegister64(index), ROR, InputInt6(index + 1)); |
| 81 case kMode_MRI: |
| 82 case kMode_MRR: |
| 83 break; |
| 84 } |
| 85 UNREACHABLE(); |
| 86 return Operand(-1); |
| 87 } |
| 88 |
49 MemOperand MemoryOperand(int* first_index) { | 89 MemOperand MemoryOperand(int* first_index) { |
50 const int index = *first_index; | 90 const int index = *first_index; |
51 switch (AddressingModeField::decode(instr_->opcode())) { | 91 switch (AddressingModeField::decode(instr_->opcode())) { |
52 case kMode_None: | 92 case kMode_None: |
| 93 case kMode_Operand2_R_LSL_I: |
| 94 case kMode_Operand2_R_LSR_I: |
| 95 case kMode_Operand2_R_ASR_I: |
| 96 case kMode_Operand2_R_ROR_I: |
53 break; | 97 break; |
54 case kMode_MRI: | 98 case kMode_MRI: |
55 *first_index += 2; | 99 *first_index += 2; |
56 return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); | 100 return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); |
57 case kMode_MRR: | 101 case kMode_MRR: |
58 *first_index += 2; | 102 *first_index += 2; |
59 return MemOperand(InputRegister(index + 0), InputRegister(index + 1), | 103 return MemOperand(InputRegister(index + 0), InputRegister(index + 1), |
60 SXTW); | 104 SXTW); |
61 } | 105 } |
62 UNREACHABLE(); | 106 UNREACHABLE(); |
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172 case kArchRet: | 216 case kArchRet: |
173 AssembleReturn(); | 217 AssembleReturn(); |
174 break; | 218 break; |
175 case kArchStackPointer: | 219 case kArchStackPointer: |
176 __ mov(i.OutputRegister(), masm()->StackPointer()); | 220 __ mov(i.OutputRegister(), masm()->StackPointer()); |
177 break; | 221 break; |
178 case kArchTruncateDoubleToI: | 222 case kArchTruncateDoubleToI: |
179 __ TruncateDoubleToI(i.OutputRegister(), i.InputDoubleRegister(0)); | 223 __ TruncateDoubleToI(i.OutputRegister(), i.InputDoubleRegister(0)); |
180 break; | 224 break; |
181 case kArm64Add: | 225 case kArm64Add: |
182 __ Add(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 226 __ Add(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
183 break; | 227 break; |
184 case kArm64Add32: | 228 case kArm64Add32: |
185 if (FlagsModeField::decode(opcode) != kFlags_none) { | 229 if (FlagsModeField::decode(opcode) != kFlags_none) { |
186 __ Adds(i.OutputRegister32(), i.InputRegister32(0), | 230 __ Adds(i.OutputRegister32(), i.InputRegister32(0), |
187 i.InputOperand32(1)); | 231 i.InputOperand2_32(1)); |
188 } else { | 232 } else { |
189 __ Add(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 233 __ Add(i.OutputRegister32(), i.InputRegister32(0), |
| 234 i.InputOperand2_32(1)); |
190 } | 235 } |
191 break; | 236 break; |
192 case kArm64And: | 237 case kArm64And: |
193 __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 238 __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
194 break; | 239 break; |
195 case kArm64And32: | 240 case kArm64And32: |
196 __ And(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 241 __ And(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
197 break; | 242 break; |
198 case kArm64Bic: | 243 case kArm64Bic: |
199 __ Bic(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 244 __ Bic(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
200 break; | 245 break; |
201 case kArm64Bic32: | 246 case kArm64Bic32: |
202 __ Bic(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 247 __ Bic(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
203 break; | 248 break; |
204 case kArm64Mul: | 249 case kArm64Mul: |
205 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); | 250 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); |
206 break; | 251 break; |
207 case kArm64Mul32: | 252 case kArm64Mul32: |
208 __ Mul(i.OutputRegister32(), i.InputRegister32(0), i.InputRegister32(1)); | 253 __ Mul(i.OutputRegister32(), i.InputRegister32(0), i.InputRegister32(1)); |
209 break; | 254 break; |
210 case kArm64Madd: | 255 case kArm64Madd: |
211 __ Madd(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), | 256 __ Madd(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), |
212 i.InputRegister(2)); | 257 i.InputRegister(2)); |
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278 case kArm64Not32: | 323 case kArm64Not32: |
279 __ Orn(i.OutputRegister32(), wzr, i.InputOperand32(0)); | 324 __ Orn(i.OutputRegister32(), wzr, i.InputOperand32(0)); |
280 break; | 325 break; |
281 case kArm64Neg: | 326 case kArm64Neg: |
282 __ Neg(i.OutputRegister(), i.InputOperand(0)); | 327 __ Neg(i.OutputRegister(), i.InputOperand(0)); |
283 break; | 328 break; |
284 case kArm64Neg32: | 329 case kArm64Neg32: |
285 __ Neg(i.OutputRegister32(), i.InputOperand32(0)); | 330 __ Neg(i.OutputRegister32(), i.InputOperand32(0)); |
286 break; | 331 break; |
287 case kArm64Or: | 332 case kArm64Or: |
288 __ Orr(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 333 __ Orr(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
289 break; | 334 break; |
290 case kArm64Or32: | 335 case kArm64Or32: |
291 __ Orr(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 336 __ Orr(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
292 break; | 337 break; |
293 case kArm64Orn: | 338 case kArm64Orn: |
294 __ Orn(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 339 __ Orn(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
295 break; | 340 break; |
296 case kArm64Orn32: | 341 case kArm64Orn32: |
297 __ Orn(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 342 __ Orn(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
298 break; | 343 break; |
299 case kArm64Eor: | 344 case kArm64Eor: |
300 __ Eor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 345 __ Eor(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
301 break; | 346 break; |
302 case kArm64Eor32: | 347 case kArm64Eor32: |
303 __ Eor(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 348 __ Eor(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
304 break; | 349 break; |
305 case kArm64Eon: | 350 case kArm64Eon: |
306 __ Eon(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 351 __ Eon(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
307 break; | 352 break; |
308 case kArm64Eon32: | 353 case kArm64Eon32: |
309 __ Eon(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 354 __ Eon(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1)); |
310 break; | 355 break; |
311 case kArm64Sub: | 356 case kArm64Sub: |
312 __ Sub(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 357 __ Sub(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1)); |
313 break; | 358 break; |
314 case kArm64Sub32: | 359 case kArm64Sub32: |
315 if (FlagsModeField::decode(opcode) != kFlags_none) { | 360 if (FlagsModeField::decode(opcode) != kFlags_none) { |
316 __ Subs(i.OutputRegister32(), i.InputRegister32(0), | 361 __ Subs(i.OutputRegister32(), i.InputRegister32(0), |
317 i.InputOperand32(1)); | 362 i.InputOperand2_32(1)); |
318 } else { | 363 } else { |
319 __ Sub(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1)); | 364 __ Sub(i.OutputRegister32(), i.InputRegister32(0), |
| 365 i.InputOperand2_32(1)); |
320 } | 366 } |
321 break; | 367 break; |
322 case kArm64Lsl: | 368 case kArm64Lsl: |
323 ASSEMBLE_SHIFT(Lsl, 64); | 369 ASSEMBLE_SHIFT(Lsl, 64); |
324 break; | 370 break; |
325 case kArm64Lsl32: | 371 case kArm64Lsl32: |
326 ASSEMBLE_SHIFT(Lsl, 32); | 372 ASSEMBLE_SHIFT(Lsl, 32); |
327 break; | 373 break; |
328 case kArm64Lsr: | 374 case kArm64Lsr: |
329 ASSEMBLE_SHIFT(Lsr, 64); | 375 ASSEMBLE_SHIFT(Lsr, 64); |
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935 } | 981 } |
936 } | 982 } |
937 MarkLazyDeoptSite(); | 983 MarkLazyDeoptSite(); |
938 } | 984 } |
939 | 985 |
940 #undef __ | 986 #undef __ |
941 | 987 |
942 } // namespace compiler | 988 } // namespace compiler |
943 } // namespace internal | 989 } // namespace internal |
944 } // namespace v8 | 990 } // namespace v8 |
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