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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 640603002: emitIAS for cvtt?.*2.* (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: move check Created 6 years, 2 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
(...skipping 2040 matching lines...) Expand 10 before | Expand all | Expand 10 after
2051 _and(T, Ctx->getConstantInt32(IceType_i1, 1)); 2051 _and(T, Ctx->getConstantInt32(IceType_i1, 1));
2052 _mov(Dest, T); 2052 _mov(Dest, T);
2053 } 2053 }
2054 break; 2054 break;
2055 } 2055 }
2056 case InstCast::Fptrunc: 2056 case InstCast::Fptrunc:
2057 case InstCast::Fpext: { 2057 case InstCast::Fpext: {
2058 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2058 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2059 // t1 = cvt Src0RM; Dest = t1 2059 // t1 = cvt Src0RM; Dest = t1
2060 Variable *T = makeReg(Dest->getType()); 2060 Variable *T = makeReg(Dest->getType());
2061 _cvt(T, Src0RM); 2061 _cvt(T, Src0RM, InstX8632Cvt::Float2float);
2062 _mov(Dest, T); 2062 _mov(Dest, T);
2063 break; 2063 break;
2064 } 2064 }
2065 case InstCast::Fptosi: 2065 case InstCast::Fptosi:
2066 if (isVectorType(Dest->getType())) { 2066 if (isVectorType(Dest->getType())) {
2067 assert(Dest->getType() == IceType_v4i32 && 2067 assert(Dest->getType() == IceType_v4i32 &&
2068 Inst->getSrc(0)->getType() == IceType_v4f32); 2068 Inst->getSrc(0)->getType() == IceType_v4f32);
2069 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2069 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2070 Variable *T = makeReg(Dest->getType()); 2070 Variable *T = makeReg(Dest->getType());
2071 _cvtt(T, Src0RM); 2071 _cvt(T, Src0RM, InstX8632Cvt::Tps2dq);
2072 _movp(Dest, T); 2072 _movp(Dest, T);
2073 } else if (Dest->getType() == IceType_i64) { 2073 } else if (Dest->getType() == IceType_i64) {
2074 // Use a helper for converting floating-point values to 64-bit 2074 // Use a helper for converting floating-point values to 64-bit
2075 // integers. SSE2 appears to have no way to convert from xmm 2075 // integers. SSE2 appears to have no way to convert from xmm
2076 // registers to something like the edx:eax register pair, and 2076 // registers to something like the edx:eax register pair, and
2077 // gcc and clang both want to use x87 instructions complete with 2077 // gcc and clang both want to use x87 instructions complete with
2078 // temporary manipulation of the status word. This helper is 2078 // temporary manipulation of the status word. This helper is
2079 // not needed for x86-64. 2079 // not needed for x86-64.
2080 split64(Dest); 2080 split64(Dest);
2081 const SizeT MaxSrcs = 1; 2081 const SizeT MaxSrcs = 1;
2082 Type SrcType = Inst->getSrc(0)->getType(); 2082 Type SrcType = Inst->getSrc(0)->getType();
2083 InstCall *Call = makeHelperCall( 2083 InstCall *Call = makeHelperCall(
2084 isFloat32Asserting32Or64(SrcType) ? "cvtftosi64" : "cvtdtosi64", Dest, 2084 isFloat32Asserting32Or64(SrcType) ? "cvtftosi64" : "cvtdtosi64", Dest,
2085 MaxSrcs); 2085 MaxSrcs);
2086 // TODO: Call the correct compiler-rt helper function. 2086 // TODO: Call the correct compiler-rt helper function.
2087 Call->addArg(Inst->getSrc(0)); 2087 Call->addArg(Inst->getSrc(0));
2088 lowerCall(Call); 2088 lowerCall(Call);
2089 } else { 2089 } else {
2090 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2090 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2091 // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type 2091 // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
2092 Variable *T_1 = makeReg(IceType_i32); 2092 Variable *T_1 = makeReg(IceType_i32);
2093 Variable *T_2 = makeReg(Dest->getType()); 2093 Variable *T_2 = makeReg(Dest->getType());
2094 _cvtt(T_1, Src0RM); 2094 _cvt(T_1, Src0RM, InstX8632Cvt::Tss2si);
2095 _mov(T_2, T_1); // T_1 and T_2 may have different integer types 2095 _mov(T_2, T_1); // T_1 and T_2 may have different integer types
2096 if (Dest->getType() == IceType_i1) 2096 if (Dest->getType() == IceType_i1)
2097 _and(T_2, Ctx->getConstantInt32(IceType_i1, 1)); 2097 _and(T_2, Ctx->getConstantInt32(IceType_i1, 1));
2098 _mov(Dest, T_2); 2098 _mov(Dest, T_2);
2099 } 2099 }
2100 break; 2100 break;
2101 case InstCast::Fptoui: 2101 case InstCast::Fptoui:
2102 if (isVectorType(Dest->getType())) { 2102 if (isVectorType(Dest->getType())) {
2103 assert(Dest->getType() == IceType_v4i32 && 2103 assert(Dest->getType() == IceType_v4i32 &&
2104 Inst->getSrc(0)->getType() == IceType_v4f32); 2104 Inst->getSrc(0)->getType() == IceType_v4f32);
(...skipping 15 matching lines...) Expand all
2120 // TODO: Call the correct compiler-rt helper function. 2120 // TODO: Call the correct compiler-rt helper function.
2121 InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs); 2121 InstCall *Call = makeHelperCall(TargetString, Dest, MaxSrcs);
2122 Call->addArg(Inst->getSrc(0)); 2122 Call->addArg(Inst->getSrc(0));
2123 lowerCall(Call); 2123 lowerCall(Call);
2124 return; 2124 return;
2125 } else { 2125 } else {
2126 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2126 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2127 // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type 2127 // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
2128 Variable *T_1 = makeReg(IceType_i32); 2128 Variable *T_1 = makeReg(IceType_i32);
2129 Variable *T_2 = makeReg(Dest->getType()); 2129 Variable *T_2 = makeReg(Dest->getType());
2130 _cvtt(T_1, Src0RM); 2130 _cvt(T_1, Src0RM, InstX8632Cvt::Tss2si);
2131 _mov(T_2, T_1); // T_1 and T_2 may have different integer types 2131 _mov(T_2, T_1); // T_1 and T_2 may have different integer types
2132 if (Dest->getType() == IceType_i1) 2132 if (Dest->getType() == IceType_i1)
2133 _and(T_2, Ctx->getConstantInt32(IceType_i1, 1)); 2133 _and(T_2, Ctx->getConstantInt32(IceType_i1, 1));
2134 _mov(Dest, T_2); 2134 _mov(Dest, T_2);
2135 } 2135 }
2136 break; 2136 break;
2137 case InstCast::Sitofp: 2137 case InstCast::Sitofp:
2138 if (isVectorType(Dest->getType())) { 2138 if (isVectorType(Dest->getType())) {
2139 assert(Dest->getType() == IceType_v4f32 && 2139 assert(Dest->getType() == IceType_v4f32 &&
2140 Inst->getSrc(0)->getType() == IceType_v4i32); 2140 Inst->getSrc(0)->getType() == IceType_v4i32);
2141 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2141 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2142 Variable *T = makeReg(Dest->getType()); 2142 Variable *T = makeReg(Dest->getType());
2143 _cvt(T, Src0RM); 2143 _cvt(T, Src0RM, InstX8632Cvt::Dq2ps);
2144 _movp(Dest, T); 2144 _movp(Dest, T);
2145 } else if (Inst->getSrc(0)->getType() == IceType_i64) { 2145 } else if (Inst->getSrc(0)->getType() == IceType_i64) {
2146 // Use a helper for x86-32. 2146 // Use a helper for x86-32.
2147 const SizeT MaxSrcs = 1; 2147 const SizeT MaxSrcs = 1;
2148 Type DestType = Dest->getType(); 2148 Type DestType = Dest->getType();
2149 InstCall *Call = makeHelperCall( 2149 InstCall *Call = makeHelperCall(
2150 isFloat32Asserting32Or64(DestType) ? "cvtsi64tof" : "cvtsi64tod", 2150 isFloat32Asserting32Or64(DestType) ? "cvtsi64tof" : "cvtsi64tod",
2151 Dest, MaxSrcs); 2151 Dest, MaxSrcs);
2152 // TODO: Call the correct compiler-rt helper function. 2152 // TODO: Call the correct compiler-rt helper function.
2153 Call->addArg(Inst->getSrc(0)); 2153 Call->addArg(Inst->getSrc(0));
2154 lowerCall(Call); 2154 lowerCall(Call);
2155 return; 2155 return;
2156 } else { 2156 } else {
2157 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem); 2157 Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
2158 // Sign-extend the operand. 2158 // Sign-extend the operand.
2159 // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2 2159 // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
2160 Variable *T_1 = makeReg(IceType_i32); 2160 Variable *T_1 = makeReg(IceType_i32);
2161 Variable *T_2 = makeReg(Dest->getType()); 2161 Variable *T_2 = makeReg(Dest->getType());
2162 if (Src0RM->getType() == IceType_i32) 2162 if (Src0RM->getType() == IceType_i32)
2163 _mov(T_1, Src0RM); 2163 _mov(T_1, Src0RM);
2164 else 2164 else
2165 _movsx(T_1, Src0RM); 2165 _movsx(T_1, Src0RM);
2166 _cvt(T_2, T_1); 2166 _cvt(T_2, T_1, InstX8632Cvt::Si2ss);
2167 _mov(Dest, T_2); 2167 _mov(Dest, T_2);
2168 } 2168 }
2169 break; 2169 break;
2170 case InstCast::Uitofp: { 2170 case InstCast::Uitofp: {
2171 Operand *Src0 = Inst->getSrc(0); 2171 Operand *Src0 = Inst->getSrc(0);
2172 if (isVectorType(Src0->getType())) { 2172 if (isVectorType(Src0->getType())) {
2173 assert(Dest->getType() == IceType_v4f32 && 2173 assert(Dest->getType() == IceType_v4f32 &&
2174 Src0->getType() == IceType_v4i32); 2174 Src0->getType() == IceType_v4i32);
2175 const SizeT MaxSrcs = 1; 2175 const SizeT MaxSrcs = 1;
2176 InstCall *Call = makeHelperCall("Sz_uitofp_v4i32", Dest, MaxSrcs); 2176 InstCall *Call = makeHelperCall("Sz_uitofp_v4i32", Dest, MaxSrcs);
(...skipping 18 matching lines...) Expand all
2195 } else { 2195 } else {
2196 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); 2196 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
2197 // Zero-extend the operand. 2197 // Zero-extend the operand.
2198 // t1.i32 = movzx Src0RM; t2 = Cvt t1.i32; Dest = t2 2198 // t1.i32 = movzx Src0RM; t2 = Cvt t1.i32; Dest = t2
2199 Variable *T_1 = makeReg(IceType_i32); 2199 Variable *T_1 = makeReg(IceType_i32);
2200 Variable *T_2 = makeReg(Dest->getType()); 2200 Variable *T_2 = makeReg(Dest->getType());
2201 if (Src0RM->getType() == IceType_i32) 2201 if (Src0RM->getType() == IceType_i32)
2202 _mov(T_1, Src0RM); 2202 _mov(T_1, Src0RM);
2203 else 2203 else
2204 _movzx(T_1, Src0RM); 2204 _movzx(T_1, Src0RM);
2205 _cvt(T_2, T_1); 2205 _cvt(T_2, T_1, InstX8632Cvt::Si2ss);
2206 _mov(Dest, T_2); 2206 _mov(Dest, T_2);
2207 } 2207 }
2208 break; 2208 break;
2209 } 2209 }
2210 case InstCast::Bitcast: { 2210 case InstCast::Bitcast: {
2211 Operand *Src0 = Inst->getSrc(0); 2211 Operand *Src0 = Inst->getSrc(0);
2212 if (Dest->getType() == Src0->getType()) { 2212 if (Dest->getType() == Src0->getType()) {
2213 InstAssign *Assign = InstAssign::create(Func, Dest, Src0); 2213 InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
2214 lowerAssign(Assign); 2214 lowerAssign(Assign);
2215 return; 2215 return;
(...skipping 2308 matching lines...) Expand 10 before | Expand all | Expand 10 after
4524 } else if (IsConstant || IsExternal) 4524 } else if (IsConstant || IsExternal)
4525 Str << "\t.zero\t" << Size << "\n"; 4525 Str << "\t.zero\t" << Size << "\n";
4526 // Size is part of .comm. 4526 // Size is part of .comm.
4527 4527
4528 if (IsConstant || HasInitializer || IsExternal) 4528 if (IsConstant || HasInitializer || IsExternal)
4529 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; 4529 Str << "\t.size\t" << MangledName << ", " << Size << "\n";
4530 // Size is part of .comm. 4530 // Size is part of .comm.
4531 } 4531 }
4532 4532
4533 } // end of namespace Ice 4533 } // end of namespace Ice
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