ath9k: Add pktlog support

chromeos/compat-wireless/drivers/net/wireless/ath/ath9k/hw.h

 /*
  * Copyright (c) 2008-2010 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ skipping 596 matching lines @@
         bool (*calibrate)(struct ath_hw *ah,
                           struct ath9k_channel *chan,
                           u8 rxchainmask,
                           bool longcal);
         bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
         void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
                             bool is_firstseg, bool is_is_lastseg,
                             const void *ds0, dma_addr_t buf_addr,
                             unsigned int qcu);
         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
-                           struct ath_tx_status *ts);
+                           struct ath_tx_status *ts, void* txs_desc);
         void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
                               u32 pktLen, enum ath9k_pkt_type type,
                               u32 txPower, u32 keyIx,
                               enum ath9k_key_type keyType,
                               u32 flags);
         void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
                                 void *lastds,
                                 u32 durUpdateEn, u32 rtsctsRate,
                                 u32 rtsctsDuration,
                                 struct ath9k_11n_rate_series series[],
@@ skipping 214 matching lines @@
         bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
          * Store the permanent value of Reg 0x4004in WARegVal
          * so we dont have to R/M/W. We should not be reading
          * this register when in sleep states.
          */
         u32 WARegVal;
 
+        bool is_pkt_logging;
+
         /* Enterprise mode cap */
         u32 ent_mode;
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
 {
         return &ah->common;
 }
 
 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
@@ skipping 156 matching lines @@
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1
 #define ATH_PCIE_CAP_LINK_L1    2
 
 #define ATH9K_CLOCK_RATE_CCK            22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
 
 #endif