Implement bigint mulAdd and sqrAdd intrinsics on ARM.

runtime/vm/disassembler_arm.cc

Index: runtime/vm/disassembler_arm.cc
===================================================================
--- runtime/vm/disassembler_arm.cc	(revision 40991)
+++ runtime/vm/disassembler_arm.cc	(working copy)
@@ -714,6 +714,11 @@
             Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
             break;
           }
+          case 2: {
+            // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+            Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
+            break;
+          }
           case 3: {
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");