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Issue 638983002: Implement bigint mulAdd and sqrAdd intrinsics on ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <setjmp.h> 5 #include <setjmp.h>
6 #include <stdlib.h> 6 #include <stdlib.h>
7 7
8 #include "vm/globals.h" 8 #include "vm/globals.h"
9 #if defined(TARGET_ARCH_ARM) 9 #if defined(TARGET_ARCH_ARM)
10 10
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1746 case 4: 1746 case 4:
1747 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 1747 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1748 // Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs"); 1748 // Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
1749 case 6: { 1749 case 6: {
1750 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 1750 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1751 // Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs"); 1751 // Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs");
1752 int64_t result; 1752 int64_t result;
1753 if (instr->Bits(21, 3) == 4) { // umull 1753 if (instr->Bits(21, 3) == 4) { // umull
1754 uint64_t left_op = static_cast<uint32_t>(rm_val); 1754 uint64_t left_op = static_cast<uint32_t>(rm_val);
1755 uint64_t right_op = static_cast<uint32_t>(rs_val); 1755 uint64_t right_op = static_cast<uint32_t>(rs_val);
1756 result = left_op * right_op; // Unsigned nultiplication. 1756 result = left_op * right_op; // Unsigned multiplication.
1757 } else { // smull 1757 } else { // smull
1758 int64_t left_op = static_cast<int32_t>(rm_val); 1758 int64_t left_op = static_cast<int32_t>(rm_val);
1759 int64_t right_op = static_cast<int32_t>(rs_val); 1759 int64_t right_op = static_cast<int32_t>(rs_val);
1760 result = left_op * right_op; // Signed nultiplication. 1760 result = left_op * right_op; // Signed multiplication.
1761 } 1761 }
1762 int32_t hi_res = Utils::High32Bits(result); 1762 int32_t hi_res = Utils::High32Bits(result);
1763 int32_t lo_res = Utils::Low32Bits(result); 1763 int32_t lo_res = Utils::Low32Bits(result);
1764 set_register(rd, lo_res); 1764 set_register(rd, lo_res);
1765 set_register(rn, hi_res); 1765 set_register(rn, hi_res);
1766 if (instr->HasS()) { 1766 if (instr->HasS()) {
1767 if (lo_res != 0) { 1767 if (lo_res != 0) {
1768 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works. 1768 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
1769 hi_res |= 1; 1769 hi_res |= 1;
1770 } 1770 }
1771 ASSERT((result == 0) == (hi_res == 0)); // Z bit 1771 ASSERT((result == 0) == (hi_res == 0)); // Z bit
1772 ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit 1772 ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit
1773 SetNZFlags(hi_res); 1773 SetNZFlags(hi_res);
1774 } 1774 }
1775 break; 1775 break;
1776 } 1776 }
1777 case 2:
1778 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1779 // Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
1777 case 5: 1780 case 5:
1778 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 1781 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1779 // Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs"); 1782 // Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs");
1780 case 7: { 1783 case 7: {
1781 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 1784 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
1782 // Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs"); 1785 // Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs");
1783 int32_t rd_lo_val = get_register(rd); 1786 int32_t rd_lo_val = get_register(rd);
1784 int32_t rd_hi_val = get_register(rn); 1787 int32_t rd_hi_val = get_register(rn);
1785 uint32_t accum_lo = static_cast<uint32_t>(rd_lo_val); 1788 uint32_t accum_lo = static_cast<uint32_t>(rd_lo_val);
1786 int32_t accum_hi = static_cast<int32_t>(rd_hi_val); 1789 int32_t accum_hi = static_cast<int32_t>(rd_hi_val);
1787 int64_t accum = Utils::LowHighTo64Bits(accum_lo, accum_hi); 1790 int64_t accum = Utils::LowHighTo64Bits(accum_lo, accum_hi);
1788 int64_t result; 1791 int64_t result;
1789 if (instr->Bits(21, 3) == 5) { // umlal 1792 if (instr->Bits(21, 3) == 5) { // umlal
1790 uint64_t left_op = static_cast<uint32_t>(rm_val); 1793 uint64_t left_op = static_cast<uint32_t>(rm_val);
1791 uint64_t right_op = static_cast<uint32_t>(rs_val); 1794 uint64_t right_op = static_cast<uint32_t>(rs_val);
1792 result = accum + left_op * right_op; // Unsigned nultiplication. 1795 result = accum + left_op * right_op; // Unsigned multiplication.
1793 } else { // smlal 1796 } else if (instr->Bits(21, 3) == 7) { // smlal
1794 int64_t left_op = static_cast<int32_t>(rm_val); 1797 int64_t left_op = static_cast<int32_t>(rm_val);
1795 int64_t right_op = static_cast<int32_t>(rs_val); 1798 int64_t right_op = static_cast<int32_t>(rs_val);
1796 result = accum + left_op * right_op; // Signed nultiplication. 1799 result = accum + left_op * right_op; // Signed multiplication.
1800 } else {
1801 ASSERT(instr->Bits(21, 3) == 2); // umaal
1802 ASSERT(!instr->HasS());
1803 uint64_t left_op = static_cast<uint32_t>(rm_val);
1804 uint64_t right_op = static_cast<uint32_t>(rs_val);
1805 result = left_op * right_op + // Unsigned multiplication.
1806 static_cast<uint32_t>(rd_lo_val) +
1807 static_cast<uint32_t>(rd_hi_val);
1797 } 1808 }
1798 int32_t hi_res = Utils::High32Bits(result); 1809 int32_t hi_res = Utils::High32Bits(result);
1799 int32_t lo_res = Utils::Low32Bits(result); 1810 int32_t lo_res = Utils::Low32Bits(result);
1800 set_register(rd, lo_res); 1811 set_register(rd, lo_res);
1801 set_register(rn, hi_res); 1812 set_register(rn, hi_res);
1802 if (instr->HasS()) { 1813 if (instr->HasS()) {
1803 if (lo_res != 0) { 1814 if (lo_res != 0) {
1804 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works. 1815 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
1805 hi_res |= 1; 1816 hi_res |= 1;
1806 } 1817 }
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3848 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); 3859 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
3849 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); 3860 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
3850 buf->Longjmp(); 3861 buf->Longjmp();
3851 } 3862 }
3852 3863
3853 } // namespace dart 3864 } // namespace dart
3854 3865
3855 #endif // !defined(HOST_ARCH_ARM) 3866 #endif // !defined(HOST_ARCH_ARM)
3856 3867
3857 #endif // defined TARGET_ARCH_ARM 3868 #endif // defined TARGET_ARCH_ARM
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