Implement bigint mulAdd and sqrAdd intrinsics on ARM.

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "platform/assert.h"
@@ skipping 696 matching lines @@
           case 0: {
             // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
             Format(instr, "mul'cond's 'rn, 'rm, 'rs");
             break;
           }
           case 1: {
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
             break;
           }
+          case 2: {
+            // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+            Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
+            break;
+          }
           case 3: {
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
             break;
           }
           case 4: {
             // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
             Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
             break;
           }
@@ skipping 826 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM